xref: /openbmc/u-boot/board/phytec/pcl063/pcl063.c (revision db4a2999)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2018 Collabora Ltd.
4  *
5  * Based on board/ccv/xpress/xpress.c:
6  * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
7  */
8 
9 #include <asm/arch/clock.h>
10 #include <asm/arch/crm_regs.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/mach-imx/iomux-v3.h>
14 #include <asm/mach-imx/mxc_i2c.h>
15 #include <fsl_esdhc.h>
16 #include <linux/bitops.h>
17 #include <miiphy.h>
18 #include <netdev.h>
19 #include <usb.h>
20 #include <usb/ehci-ci.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
dram_init(void)24 int dram_init(void)
25 {
26 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
27 
28 	return 0;
29 }
30 
31 #define UART_PAD_CTRL  (PAD_CTL_PKE         | PAD_CTL_PUE       | \
32 			PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
33 			PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | \
34 			PAD_CTL_HYS)
35 
36 static iomux_v3_cfg_t const uart1_pads[] = {
37 	MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
38 	MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
39 };
40 
41 static iomux_v3_cfg_t const uart5_pads[] = {
42 	MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
43 	MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
44 	MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
45 	MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
46 };
47 
setup_iomux_uart(void)48 static void setup_iomux_uart(void)
49 {
50 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
51 	imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
52 }
53 
54 #ifdef CONFIG_NAND_MXS
55 
56 #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
57 
58 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
59 
60 #define NANDREADYPC MUX_PAD_CTRL(NAND_PAD_READY0_CTRL)
61 
62 static iomux_v3_cfg_t const gpmi_pads[] = {
63 	MX6_PAD_NAND_DATA00__RAWNAND_DATA00	| MUX_PAD_CTRL(NAND_PAD_CTRL),
64 	MX6_PAD_NAND_DATA01__RAWNAND_DATA01	| MUX_PAD_CTRL(NAND_PAD_CTRL),
65 	MX6_PAD_NAND_DATA02__RAWNAND_DATA02	| MUX_PAD_CTRL(NAND_PAD_CTRL),
66 	MX6_PAD_NAND_DATA03__RAWNAND_DATA03	| MUX_PAD_CTRL(NAND_PAD_CTRL),
67 	MX6_PAD_NAND_DATA04__RAWNAND_DATA04	| MUX_PAD_CTRL(NAND_PAD_CTRL),
68 	MX6_PAD_NAND_DATA05__RAWNAND_DATA05	| MUX_PAD_CTRL(NAND_PAD_CTRL),
69 	MX6_PAD_NAND_DATA06__RAWNAND_DATA06	| MUX_PAD_CTRL(NAND_PAD_CTRL),
70 	MX6_PAD_NAND_DATA07__RAWNAND_DATA07	| MUX_PAD_CTRL(NAND_PAD_CTRL),
71 	MX6_PAD_NAND_CLE__RAWNAND_CLE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
72 	MX6_PAD_NAND_ALE__RAWNAND_ALE		| MUX_PAD_CTRL(NAND_PAD_CTRL),
73 	MX6_PAD_NAND_RE_B__RAWNAND_RE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
74 	MX6_PAD_NAND_WE_B__RAWNAND_WE_B		| MUX_PAD_CTRL(NAND_PAD_CTRL),
75 	MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
76 	MX6_PAD_NAND_READY_B__RAWNAND_READY_B	| NANDREADYPC,
77 };
78 
setup_gpmi_nand(void)79 static void setup_gpmi_nand(void)
80 {
81 	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
82 
83 	setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
84 			  (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
85 }
86 
87 #endif /* CONFIG_NAND_MXS */
88 
89 #ifdef CONFIG_FEC_MXC
90 
91 #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
92 
93 #define ENET_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE       | \
94 			   PAD_CTL_SPEED_HIGH  | PAD_CTL_DSE_48ohm | \
95 			   PAD_CTL_SRE_FAST)
96 
97 #define MDIO_PAD_CTRL     (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE      | \
98 			   PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | \
99 			   PAD_CTL_ODE)
100 
101 static iomux_v3_cfg_t const fec1_pads[] = {
102 	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
103 	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
104 	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
105 	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
106 	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
107 	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
108 	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
109 	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
110 	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
111 	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
112 };
113 
114 static iomux_v3_cfg_t const fec2_pads[] = {
115 	MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 	MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 	MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 	MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
119 	MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 	MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 	MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 	MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 };
124 
setup_iomux_fec(void)125 static void setup_iomux_fec(void)
126 {
127 	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
128 	imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
129 }
130 
setup_fec(void)131 static int setup_fec(void)
132 {
133 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
134 	int ret;
135 
136 	/*
137 	 * Use 50M anatop loopback REF_CLK1 for ENET1,
138 	 * clear gpr1[13], set gpr1[17].
139 	 */
140 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
141 			IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
142 
143 	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
144 	if (ret)
145 		return ret;
146 
147 	/*
148 	 * Use 50M anatop loopback REF_CLK2 for ENET2,
149 	 * clear gpr1[14], set gpr1[18].
150 	 */
151 	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
152 			IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
153 
154 	ret = enable_fec_anatop_clock(1, ENET_50MHZ);
155 	if (ret)
156 		return ret;
157 
158 	enable_enet_clk(1);
159 
160 	return 0;
161 }
162 
board_phy_config(struct phy_device * phydev)163 int board_phy_config(struct phy_device *phydev)
164 {
165 	/*
166 	 * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
167 	 * 50 MHz RMII clock mode.
168 	 */
169 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
170 
171 	if (phydev->drv->config)
172 		phydev->drv->config(phydev);
173 
174 	return 0;
175 }
176 #endif /* CONFIG_FEC_MXC */
177 
board_early_init_f(void)178 int board_early_init_f(void)
179 {
180 	setup_iomux_uart();
181 	setup_iomux_fec();
182 
183 	return 0;
184 }
185 
board_init(void)186 int board_init(void)
187 {
188 	/* Address of boot parameters */
189 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
190 
191 #ifdef CONFIG_NAND_MXS
192 	setup_gpmi_nand();
193 #endif
194 
195 #ifdef CONFIG_FEC_MXC
196 	setup_fec();
197 #endif
198 	return 0;
199 }
200 
checkboard(void)201 int checkboard(void)
202 {
203 	puts("Board: PHYTEC phyCORE-i.MX6UL\n");
204 
205 	return 0;
206 }
207