xref: /openbmc/linux/drivers/hwmon/jc42.c (revision 1975d167)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
4  *
5  * Copyright (c) 2010  Ericsson AB.
6  *
7  * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
8  *
9  * JC42.4 compliant temperature sensors are typically used on memory modules.
10  */
11 
12 #include <linux/bitops.h>
13 #include <linux/bitfield.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/slab.h>
17 #include <linux/jiffies.h>
18 #include <linux/i2c.h>
19 #include <linux/hwmon.h>
20 #include <linux/err.h>
21 #include <linux/mutex.h>
22 #include <linux/of.h>
23 #include <linux/regmap.h>
24 
25 /* Addresses to scan */
26 static const unsigned short normal_i2c[] = {
27 	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
28 
29 /* JC42 registers. All registers are 16 bit. */
30 #define JC42_REG_CAP		0x00
31 #define JC42_REG_CONFIG		0x01
32 #define JC42_REG_TEMP_UPPER	0x02
33 #define JC42_REG_TEMP_LOWER	0x03
34 #define JC42_REG_TEMP_CRITICAL	0x04
35 #define JC42_REG_TEMP		0x05
36 #define JC42_REG_MANID		0x06
37 #define JC42_REG_DEVICEID	0x07
38 #define JC42_REG_SMBUS		0x22 /* NXP and Atmel, possibly others? */
39 
40 /* Status bits in temperature register */
41 #define JC42_ALARM_CRIT		BIT(15)
42 #define JC42_ALARM_MAX		BIT(14)
43 #define JC42_ALARM_MIN		BIT(13)
44 
45 /* Configuration register defines */
46 #define JC42_CFG_CRIT_ONLY	BIT(2)
47 #define JC42_CFG_TCRIT_LOCK	BIT(6)
48 #define JC42_CFG_EVENT_LOCK	BIT(7)
49 #define JC42_CFG_SHUTDOWN	BIT(8)
50 #define JC42_CFG_HYST_MASK	GENMASK(10, 9)
51 
52 /* Capabilities */
53 #define JC42_CAP_RANGE		BIT(2)
54 
55 /* Manufacturer IDs */
56 #define ADT_MANID		0x11d4  /* Analog Devices */
57 #define ATMEL_MANID		0x001f  /* Atmel */
58 #define ATMEL_MANID2		0x1114	/* Atmel */
59 #define MAX_MANID		0x004d  /* Maxim */
60 #define IDT_MANID		0x00b3  /* IDT */
61 #define MCP_MANID		0x0054  /* Microchip */
62 #define NXP_MANID		0x1131  /* NXP Semiconductors */
63 #define ONS_MANID		0x1b09  /* ON Semiconductor */
64 #define STM_MANID		0x104a  /* ST Microelectronics */
65 #define GT_MANID		0x1c68	/* Giantec */
66 #define GT_MANID2		0x132d	/* Giantec, 2nd mfg ID */
67 #define SI_MANID		0x1c85	/* Seiko Instruments */
68 
69 /* SMBUS register */
70 #define SMBUS_STMOUT		BIT(7)  /* SMBus time-out, active low */
71 
72 /* Supported chips */
73 
74 /* Analog Devices */
75 #define ADT7408_DEVID		0x0801
76 #define ADT7408_DEVID_MASK	0xffff
77 
78 /* Atmel */
79 #define AT30TS00_DEVID		0x8201
80 #define AT30TS00_DEVID_MASK	0xffff
81 
82 #define AT30TSE004_DEVID	0x2200
83 #define AT30TSE004_DEVID_MASK	0xffff
84 
85 /* Giantec */
86 #define GT30TS00_DEVID		0x2200
87 #define GT30TS00_DEVID_MASK	0xff00
88 
89 #define GT34TS02_DEVID		0x3300
90 #define GT34TS02_DEVID_MASK	0xff00
91 
92 /* IDT */
93 #define TSE2004_DEVID		0x2200
94 #define TSE2004_DEVID_MASK	0xff00
95 
96 #define TS3000_DEVID		0x2900  /* Also matches TSE2002 */
97 #define TS3000_DEVID_MASK	0xff00
98 
99 #define TS3001_DEVID		0x3000
100 #define TS3001_DEVID_MASK	0xff00
101 
102 /* Maxim */
103 #define MAX6604_DEVID		0x3e00
104 #define MAX6604_DEVID_MASK	0xffff
105 
106 /* Microchip */
107 #define MCP9804_DEVID		0x0200
108 #define MCP9804_DEVID_MASK	0xfffc
109 
110 #define MCP9808_DEVID		0x0400
111 #define MCP9808_DEVID_MASK	0xfffc
112 
113 #define MCP98242_DEVID		0x2000
114 #define MCP98242_DEVID_MASK	0xfffc
115 
116 #define MCP98243_DEVID		0x2100
117 #define MCP98243_DEVID_MASK	0xfffc
118 
119 #define MCP98244_DEVID		0x2200
120 #define MCP98244_DEVID_MASK	0xfffc
121 
122 #define MCP9843_DEVID		0x0000	/* Also matches mcp9805 */
123 #define MCP9843_DEVID_MASK	0xfffe
124 
125 /* NXP */
126 #define SE97_DEVID		0xa200
127 #define SE97_DEVID_MASK		0xfffc
128 
129 #define SE98_DEVID		0xa100
130 #define SE98_DEVID_MASK		0xfffc
131 
132 /* ON Semiconductor */
133 #define CAT6095_DEVID		0x0800	/* Also matches CAT34TS02 */
134 #define CAT6095_DEVID_MASK	0xffe0
135 
136 #define CAT34TS02C_DEVID	0x0a00
137 #define CAT34TS02C_DEVID_MASK	0xfff0
138 
139 #define CAT34TS04_DEVID		0x2200
140 #define CAT34TS04_DEVID_MASK	0xfff0
141 
142 #define N34TS04_DEVID		0x2230
143 #define N34TS04_DEVID_MASK	0xfff0
144 
145 /* ST Microelectronics */
146 #define STTS424_DEVID		0x0101
147 #define STTS424_DEVID_MASK	0xffff
148 
149 #define STTS424E_DEVID		0x0000
150 #define STTS424E_DEVID_MASK	0xfffe
151 
152 #define STTS2002_DEVID		0x0300
153 #define STTS2002_DEVID_MASK	0xffff
154 
155 #define STTS2004_DEVID		0x2201
156 #define STTS2004_DEVID_MASK	0xffff
157 
158 #define STTS3000_DEVID		0x0200
159 #define STTS3000_DEVID_MASK	0xffff
160 
161 /* Seiko Instruments */
162 #define S34TS04A_DEVID		0x2221
163 #define S34TS04A_DEVID_MASK	0xffff
164 
165 static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
166 
167 struct jc42_chips {
168 	u16 manid;
169 	u16 devid;
170 	u16 devid_mask;
171 };
172 
173 static struct jc42_chips jc42_chips[] = {
174 	{ ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
175 	{ ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
176 	{ ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
177 	{ GT_MANID, GT30TS00_DEVID, GT30TS00_DEVID_MASK },
178 	{ GT_MANID2, GT34TS02_DEVID, GT34TS02_DEVID_MASK },
179 	{ IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
180 	{ IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
181 	{ IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
182 	{ MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
183 	{ MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
184 	{ MCP_MANID, MCP9808_DEVID, MCP9808_DEVID_MASK },
185 	{ MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
186 	{ MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
187 	{ MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
188 	{ MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
189 	{ NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
190 	{ ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
191 	{ ONS_MANID, CAT34TS02C_DEVID, CAT34TS02C_DEVID_MASK },
192 	{ ONS_MANID, CAT34TS04_DEVID, CAT34TS04_DEVID_MASK },
193 	{ ONS_MANID, N34TS04_DEVID, N34TS04_DEVID_MASK },
194 	{ NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
195 	{ SI_MANID,  S34TS04A_DEVID, S34TS04A_DEVID_MASK },
196 	{ STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
197 	{ STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
198 	{ STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
199 	{ STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
200 	{ STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
201 };
202 
203 /* Each client has this additional data */
204 struct jc42_data {
205 	struct mutex	update_lock;	/* protect register access */
206 	struct regmap	*regmap;
207 	bool		extended;	/* true if extended range supported */
208 	bool		valid;
209 	u16		orig_config;	/* original configuration */
210 	u16		config;		/* current configuration */
211 };
212 
213 #define JC42_TEMP_MIN_EXTENDED	(-40000)
214 #define JC42_TEMP_MIN		0
215 #define JC42_TEMP_MAX		125000
216 
jc42_temp_to_reg(long temp,bool extended)217 static u16 jc42_temp_to_reg(long temp, bool extended)
218 {
219 	int ntemp = clamp_val(temp,
220 			      extended ? JC42_TEMP_MIN_EXTENDED :
221 			      JC42_TEMP_MIN, JC42_TEMP_MAX);
222 
223 	/* convert from 0.001 to 0.0625 resolution */
224 	return (ntemp * 2 / 125) & 0x1fff;
225 }
226 
jc42_temp_from_reg(s16 reg)227 static int jc42_temp_from_reg(s16 reg)
228 {
229 	reg = sign_extend32(reg, 12);
230 
231 	/* convert from 0.0625 to 0.001 resolution */
232 	return reg * 125 / 2;
233 }
234 
jc42_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)235 static int jc42_read(struct device *dev, enum hwmon_sensor_types type,
236 		     u32 attr, int channel, long *val)
237 {
238 	struct jc42_data *data = dev_get_drvdata(dev);
239 	unsigned int regval;
240 	int ret, temp, hyst;
241 
242 	mutex_lock(&data->update_lock);
243 
244 	switch (attr) {
245 	case hwmon_temp_input:
246 		ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);
247 		if (ret)
248 			break;
249 
250 		*val = jc42_temp_from_reg(regval);
251 		break;
252 	case hwmon_temp_min:
253 		ret = regmap_read(data->regmap, JC42_REG_TEMP_LOWER, &regval);
254 		if (ret)
255 			break;
256 
257 		*val = jc42_temp_from_reg(regval);
258 		break;
259 	case hwmon_temp_max:
260 		ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, &regval);
261 		if (ret)
262 			break;
263 
264 		*val = jc42_temp_from_reg(regval);
265 		break;
266 	case hwmon_temp_crit:
267 		ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
268 				  &regval);
269 		if (ret)
270 			break;
271 
272 		*val = jc42_temp_from_reg(regval);
273 		break;
274 	case hwmon_temp_max_hyst:
275 		ret = regmap_read(data->regmap, JC42_REG_TEMP_UPPER, &regval);
276 		if (ret)
277 			break;
278 
279 		temp = jc42_temp_from_reg(regval);
280 		hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK,
281 						 data->config)];
282 		*val = temp - hyst;
283 		break;
284 	case hwmon_temp_crit_hyst:
285 		ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
286 				  &regval);
287 		if (ret)
288 			break;
289 
290 		temp = jc42_temp_from_reg(regval);
291 		hyst = jc42_hysteresis[FIELD_GET(JC42_CFG_HYST_MASK,
292 						 data->config)];
293 		*val = temp - hyst;
294 		break;
295 	case hwmon_temp_min_alarm:
296 		ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);
297 		if (ret)
298 			break;
299 
300 		*val = FIELD_GET(JC42_ALARM_MIN, regval);
301 		break;
302 	case hwmon_temp_max_alarm:
303 		ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);
304 		if (ret)
305 			break;
306 
307 		*val = FIELD_GET(JC42_ALARM_MAX, regval);
308 		break;
309 	case hwmon_temp_crit_alarm:
310 		ret = regmap_read(data->regmap, JC42_REG_TEMP, &regval);
311 		if (ret)
312 			break;
313 
314 		*val = FIELD_GET(JC42_ALARM_CRIT, regval);
315 		break;
316 	default:
317 		ret = -EOPNOTSUPP;
318 		break;
319 	}
320 
321 	mutex_unlock(&data->update_lock);
322 
323 	return ret;
324 }
325 
jc42_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)326 static int jc42_write(struct device *dev, enum hwmon_sensor_types type,
327 		      u32 attr, int channel, long val)
328 {
329 	struct jc42_data *data = dev_get_drvdata(dev);
330 	unsigned int regval;
331 	int diff, hyst;
332 	int ret;
333 
334 	mutex_lock(&data->update_lock);
335 
336 	switch (attr) {
337 	case hwmon_temp_min:
338 		ret = regmap_write(data->regmap, JC42_REG_TEMP_LOWER,
339 				   jc42_temp_to_reg(val, data->extended));
340 		break;
341 	case hwmon_temp_max:
342 		ret = regmap_write(data->regmap, JC42_REG_TEMP_UPPER,
343 				   jc42_temp_to_reg(val, data->extended));
344 		break;
345 	case hwmon_temp_crit:
346 		ret = regmap_write(data->regmap, JC42_REG_TEMP_CRITICAL,
347 				   jc42_temp_to_reg(val, data->extended));
348 		break;
349 	case hwmon_temp_crit_hyst:
350 		ret = regmap_read(data->regmap, JC42_REG_TEMP_CRITICAL,
351 				  &regval);
352 		if (ret)
353 			break;
354 
355 		/*
356 		 * JC42.4 compliant chips only support four hysteresis values.
357 		 * Pick best choice and go from there.
358 		 */
359 		val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED
360 						     : JC42_TEMP_MIN) - 6000,
361 				JC42_TEMP_MAX);
362 		diff = jc42_temp_from_reg(regval) - val;
363 		hyst = 0;
364 		if (diff > 0) {
365 			if (diff < 2250)
366 				hyst = 1;	/* 1.5 degrees C */
367 			else if (diff < 4500)
368 				hyst = 2;	/* 3.0 degrees C */
369 			else
370 				hyst = 3;	/* 6.0 degrees C */
371 		}
372 		data->config = (data->config & ~JC42_CFG_HYST_MASK) |
373 				FIELD_PREP(JC42_CFG_HYST_MASK, hyst);
374 		ret = regmap_write(data->regmap, JC42_REG_CONFIG,
375 				   data->config);
376 		break;
377 	default:
378 		ret = -EOPNOTSUPP;
379 		break;
380 	}
381 
382 	mutex_unlock(&data->update_lock);
383 
384 	return ret;
385 }
386 
jc42_is_visible(const void * _data,enum hwmon_sensor_types type,u32 attr,int channel)387 static umode_t jc42_is_visible(const void *_data, enum hwmon_sensor_types type,
388 			       u32 attr, int channel)
389 {
390 	const struct jc42_data *data = _data;
391 	unsigned int config = data->config;
392 	umode_t mode = 0444;
393 
394 	switch (attr) {
395 	case hwmon_temp_min:
396 	case hwmon_temp_max:
397 		if (!(config & JC42_CFG_EVENT_LOCK))
398 			mode |= 0200;
399 		break;
400 	case hwmon_temp_crit:
401 		if (!(config & JC42_CFG_TCRIT_LOCK))
402 			mode |= 0200;
403 		break;
404 	case hwmon_temp_crit_hyst:
405 		if (!(config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK)))
406 			mode |= 0200;
407 		break;
408 	case hwmon_temp_input:
409 	case hwmon_temp_max_hyst:
410 	case hwmon_temp_min_alarm:
411 	case hwmon_temp_max_alarm:
412 	case hwmon_temp_crit_alarm:
413 		break;
414 	default:
415 		mode = 0;
416 		break;
417 	}
418 	return mode;
419 }
420 
421 /* Return 0 if detection is successful, -ENODEV otherwise */
jc42_detect(struct i2c_client * client,struct i2c_board_info * info)422 static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
423 {
424 	struct i2c_adapter *adapter = client->adapter;
425 	int i, config, cap, manid, devid;
426 
427 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
428 				     I2C_FUNC_SMBUS_WORD_DATA))
429 		return -ENODEV;
430 
431 	cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
432 	config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
433 	manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
434 	devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
435 
436 	if (cap < 0 || config < 0 || manid < 0 || devid < 0)
437 		return -ENODEV;
438 
439 	if ((cap & 0xff00) || (config & 0xf800))
440 		return -ENODEV;
441 
442 	for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
443 		struct jc42_chips *chip = &jc42_chips[i];
444 		if (manid == chip->manid &&
445 		    (devid & chip->devid_mask) == chip->devid) {
446 			strscpy(info->type, "jc42", I2C_NAME_SIZE);
447 			return 0;
448 		}
449 	}
450 	return -ENODEV;
451 }
452 
453 static const struct hwmon_channel_info * const jc42_info[] = {
454 	HWMON_CHANNEL_INFO(chip,
455 			   HWMON_C_REGISTER_TZ | HWMON_C_UPDATE_INTERVAL),
456 	HWMON_CHANNEL_INFO(temp,
457 			   HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
458 			   HWMON_T_CRIT | HWMON_T_MAX_HYST |
459 			   HWMON_T_CRIT_HYST | HWMON_T_MIN_ALARM |
460 			   HWMON_T_MAX_ALARM | HWMON_T_CRIT_ALARM),
461 	NULL
462 };
463 
464 static const struct hwmon_ops jc42_hwmon_ops = {
465 	.is_visible = jc42_is_visible,
466 	.read = jc42_read,
467 	.write = jc42_write,
468 };
469 
470 static const struct hwmon_chip_info jc42_chip_info = {
471 	.ops = &jc42_hwmon_ops,
472 	.info = jc42_info,
473 };
474 
jc42_readable_reg(struct device * dev,unsigned int reg)475 static bool jc42_readable_reg(struct device *dev, unsigned int reg)
476 {
477 	return (reg >= JC42_REG_CAP && reg <= JC42_REG_DEVICEID) ||
478 		reg == JC42_REG_SMBUS;
479 }
480 
jc42_writable_reg(struct device * dev,unsigned int reg)481 static bool jc42_writable_reg(struct device *dev, unsigned int reg)
482 {
483 	return (reg >= JC42_REG_CONFIG && reg <= JC42_REG_TEMP_CRITICAL) ||
484 		reg == JC42_REG_SMBUS;
485 }
486 
jc42_volatile_reg(struct device * dev,unsigned int reg)487 static bool jc42_volatile_reg(struct device *dev, unsigned int reg)
488 {
489 	return reg == JC42_REG_CONFIG || reg == JC42_REG_TEMP;
490 }
491 
492 static const struct regmap_config jc42_regmap_config = {
493 	.reg_bits = 8,
494 	.val_bits = 16,
495 	.val_format_endian = REGMAP_ENDIAN_BIG,
496 	.max_register = JC42_REG_SMBUS,
497 	.writeable_reg = jc42_writable_reg,
498 	.readable_reg = jc42_readable_reg,
499 	.volatile_reg = jc42_volatile_reg,
500 	.cache_type = REGCACHE_RBTREE,
501 };
502 
jc42_probe(struct i2c_client * client)503 static int jc42_probe(struct i2c_client *client)
504 {
505 	struct device *dev = &client->dev;
506 	struct device *hwmon_dev;
507 	unsigned int config, cap;
508 	struct jc42_data *data;
509 	int ret;
510 
511 	data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
512 	if (!data)
513 		return -ENOMEM;
514 
515 	data->regmap = devm_regmap_init_i2c(client, &jc42_regmap_config);
516 	if (IS_ERR(data->regmap))
517 		return PTR_ERR(data->regmap);
518 
519 	i2c_set_clientdata(client, data);
520 	mutex_init(&data->update_lock);
521 
522 	ret = regmap_read(data->regmap, JC42_REG_CAP, &cap);
523 	if (ret)
524 		return ret;
525 
526 	data->extended = !!(cap & JC42_CAP_RANGE);
527 
528 	if (device_property_read_bool(dev, "smbus-timeout-disable")) {
529 		/*
530 		 * Not all chips support this register, but from a
531 		 * quick read of various datasheets no chip appears
532 		 * incompatible with the below attempt to disable
533 		 * the timeout. And the whole thing is opt-in...
534 		 */
535 		ret = regmap_set_bits(data->regmap, JC42_REG_SMBUS,
536 				      SMBUS_STMOUT);
537 		if (ret)
538 			return ret;
539 	}
540 
541 	ret = regmap_read(data->regmap, JC42_REG_CONFIG, &config);
542 	if (ret)
543 		return ret;
544 
545 	data->orig_config = config;
546 	if (config & JC42_CFG_SHUTDOWN) {
547 		config &= ~JC42_CFG_SHUTDOWN;
548 		regmap_write(data->regmap, JC42_REG_CONFIG, config);
549 	}
550 	data->config = config;
551 
552 	hwmon_dev = devm_hwmon_device_register_with_info(dev, "jc42",
553 							 data, &jc42_chip_info,
554 							 NULL);
555 	return PTR_ERR_OR_ZERO(hwmon_dev);
556 }
557 
jc42_remove(struct i2c_client * client)558 static void jc42_remove(struct i2c_client *client)
559 {
560 	struct jc42_data *data = i2c_get_clientdata(client);
561 
562 	/* Restore original configuration except hysteresis */
563 	if ((data->config & ~JC42_CFG_HYST_MASK) !=
564 	    (data->orig_config & ~JC42_CFG_HYST_MASK)) {
565 		int config;
566 
567 		config = (data->orig_config & ~JC42_CFG_HYST_MASK)
568 		  | (data->config & JC42_CFG_HYST_MASK);
569 		regmap_write(data->regmap, JC42_REG_CONFIG, config);
570 	}
571 }
572 
573 #ifdef CONFIG_PM
574 
jc42_suspend(struct device * dev)575 static int jc42_suspend(struct device *dev)
576 {
577 	struct jc42_data *data = dev_get_drvdata(dev);
578 
579 	data->config |= JC42_CFG_SHUTDOWN;
580 	regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
581 
582 	regcache_cache_only(data->regmap, true);
583 	regcache_mark_dirty(data->regmap);
584 
585 	return 0;
586 }
587 
jc42_resume(struct device * dev)588 static int jc42_resume(struct device *dev)
589 {
590 	struct jc42_data *data = dev_get_drvdata(dev);
591 
592 	regcache_cache_only(data->regmap, false);
593 
594 	data->config &= ~JC42_CFG_SHUTDOWN;
595 	regmap_write(data->regmap, JC42_REG_CONFIG, data->config);
596 
597 	/* Restore cached register values to hardware */
598 	return regcache_sync(data->regmap);
599 }
600 
601 static const struct dev_pm_ops jc42_dev_pm_ops = {
602 	.suspend = jc42_suspend,
603 	.resume = jc42_resume,
604 };
605 
606 #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
607 #else
608 #define JC42_DEV_PM_OPS NULL
609 #endif /* CONFIG_PM */
610 
611 static const struct i2c_device_id jc42_id[] = {
612 	{ "jc42", 0 },
613 	{ }
614 };
615 MODULE_DEVICE_TABLE(i2c, jc42_id);
616 
617 #ifdef CONFIG_OF
618 static const struct of_device_id jc42_of_ids[] = {
619 	{ .compatible = "jedec,jc-42.4-temp", },
620 	{ }
621 };
622 MODULE_DEVICE_TABLE(of, jc42_of_ids);
623 #endif
624 
625 static struct i2c_driver jc42_driver = {
626 	.class		= I2C_CLASS_SPD | I2C_CLASS_HWMON,
627 	.driver = {
628 		.name	= "jc42",
629 		.pm = JC42_DEV_PM_OPS,
630 		.of_match_table = of_match_ptr(jc42_of_ids),
631 	},
632 	.probe		= jc42_probe,
633 	.remove		= jc42_remove,
634 	.id_table	= jc42_id,
635 	.detect		= jc42_detect,
636 	.address_list	= normal_i2c,
637 };
638 
639 module_i2c_driver(jc42_driver);
640 
641 MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
642 MODULE_DESCRIPTION("JC42 driver");
643 MODULE_LICENSE("GPL");
644