1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * JZ4780 PLL setup 4 * 5 * Copyright (c) 2013 Imagination Technologies 6 * Author: Paul Burton <paul.burton@imgtec.com> 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <asm/io.h> 12 #include <mach/jz4780.h> 13 14 #define CPM_CPCCR 0x00 15 #define CPM_LCR 0x04 16 #define CPM_RSR 0x08 17 #define CPM_CPPCR 0x0c 18 #define CPM_CPAPCR 0x10 19 #define CPM_CPMPCR 0x14 20 #define CPM_CPEPCR 0x18 21 #define CPM_CPVPCR 0x1c 22 #define CPM_CLKGR0 0x20 23 #define CPM_OPCR 0x24 24 #define CPM_CLKGR1 0x28 25 #define CPM_DDCDR 0x2c 26 #define CPM_VPUCDR 0x30 27 #define CPM_CPSPR 0x34 28 #define CPM_CPSPPR 0x38 29 #define CPM_USBPCR 0x3c 30 #define CPM_USBRDT 0x40 31 #define CPM_USBVBFIL 0x44 32 #define CPM_USBPCR1 0x48 33 #define CPM_USBCDR 0x50 34 #define CPM_LPCDR 0x54 35 #define CPM_I2SCDR 0x60 36 #define CPM_LPCDR1 0x64 37 #define CPM_MSCCDR 0x68 38 #define CPM_UHCCDR 0x6c 39 #define CPM_SSICDR 0x74 40 #define CPM_CIMCDR 0x7c 41 #define CPM_PCMCDR 0x84 42 #define CPM_GPUCDR 0x88 43 #define CPM_HDMICDR 0x8c 44 #define CPM_I2S1CDR 0xa0 45 #define CPM_MSCCDR1 0xa4 46 #define CPM_MSCCDR2 0xa8 47 #define CPM_BCHCDR 0xac 48 #define CPM_SPCR0 0xb8 49 #define CPM_SPCR1 0xbc 50 #define CPM_CPCSR 0xd4 51 #define CPM_PSWCST(n) ((0x4 * (n)) + 0x90) 52 53 /* Clock control register */ 54 #define CPM_CPCCR_SEL_SRC_BIT 30 55 #define CPM_CPCCR_SEL_SRC_MASK (0x3 << CPM_CPCCR_SEL_SRC_BIT) 56 #define CPM_SRC_SEL_STOP 0 57 #define CPM_SRC_SEL_APLL 1 58 #define CPM_SRC_SEL_EXCLK 2 59 #define CPM_SRC_SEL_RTCLK 3 60 #define CPM_CPCCR_SEL_CPLL_BIT 28 61 #define CPM_CPCCR_SEL_CPLL_MASK (0x3 << CPM_CPCCR_SEL_CPLL_BIT) 62 #define CPM_CPCCR_SEL_H0PLL_BIT 26 63 #define CPM_CPCCR_SEL_H0PLL_MASK (0x3 << CPM_CPCCR_SEL_H0PLL_BIT) 64 #define CPM_CPCCR_SEL_H2PLL_BIT 24 65 #define CPM_CPCCR_SEL_H2PLL_MASK (0x3 << CPM_CPCCR_SEL_H2PLL_BIT) 66 #define CPM_PLL_SEL_STOP 0 67 #define CPM_PLL_SEL_SRC 1 68 #define CPM_PLL_SEL_MPLL 2 69 #define CPM_PLL_SEL_EPLL 3 70 #define CPM_CPCCR_CE_CPU (0x1 << 22) 71 #define CPM_CPCCR_CE_AHB0 (0x1 << 21) 72 #define CPM_CPCCR_CE_AHB2 (0x1 << 20) 73 #define CPM_CPCCR_PDIV_BIT 16 74 #define CPM_CPCCR_PDIV_MASK (0xf << CPM_CPCCR_PDIV_BIT) 75 #define CPM_CPCCR_H2DIV_BIT 12 76 #define CPM_CPCCR_H2DIV_MASK (0xf << CPM_CPCCR_H2DIV_BIT) 77 #define CPM_CPCCR_H0DIV_BIT 8 78 #define CPM_CPCCR_H0DIV_MASK (0x0f << CPM_CPCCR_H0DIV_BIT) 79 #define CPM_CPCCR_L2DIV_BIT 4 80 #define CPM_CPCCR_L2DIV_MASK (0x0f << CPM_CPCCR_L2DIV_BIT) 81 #define CPM_CPCCR_CDIV_BIT 0 82 #define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) 83 84 /* Clock Status register */ 85 #define CPM_CPCSR_H2DIV_BUSY BIT(2) 86 #define CPM_CPCSR_H0DIV_BUSY BIT(1) 87 #define CPM_CPCSR_CDIV_BUSY BIT(0) 88 89 /* PLL control register */ 90 #define CPM_CPPCR_PLLST_BIT 0 91 #define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) 92 93 /* XPLL control register */ 94 #define CPM_CPXPCR_XPLLM_BIT 19 95 #define CPM_CPXPCR_XPLLM_MASK (0x1fff << CPM_CPXPCR_XPLLM_BIT) 96 #define CPM_CPXPCR_XPLLN_BIT 13 97 #define CPM_CPXPCR_XPLLN_MASK (0x3f << CPM_CPXPCR_XPLLN_BIT) 98 #define CPM_CPXPCR_XPLLOD_BIT 9 99 #define CPM_CPXPCR_XPLLOD_MASK (0xf << CPM_CPXPCR_XPLLOD_BIT) 100 #define CPM_CPXPCR_XLOCK BIT(6) 101 #define CPM_CPXPCR_XPLL_ON BIT(4) 102 #define CPM_CPXPCR_XF_MODE BIT(3) 103 #define CPM_CPXPCR_XPLLBP BIT(1) 104 #define CPM_CPXPCR_XPLLEN BIT(0) 105 106 /* CPM scratch protected register */ 107 #define CPM_CPSPPR_BIT 0 108 #define CPM_CPSPPR_MASK (0xffff << CPM_CPSPPR_BIT) 109 110 /* USB parameter control register */ 111 #define CPM_USBPCR_USB_MODE BIT(31) /* 1: OTG, 0: UDC*/ 112 #define CPM_USBPCR_AVLD_REG BIT(30) 113 #define CPM_USBPCR_IDPULLUP_MASK_BIT 28 114 #define CPM_USBPCR_IDPULLUP_MASK_MASK (0x02 << IDPULLUP_MASK_BIT) 115 #define CPM_USBPCR_INCR_MASK BIT(27) 116 #define CPM_USBPCR_CLK12_EN BIT(26) 117 #define CPM_USBPCR_COMMONONN BIT(25) 118 #define CPM_USBPCR_VBUSVLDEXT BIT(24) 119 #define CPM_USBPCR_VBUSVLDEXTSEL BIT(23) 120 #define CPM_USBPCR_POR BIT(22) 121 #define CPM_USBPCR_SIDDQ BIT(21) 122 #define CPM_USBPCR_OTG_DISABLE BIT(20) 123 #define CPM_USBPCR_COMPDISTUNE_BIT 17 124 #define CPM_USBPCR_COMPDISTUNE_MASK (0x07 << COMPDISTUNE_BIT) 125 #define CPM_USBPCR_OTGTUNE_BIT 14 126 #define CPM_USBPCR_OTGTUNE_MASK (0x07 << OTGTUNE_BIT) 127 #define CPM_USBPCR_SQRXTUNE_BIT 11 128 #define CPM_USBPCR_SQRXTUNE_MASK (0x7x << SQRXTUNE_BIT) 129 #define CPM_USBPCR_TXFSLSTUNE_BIT 7 130 #define CPM_USBPCR_TXFSLSTUNE_MASK (0x0f << TXFSLSTUNE_BIT) 131 #define CPM_USBPCR_TXPREEMPHTUNE BIT(6) 132 #define CPM_USBPCR_TXRISETUNE_BIT 4 133 #define CPM_USBPCR_TXRISETUNE_MASK (0x03 << TXRISETUNE_BIT) 134 #define CPM_USBPCR_TXVREFTUNE_BIT 0 135 #define CPM_USBPCR_TXVREFTUNE_MASK (0x0f << TXVREFTUNE_BIT) 136 137 /* DDR memory clock divider register */ 138 #define CPM_DDRCDR_DCS_BIT 30 139 #define CPM_DDRCDR_DCS_MASK (0x3 << CPM_DDRCDR_DCS_BIT) 140 #define CPM_DDRCDR_DCS_STOP (0x0 << CPM_DDRCDR_DCS_BIT) 141 #define CPM_DDRCDR_DCS_SRC (0x1 << CPM_DDRCDR_DCS_BIT) 142 #define CPM_DDRCDR_DCS_MPLL (0x2 << CPM_DDRCDR_DCS_BIT) 143 #define CPM_DDRCDR_CE_DDR BIT(29) 144 #define CPM_DDRCDR_DDR_BUSY BIT(28) 145 #define CPM_DDRCDR_DDR_STOP BIT(27) 146 #define CPM_DDRCDR_DDRDIV_BIT 0 147 #define CPM_DDRCDR_DDRDIV_MASK (0xf << CPM_DDRCDR_DDRDIV_BIT) 148 149 /* USB reset detect timer register */ 150 #define CPM_USBRDT_VBFIL_LD_EN BIT(25) 151 #define CPM_USBRDT_IDDIG_EN BIT(24) 152 #define CPM_USBRDT_IDDIG_REG BIT(23) 153 #define CPM_USBRDT_USBRDT_BIT 0 154 #define CPM_USBRDT_USBRDT_MASK (0x7fffff << CPM_USBRDT_USBRDT_BIT) 155 156 /* USB OTG PHY clock divider register */ 157 #define CPM_USBCDR_UCS BIT(31) 158 #define CPM_USBCDR_UPCS BIT(30) 159 #define CPM_USBCDR_CEUSB BIT(29) 160 #define CPM_USBCDR_USB_BUSY BIT(28) 161 #define CPM_USBCDR_OTGDIV_BIT 0 162 #define CPM_USBCDR_OTGDIV_MASK (0xff << CPM_USBCDR_OTGDIV_BIT) 163 164 /* I2S device clock divider register */ 165 #define CPM_I2SCDR_I2CS BIT(31) 166 #define CPM_I2SCDR_I2PCS BIT(30) 167 #define CPM_I2SCDR_I2SDIV_BIT 0 168 #define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) 169 170 /* LCD0 pix clock divider register */ 171 #define CPM_LPCDR_LPCS_BIT 30 172 #define CPM_LPCDR_LPCS_MASK (0x3 << CPM_LPCDR_LPCS_BIT) 173 #define CPM_LPCDR_CELCD BIT(28) 174 #define CPM_LPCDR_LCD_BUSY BIT(27) 175 #define CPM_LPCDR_LCD_STOP BIT(26) 176 #define CPM_LPCDR_PIXDIV_BIT 0 177 #define CPM_LPCDR_PIXDIV_MASK (0xff << CPM_LPCDR_PIXDIV_BIT) 178 179 /* MSC clock divider register */ 180 #define CPM_MSCCDR_MPCS_BIT 30 181 #define CPM_MSCCDR_MPCS_MASK (3 << CPM_MSCCDR_MPCS_BIT) 182 #define CPM_MSCCDR_MPCS_STOP (0x0 << CPM_MSCCDR_MPCS_BIT) 183 #define CPM_MSCCDR_MPCS_SRC (0x1 << CPM_MSCCDR_MPCS_BIT) 184 #define CPM_MSCCDR_MPCS_MPLL (0x2 << CPM_MSCCDR_MPCS_BIT) 185 #define CPM_MSCCDR_CE BIT(29) 186 #define CPM_MSCCDR_MSC_BUSY BIT(28) 187 #define CPM_MSCCDR_MSC_STOP BIT(27) 188 #define CPM_MSCCDR_MSC_CLK0_SEL BIT(15) 189 #define CPM_MSCCDR_MSCDIV_BIT 0 190 #define CPM_MSCCDR_MSCDIV_MASK (0xff << CPM_MSCCDR_MSCDIV_BIT) 191 192 /* UHC 48M clock divider register */ 193 #define CPM_UHCCDR_UHCS_BIT 30 194 #define CPM_UHCCDR_UHCS_MASK (0x3 << CPM_UHCCDR_UHCS_BIT) 195 #define CPM_UHCCDR_UHCS_SRC (0x0 << CPM_UHCCDR_UHCS_BIT) 196 #define CPM_UHCCDR_UHCS_MPLL (0x1 << CPM_UHCCDR_UHCS_BIT) 197 #define CPM_UHCCDR_UHCS_EPLL (0x2 << CPM_UHCCDR_UHCS_BIT) 198 #define CPM_UHCCDR_UHCS_OTG (0x3 << CPM_UHCCDR_UHCS_BIT) 199 #define CPM_UHCCDR_CE_UHC BIT(29) 200 #define CPM_UHCCDR_UHC_BUSY BIT(28) 201 #define CPM_UHCCDR_UHC_STOP BIT(27) 202 #define CPM_UHCCDR_UHCDIV_BIT 0 203 #define CPM_UHCCDR_UHCDIV_MASK (0xff << CPM_UHCCDR_UHCDIV_BIT) 204 205 /* SSI clock divider register */ 206 #define CPM_SSICDR_SCS BIT(31) 207 #define CPM_SSICDR_SSIDIV_BIT 0 208 #define CPM_SSICDR_SSIDIV_MASK (0x3f << CPM_SSICDR_SSIDIV_BIT) 209 210 /* CIM MCLK clock divider register */ 211 #define CPM_CIMCDR_CIMDIV_BIT 0 212 #define CPM_CIMCDR_CIMDIV_MASK (0xff << CPM_CIMCDR_CIMDIV_BIT) 213 214 /* GPS clock divider register */ 215 #define CPM_GPSCDR_GPCS BIT(31) 216 #define CPM_GPSCDR_GPSDIV_BIT 0 217 #define CPM_GSPCDR_GPSDIV_MASK (0xf << CPM_GPSCDR_GPSDIV_BIT) 218 219 /* PCM device clock divider register */ 220 #define CPM_PCMCDR_PCMS BIT(31) 221 #define CPM_PCMCDR_PCMPCS BIT(30) 222 #define CPM_PCMCDR_PCMDIV_BIT 0 223 #define CPM_PCMCDR_PCMDIV_MASK (0x1ff << CPM_PCMCDR_PCMDIV_BIT) 224 225 /* GPU clock divider register */ 226 #define CPM_GPUCDR_GPCS BIT(31) 227 #define CPM_GPUCDR_GPUDIV_BIT 0 228 #define CPM_GPUCDR_GPUDIV_MASK (0x7 << CPM_GPUCDR_GPUDIV_BIT) 229 230 /* HDMI clock divider register */ 231 #define CPM_HDMICDR_HPCS_BIT 30 232 #define CPM_HDMICDR_HPCS_MASK (0x3 << CPM_HDMICDR_HPCS_BIT) 233 #define CPM_HDMICDR_CEHDMI BIT(29) 234 #define CPM_HDMICDR_HDMI_BUSY BIT(28) 235 #define CPM_HDMICDR_HDMI_STOP BIT(26) 236 #define CPM_HDMICDR_HDMIDIV_BIT 0 237 #define CPM_HDMICDR_HDMIDIV_MASK (0xff << CPM_HDMICDR_HDMIDIV_BIT) 238 239 /* Low Power Control Register */ 240 #define CPM_LCR_PD_SCPU BIT(31) 241 #define CPM_LCR_PD_VPU BIT(30) 242 #define CPM_LCR_PD_GPU BIT(29) 243 #define CPM_LCR_PD_GPS BIT(28) 244 #define CPM_LCR_SCPUS BIT(27) 245 #define CPM_LCR_VPUS BIT(26) 246 #define CPM_LCR_GPUS BIT(25) 247 #define CPM_LCR_GPSS BIT(24) 248 #define CPM_LCR_GPU_IDLE BIT(20) 249 #define CPM_LCR_PST_BIT 8 250 #define CPM_LCR_PST_MASK (0xfff << CPM_LCR_PST_BIT) 251 #define CPM_LCR_DOZE_DUTY_BIT 3 252 #define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) 253 #define CPM_LCR_DOZE_ON BIT(2) 254 #define CPM_LCR_LPM_BIT 0 255 #define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) 256 #define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) 257 #define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) 258 259 /* Clock Gate Register0 */ 260 #define CPM_CLKGR0_DDR1 BIT(31) 261 #define CPM_CLKGR0_DDR0 BIT(30) 262 #define CPM_CLKGR0_IPU BIT(29) 263 #define CPM_CLKGR0_LCD1 BIT(28) 264 #define CPM_CLKGR0_LCD BIT(27) 265 #define CPM_CLKGR0_CIM BIT(26) 266 #define CPM_CLKGR0_I2C2 BIT(25) 267 #define CPM_CLKGR0_UHC BIT(24) 268 #define CPM_CLKGR0_MAC BIT(23) 269 #define CPM_CLKGR0_GPS BIT(22) 270 #define CPM_CLKGR0_PDMAC BIT(21) 271 #define CPM_CLKGR0_SSI2 BIT(20) 272 #define CPM_CLKGR0_SSI1 BIT(19) 273 #define CPM_CLKGR0_UART3 BIT(18) 274 #define CPM_CLKGR0_UART2 BIT(17) 275 #define CPM_CLKGR0_UART1 BIT(16) 276 #define CPM_CLKGR0_UART0 BIT(15) 277 #define CPM_CLKGR0_SADC BIT(14) 278 #define CPM_CLKGR0_KBC BIT(13) 279 #define CPM_CLKGR0_MSC2 BIT(12) 280 #define CPM_CLKGR0_MSC1 BIT(11) 281 #define CPM_CLKGR0_OWI BIT(10) 282 #define CPM_CLKGR0_TSSI BIT(9) 283 #define CPM_CLKGR0_AIC BIT(8) 284 #define CPM_CLKGR0_SCC BIT(7) 285 #define CPM_CLKGR0_I2C1 BIT(6) 286 #define CPM_CLKGR0_I2C0 BIT(5) 287 #define CPM_CLKGR0_SSI0 BIT(4) 288 #define CPM_CLKGR0_MSC0 BIT(3) 289 #define CPM_CLKGR0_OTG BIT(2) 290 #define CPM_CLKGR0_BCH BIT(1) 291 #define CPM_CLKGR0_NEMC BIT(0) 292 293 /* Clock Gate Register1 */ 294 #define CPM_CLKGR1_P1 BIT(15) 295 #define CPM_CLKGR1_X2D BIT(14) 296 #define CPM_CLKGR1_DES BIT(13) 297 #define CPM_CLKGR1_I2C4 BIT(12) 298 #define CPM_CLKGR1_AHB BIT(11) 299 #define CPM_CLKGR1_UART4 BIT(10) 300 #define CPM_CLKGR1_HDMI BIT(9) 301 #define CPM_CLKGR1_OTG1 BIT(8) 302 #define CPM_CLKGR1_GPVLC BIT(7) 303 #define CPM_CLKGR1_AIC1 BIT(6) 304 #define CPM_CLKGR1_COMPRES BIT(5) 305 #define CPM_CLKGR1_GPU BIT(4) 306 #define CPM_CLKGR1_PCM BIT(3) 307 #define CPM_CLKGR1_VPU BIT(2) 308 #define CPM_CLKGR1_TSSI1 BIT(1) 309 #define CPM_CLKGR1_I2C3 BIT(0) 310 311 /* Oscillator and Power Control Register */ 312 #define CPM_OPCR_O1ST_BIT 8 313 #define CPM_OPCR_O1ST_MASK (0xff << CPM_OPCR_O1ST_BIT) 314 #define CPM_OPCR_SPENDN BIT(7) 315 #define CPM_OPCR_GPSEN BIT(6) 316 #define CPM_OPCR_SPENDH BIT(5) 317 #define CPM_OPCR_O1SE BIT(4) 318 #define CPM_OPCR_ERCS BIT(2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */ 319 #define CPM_OPCR_USBM BIT(0) /* 0: select EXCLK/512 clock, 1: RTCLK clock */ 320 321 /* Reset Status Register */ 322 #define CPM_RSR_P0R BIT(2) 323 #define CPM_RSR_WR BIT(1) 324 #define CPM_RSR_PR BIT(0) 325 326 /* BCH clock divider register */ 327 #define CPM_BCHCDR_BPCS_BIT 30 328 #define CPM_BCHCDR_BPCS_MASK (0x3 << CPM_BCHCDR_BPCS_BIT) 329 #define CPM_BCHCDR_BPCS_STOP (0X0 << CPM_BCHCDR_BPCS_BIT) 330 #define CPM_BCHCDR_BPCS_SRC_CLK (0x1 << CPM_BCHCDR_BPCS_BIT) 331 #define CPM_BCHCDR_BPCS_MPLL (0x2 << CPM_BCHCDR_BPCS_BIT) 332 #define CPM_BCHCDR_BPCS_EPLL (0x3 << CPM_BCHCDR_BPCS_BIT) 333 #define CPM_BCHCDR_CE_BCH BIT(29) 334 #define CPM_BCHCDR_BCH_BUSY BIT(28) 335 #define CPM_BCHCDR_BCH_STOP BIT(27) 336 #define CPM_BCHCDR_BCHCDR_BIT 0 337 #define CPM_BCHCDR_BCHCDR_MASK (0x7 << CPM_BCHCDR_BCHCDR_BIT) 338 339 /* CPM scratch pad protected register(CPSPPR) */ 340 #define CPSPPR_CPSPR_WRITABLE 0x00005a5a 341 #define RECOVERY_SIGNATURE 0x1a1a /* means "RECY" */ 342 #define RECOVERY_SIGNATURE_SEC 0x800 /* means "RECY" */ 343 344 #define REBOOT_SIGNATURE 0x3535 /* means reboot */ 345 346 /* XPLL control register */ 347 #define XLOCK (1 << 6) 348 #define XPLL_ON (1 << 4) 349 #define XF_MODE (1 << 3) 350 #define XPLLBP (1 << 1) 351 #define XPLLEN (1 << 0) 352 353 enum PLLS { 354 EXTCLK = 0, 355 APLL, 356 MPLL, 357 EPLL, 358 VPLL, 359 }; 360 361 #define M_N_OD(m, n, od) \ 362 ((((m) - 1) << 19) | (((n) - 1) << 13) | (((od) - 1) << 9)) 363 364 struct cgu_pll_select { 365 u8 reg; 366 u8 pll; 367 u8 pll_shift; 368 }; 369 pll_init_one(int pll,int m,int n,int od)370 static void pll_init_one(int pll, int m, int n, int od) 371 { 372 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 373 void __iomem *pll_reg = cpm_regs + CPM_CPAPCR + ((pll - 1) * 4); 374 375 setbits_le32(pll_reg, M_N_OD(m, n, od) | XPLLEN); 376 377 /* FIXME */ 378 while (!(readl(pll_reg) & XPLL_ON)) 379 ; 380 } 381 cpu_mux_select(int pll)382 static void cpu_mux_select(int pll) 383 { 384 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 385 u32 clk_ctrl; 386 unsigned int selectplls[] = { 387 CPM_PLL_SEL_STOP, 388 CPM_PLL_SEL_SRC, 389 CPM_PLL_SEL_MPLL, 390 CPM_PLL_SEL_EPLL 391 }; 392 393 /* Init CPU, L2CACHE, AHB0, AHB2, APB clock */ 394 clk_ctrl = CPM_CPCCR_CE_CPU | CPM_CPCCR_CE_AHB0 | CPM_CPCCR_CE_AHB2 | 395 ((6 - 1) << CPM_CPCCR_H2DIV_BIT) | 396 ((3 - 1) << CPM_CPCCR_H0DIV_BIT) | 397 ((2 - 1) << CPM_CPCCR_L2DIV_BIT) | 398 ((1 - 1) << CPM_CPCCR_CDIV_BIT); 399 400 if (CONFIG_SYS_MHZ >= 1000) 401 clk_ctrl |= (12 - 1) << CPM_CPCCR_PDIV_BIT; 402 else 403 clk_ctrl |= (6 - 1) << CPM_CPCCR_PDIV_BIT; 404 405 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0x00ffffff, clk_ctrl); 406 407 while (readl(cpm_regs + CPM_CPCSR) & (CPM_CPCSR_CDIV_BUSY | 408 CPM_CPCSR_H0DIV_BUSY | CPM_CPCSR_H2DIV_BUSY)) 409 ; 410 411 clk_ctrl = (selectplls[pll] << CPM_CPCCR_SEL_CPLL_BIT) | 412 (selectplls[MPLL] << CPM_CPCCR_SEL_H0PLL_BIT) | 413 (selectplls[MPLL] << CPM_CPCCR_SEL_H2PLL_BIT); 414 if (pll == APLL) 415 clk_ctrl |= CPM_PLL_SEL_SRC << CPM_CPCCR_SEL_SRC_BIT; 416 else 417 clk_ctrl |= CPM_SRC_SEL_EXCLK << CPM_CPCCR_SEL_SRC_BIT; 418 419 clrsetbits_le32(cpm_regs + CPM_CPCCR, 0xff << 24, clk_ctrl); 420 } 421 ddr_mux_select(int pll)422 static void ddr_mux_select(int pll) 423 { 424 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 425 int selectplls[] = { CPM_DDRCDR_DCS_STOP, 426 CPM_DDRCDR_DCS_SRC, 427 CPM_DDRCDR_DCS_MPLL}; 428 429 writel(selectplls[pll] | CPM_DDRCDR_CE_DDR | (JZ4780_SYS_MEM_DIV - 1), 430 cpm_regs + CPM_DDCDR); 431 432 while (readl(cpm_regs + CPM_DDCDR) & CPM_DDRCDR_DDR_BUSY) 433 ; 434 435 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_DDR0); 436 437 mdelay(200); 438 } 439 cgu_mux_init(struct cgu_pll_select * cgu,unsigned int num)440 static void cgu_mux_init(struct cgu_pll_select *cgu, unsigned int num) 441 { 442 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 443 unsigned int selectplls[] = {0, 1, 2, 3, 2, 6}; 444 int i; 445 446 for (i = 0; i < num; i++) 447 writel(selectplls[cgu[i].pll] << cgu[i].pll_shift, 448 cpm_regs + cgu[i].reg); 449 } 450 pll_init(void)451 void pll_init(void) 452 { 453 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 454 struct cgu_pll_select cgu_mux[] = { 455 { CPM_MSCCDR, MPLL, 30 }, 456 { CPM_LPCDR, VPLL, 30 }, 457 { CPM_LPCDR1, VPLL, 30 }, 458 { CPM_GPUCDR, MPLL, 30 }, 459 { CPM_HDMICDR, VPLL, 30 }, 460 { CPM_I2SCDR, EPLL, 30 }, 461 { CPM_BCHCDR, MPLL, 30 }, 462 { CPM_VPUCDR, 0x1, 30 }, 463 { CPM_UHCCDR, 0x3, 30 }, 464 { CPM_CIMCDR, 0x1, 31 }, 465 { CPM_PCMCDR, 0x5, 29 }, 466 { CPM_SSICDR, 0x3, 30 }, 467 }; 468 469 /* PLL stable time set to default -- 1ms */ 470 clrsetbits_le32(cpm_regs + CPM_CPPCR, 0xfffff, (16 << 8) | 0x20); 471 472 pll_init_one(APLL, JZ4780_APLL_M, JZ4780_APLL_N, JZ4780_APLL_OD); 473 pll_init_one(MPLL, JZ4780_MPLL_M, JZ4780_MPLL_N, JZ4780_MPLL_OD); 474 pll_init_one(VPLL, JZ4780_VPLL_M, JZ4780_VPLL_N, JZ4780_VPLL_OD); 475 pll_init_one(EPLL, JZ4780_EPLL_M, JZ4780_EPLL_N, JZ4780_EPLL_OD); 476 477 cpu_mux_select(MPLL); 478 ddr_mux_select(MPLL); 479 cgu_mux_init(cgu_mux, ARRAY_SIZE(cgu_mux)); 480 } 481 jz4780_clk_get_efuse_clk(void)482 const u32 jz4780_clk_get_efuse_clk(void) 483 { 484 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 485 u32 cpccr = readl(cpm_regs + CPM_CPCCR); 486 u32 ahb2_div = ((cpccr & CPM_CPCCR_H2DIV_MASK) >> 487 CPM_CPCCR_H2DIV_BIT) + 1; 488 return JZ4780_SYS_MEM_SPEED / ahb2_div; 489 } 490 jz4780_clk_ungate_ethernet(void)491 void jz4780_clk_ungate_ethernet(void) 492 { 493 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 494 495 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_MAC); 496 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_NEMC); 497 } 498 jz4780_clk_ungate_mmc(void)499 void jz4780_clk_ungate_mmc(void) 500 { 501 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 502 u32 msc_cdr = JZ4780_SYS_MEM_SPEED / 24000000 / 2 - 1; 503 504 msc_cdr |= CPM_MSCCDR_MPCS_MPLL | CPM_MSCCDR_CE; 505 writel(msc_cdr, cpm_regs + CPM_MSCCDR); 506 writel(msc_cdr, cpm_regs + CPM_MSCCDR1); 507 writel(msc_cdr, cpm_regs + CPM_MSCCDR2); 508 509 /* The wait_for_bit() won't fit, thus unbounded loop here. */ 510 while (readl(cpm_regs + CPM_MSCCDR1) & CPM_MSCCDR_MSC_BUSY) 511 ; 512 } 513 jz4780_clk_ungate_uart(const unsigned int uart)514 void jz4780_clk_ungate_uart(const unsigned int uart) 515 { 516 void __iomem *cpm_regs = (void __iomem *)CPM_BASE; 517 518 if (uart == 0) 519 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART0); 520 else if (uart == 1) 521 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART1); 522 else if (uart == 2) 523 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART2); 524 else if (uart == 3) 525 clrbits_le32(cpm_regs + CPM_CLKGR0, CPM_CLKGR0_UART3); 526 else if (uart == 4) 527 clrbits_le32(cpm_regs + CPM_CLKGR1, CPM_CLKGR1_UART4); 528 else 529 printf("%s[%i]: Invalid UART %d\n", __func__, __LINE__, uart); 530 } 531