1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc.
5 */
6
7 #include <common.h>
8 #include <usb.h>
9 #include <errno.h>
10 #include <linux/compiler.h>
11 #include <usb/ehci-ci.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15
16 #include "ehci.h"
17
18 #define MX5_USBOTHER_REGS_OFFSET 0x800
19
20
21 #define MXC_OTG_OFFSET 0
22 #define MXC_H1_OFFSET 0x200
23 #define MXC_H2_OFFSET 0x400
24 #define MXC_H3_OFFSET 0x600
25
26 #define MXC_USBCTRL_OFFSET 0
27 #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
28 #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
29 #define MXC_USB_CTRL_1_OFFSET 0x10
30 #define MXC_USBH2CTRL_OFFSET 0x14
31 #define MXC_USBH3CTRL_OFFSET 0x18
32
33 /* USB_CTRL */
34 /* OTG wakeup intr enable */
35 #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
36 /* OTG power mask */
37 #define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
38 /* OTG power pin polarity */
39 #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
40 /* Host1 ULPI interrupt enable */
41 #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
42 /* HOST1 wakeup intr enable */
43 #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
44 /* HOST1 power mask */
45 #define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
46 /* HOST1 power pin polarity */
47 #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
48
49 /* USB_PHY_CTRL_FUNC */
50 /* OTG Polarity of Overcurrent */
51 #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
52 /* OTG Disable Overcurrent Event */
53 #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
54 /* UH1 Polarity of Overcurrent */
55 #define MXC_H1_OC_POL_BIT (1 << 6)
56 /* UH1 Disable Overcurrent Event */
57 #define MXC_H1_OC_DIS_BIT (1 << 5)
58 /* OTG Power Pin Polarity */
59 #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
60
61 /* USBH2CTRL */
62 #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
63 #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
64 #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
65 #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
66 #define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
67 #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
68
69 /* USBH3CTRL */
70 #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
71 #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
72 #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
73 #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
74 #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
75
76 /* USB_CTRL_1 */
77 #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
78
mxc_set_usbcontrol(int port,unsigned int flags)79 int mxc_set_usbcontrol(int port, unsigned int flags)
80 {
81 unsigned int v;
82 void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
83 void __iomem *usbother_base;
84 int ret = 0;
85
86 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
87
88 switch (port) {
89 case 0: /* OTG port */
90 if (flags & MXC_EHCI_INTERNAL_PHY) {
91 v = __raw_readl(usbother_base +
92 MXC_USB_PHY_CTR_FUNC_OFFSET);
93 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
94 v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
95 else
96 v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
97 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
98 /* OC/USBPWR is used */
99 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
100 else
101 /* OC/USBPWR is not used */
102 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
103 #ifdef CONFIG_MX51
104 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
105 v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
106 else
107 v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
108 #endif
109 __raw_writel(v, usbother_base +
110 MXC_USB_PHY_CTR_FUNC_OFFSET);
111
112 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
113 #ifdef CONFIG_MX51
114 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
115 v &= ~MXC_OTG_UCTRL_OPM_BIT;
116 else
117 v |= MXC_OTG_UCTRL_OPM_BIT;
118 #endif
119 #ifdef CONFIG_MX53
120 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
121 v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
122 else
123 v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
124 #endif
125 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
126 }
127 break;
128 case 1: /* Host 1 ULPI */
129 #ifdef CONFIG_MX51
130 /* The clock for the USBH1 ULPI port will come externally
131 from the PHY. */
132 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
133 __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
134 MXC_USB_CTRL_1_OFFSET);
135 #endif
136
137 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
138 #ifdef CONFIG_MX51
139 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
140 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
141 else
142 v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
143 #endif
144 #ifdef CONFIG_MX53
145 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
146 v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
147 else
148 v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
149 #endif
150 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
151
152 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
153 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
154 v |= MXC_H1_OC_POL_BIT;
155 else
156 v &= ~MXC_H1_OC_POL_BIT;
157 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
158 v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
159 else
160 v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
161 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
162
163 break;
164 case 2: /* Host 2 ULPI */
165 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
166 #ifdef CONFIG_MX51
167 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
168 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
169 else
170 v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
171 #endif
172 #ifdef CONFIG_MX53
173 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
174 v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
175 else
176 v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
177 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
178 v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
179 else
180 v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
181 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
182 v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
183 else
184 v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
185 #endif
186 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
187 break;
188 #ifdef CONFIG_MX53
189 case 3: /* Host 3 ULPI */
190 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
191 if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
192 v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
193 else
194 v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
195 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
196 v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
197 else
198 v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
199 if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
200 v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
201 else
202 v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
203 __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
204 break;
205 #endif
206 }
207
208 return ret;
209 }
210
board_ehci_hcd_init(int port)211 int __weak board_ehci_hcd_init(int port)
212 {
213 return 0;
214 }
215
board_ehci_hcd_postinit(struct usb_ehci * ehci,int port)216 void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
217 {
218 }
219
mx5_ehci_powerup_fixup(struct ehci_ctrl * ctrl,uint32_t * status_reg,uint32_t * reg)220 __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
221 uint32_t *reg)
222 {
223 mdelay(50);
224 }
225
226 static const struct ehci_ops mx5_ehci_ops = {
227 .powerup_fixup = mx5_ehci_powerup_fixup,
228 };
229
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)230 int ehci_hcd_init(int index, enum usb_init_type init,
231 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
232 {
233 struct usb_ehci *ehci;
234
235 /* The only user for this is efikamx-usb */
236 ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
237 set_usboh3_clk();
238 enable_usboh3_clk(true);
239 set_usb_phy_clk();
240 enable_usb_phy1_clk(true);
241 enable_usb_phy2_clk(true);
242 mdelay(1);
243
244 /* Do board specific initialization */
245 board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
246
247 ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
248 (0x200 * CONFIG_MXC_USB_PORT));
249 *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
250 *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
251 HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
252 setbits_le32(&ehci->usbmode, CM_HOST);
253
254 __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
255 setbits_le32(&ehci->portsc, USB_EN);
256
257 mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
258 mdelay(10);
259
260 /* Do board specific post-initialization */
261 board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
262
263 return 0;
264 }
265
ehci_hcd_stop(int index)266 int ehci_hcd_stop(int index)
267 {
268 return 0;
269 }
270