xref: /openbmc/linux/arch/sparc/include/asm/mxcc.h (revision b2441318)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * mxcc.h:  Definitions of the Viking MXCC registers
4  *
5  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6  */
7 
8 #ifndef _SPARC_MXCC_H
9 #define _SPARC_MXCC_H
10 
11 /* These registers are accessed through ASI 0x2. */
12 #define MXCC_DATSTREAM       0x1C00000  /* Data stream register */
13 #define MXCC_SRCSTREAM       0x1C00100  /* Source stream register */
14 #define MXCC_DESSTREAM       0x1C00200  /* Destination stream register */
15 #define MXCC_RMCOUNT         0x1C00300  /* Count of references and misses */
16 #define MXCC_STEST           0x1C00804  /* Internal self-test */
17 #define MXCC_CREG            0x1C00A04  /* Control register */
18 #define MXCC_SREG            0x1C00B00  /* Status register */
19 #define MXCC_RREG            0x1C00C04  /* Reset register */
20 #define MXCC_EREG            0x1C00E00  /* Error code register */
21 #define MXCC_PREG            0x1C00F04  /* Address port register */
22 
23 /* Some MXCC constants. */
24 #define MXCC_STREAM_SIZE     0x20       /* Size in bytes of one stream r/w */
25 
26 /* The MXCC Control Register:
27  *
28  * ----------------------------------------------------------------------
29  * |                                   | RRC | RSV |PRE|MCE|PARE|ECE|RSV|
30  * ----------------------------------------------------------------------
31  *  31                              10    9    8-6   5   4    3   2  1-0
32  *
33  * RRC: Controls what you read from MXCC_RMCOUNT reg.
34  *      0=Misses 1=References
35  * PRE: Prefetch enable
36  * MCE: Multiple Command Enable
37  * PARE: Parity enable
38  * ECE: External cache enable
39  */
40 
41 #define MXCC_CTL_RRC   0x00000200
42 #define MXCC_CTL_PRE   0x00000020
43 #define MXCC_CTL_MCE   0x00000010
44 #define MXCC_CTL_PARE  0x00000008
45 #define MXCC_CTL_ECE   0x00000004
46 
47 /* The MXCC Error Register:
48  *
49  * --------------------------------------------------------
50  * |ME| RSV|CE|PEW|PEE|ASE|EIV| MOPC|ECODE|PRIV|RSV|HPADDR|
51  * --------------------------------------------------------
52  *  31   30 29  28  27  26  25 24-15  14-7   6  5-3   2-0
53  *
54  * ME: Multiple Errors have occurred
55  * CE: Cache consistency Error
56  * PEW: Parity Error during a Write operation
57  * PEE: Parity Error involving the External cache
58  * ASE: ASynchronous Error
59  * EIV: This register is toast
60  * MOPC: MXCC Operation Code for instance causing error
61  * ECODE: The Error CODE
62  * PRIV: A privileged mode error? 0=no 1=yes
63  * HPADDR: High PhysicalADDRess bits (35-32)
64  */
65 
66 #define MXCC_ERR_ME     0x80000000
67 #define MXCC_ERR_CE     0x20000000
68 #define MXCC_ERR_PEW    0x10000000
69 #define MXCC_ERR_PEE    0x08000000
70 #define MXCC_ERR_ASE    0x04000000
71 #define MXCC_ERR_EIV    0x02000000
72 #define MXCC_ERR_MOPC   0x01FF8000
73 #define MXCC_ERR_ECODE  0x00007F80
74 #define MXCC_ERR_PRIV   0x00000040
75 #define MXCC_ERR_HPADDR 0x0000000f
76 
77 /* The MXCC Port register:
78  *
79  * -----------------------------------------------------
80  * |                | MID |                            |
81  * -----------------------------------------------------
82  *  31            21 20-18 17                         0
83  *
84  * MID: The moduleID of the cpu your read this from.
85  */
86 
87 #ifndef __ASSEMBLY__
88 
mxcc_set_stream_src(unsigned long * paddr)89 static inline void mxcc_set_stream_src(unsigned long *paddr)
90 {
91 	unsigned long data0 = paddr[0];
92 	unsigned long data1 = paddr[1];
93 
94 	__asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
95 			      "or %%g0, %1, %%g3\n\t"
96 			      "stda %%g2, [%2] %3\n\t" : :
97 			      "r" (data0), "r" (data1),
98 			      "r" (MXCC_SRCSTREAM),
99 			      "i" (ASI_M_MXCC) : "g2", "g3");
100 }
101 
mxcc_set_stream_dst(unsigned long * paddr)102 static inline void mxcc_set_stream_dst(unsigned long *paddr)
103 {
104 	unsigned long data0 = paddr[0];
105 	unsigned long data1 = paddr[1];
106 
107 	__asm__ __volatile__ ("or %%g0, %0, %%g2\n\t"
108 			      "or %%g0, %1, %%g3\n\t"
109 			      "stda %%g2, [%2] %3\n\t" : :
110 			      "r" (data0), "r" (data1),
111 			      "r" (MXCC_DESSTREAM),
112 			      "i" (ASI_M_MXCC) : "g2", "g3");
113 }
114 
mxcc_get_creg(void)115 static inline unsigned long mxcc_get_creg(void)
116 {
117 	unsigned long mxcc_control;
118 
119 	__asm__ __volatile__("set 0xffffffff, %%g2\n\t"
120 			     "set 0xffffffff, %%g3\n\t"
121 			     "stda %%g2, [%1] %2\n\t"
122 			     "lda [%3] %2, %0\n\t" :
123 			     "=r" (mxcc_control) :
124 			     "r" (MXCC_EREG), "i" (ASI_M_MXCC),
125 			     "r" (MXCC_CREG) : "g2", "g3");
126 	return mxcc_control;
127 }
128 
mxcc_set_creg(unsigned long mxcc_control)129 static inline void mxcc_set_creg(unsigned long mxcc_control)
130 {
131 	__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
132 			     "r" (mxcc_control), "r" (MXCC_CREG),
133 			     "i" (ASI_M_MXCC));
134 }
135 
136 #endif /* !__ASSEMBLY__ */
137 
138 #endif /* !(_SPARC_MXCC_H) */
139