1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* @file mwifiex_pcie.h
3  *
4  * @brief This file contains definitions for PCI-E interface.
5  * driver.
6  *
7  * Copyright 2011-2020 NXP
8  */
9 
10 #ifndef	_MWIFIEX_PCIE_H
11 #define	_MWIFIEX_PCIE_H
12 
13 #include    <linux/completion.h>
14 #include    <linux/pci.h>
15 #include    <linux/interrupt.h>
16 
17 #include    "decl.h"
18 #include    "main.h"
19 
20 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
21 #define PCIE8897_DEFAULT_FW_NAME "mrvl/pcie8897_uapsta.bin"
22 #define PCIE8897_A0_FW_NAME "mrvl/pcie8897_uapsta_a0.bin"
23 #define PCIE8897_B0_FW_NAME "mrvl/pcie8897_uapsta.bin"
24 #define PCIEUART8997_FW_NAME_V4 "mrvl/pcieuart8997_combo_v4.bin"
25 #define PCIEUSB8997_FW_NAME_V4 "mrvl/pcieusb8997_combo_v4.bin"
26 
27 #define PCIE_VENDOR_ID_MARVELL              (0x11ab)
28 #define PCIE_VENDOR_ID_V2_MARVELL           (0x1b4b)
29 #define PCIE_DEVICE_ID_MARVELL_88W8766P		(0x2b30)
30 #define PCIE_DEVICE_ID_MARVELL_88W8897		(0x2b38)
31 #define PCIE_DEVICE_ID_MARVELL_88W8997		(0x2b42)
32 
33 #define PCIE8897_A0	0x1100
34 #define PCIE8897_B0	0x1200
35 #define PCIE8997_A0	0x10
36 #define PCIE8997_A1	0x11
37 #define CHIP_VER_PCIEUART	0x3
38 #define CHIP_MAGIC_VALUE	0x24
39 
40 /* Constants for Buffer Descriptor (BD) rings */
41 #define MWIFIEX_MAX_TXRX_BD			0x20
42 #define MWIFIEX_TXBD_MASK			0x3F
43 #define MWIFIEX_RXBD_MASK			0x3F
44 
45 #define MWIFIEX_MAX_EVT_BD			0x08
46 #define MWIFIEX_EVTBD_MASK			0x0f
47 
48 /* PCIE INTERNAL REGISTERS */
49 #define PCIE_SCRATCH_0_REG				0xC10
50 #define PCIE_SCRATCH_1_REG				0xC14
51 #define PCIE_CPU_INT_EVENT				0xC18
52 #define PCIE_CPU_INT_STATUS				0xC1C
53 #define PCIE_HOST_INT_STATUS				0xC30
54 #define PCIE_HOST_INT_MASK				0xC34
55 #define PCIE_HOST_INT_STATUS_MASK			0xC3C
56 #define PCIE_SCRATCH_2_REG				0xC40
57 #define PCIE_SCRATCH_3_REG				0xC44
58 #define PCIE_SCRATCH_4_REG				0xCD0
59 #define PCIE_SCRATCH_5_REG				0xCD4
60 #define PCIE_SCRATCH_6_REG				0xCD8
61 #define PCIE_SCRATCH_7_REG				0xCDC
62 #define PCIE_SCRATCH_8_REG				0xCE0
63 #define PCIE_SCRATCH_9_REG				0xCE4
64 #define PCIE_SCRATCH_10_REG				0xCE8
65 #define PCIE_SCRATCH_11_REG				0xCEC
66 #define PCIE_SCRATCH_12_REG				0xCF0
67 #define PCIE_SCRATCH_13_REG				0xCF4
68 #define PCIE_SCRATCH_14_REG				0xCF8
69 #define PCIE_SCRATCH_15_REG				0xCFC
70 #define PCIE_RD_DATA_PTR_Q0_Q1                          0xC08C
71 #define PCIE_WR_DATA_PTR_Q0_Q1                          0xC05C
72 
73 #define CPU_INTR_DNLD_RDY				BIT(0)
74 #define CPU_INTR_DOOR_BELL				BIT(1)
75 #define CPU_INTR_SLEEP_CFM_DONE			BIT(2)
76 #define CPU_INTR_RESET					BIT(3)
77 #define CPU_INTR_EVENT_DONE				BIT(5)
78 
79 #define HOST_INTR_DNLD_DONE				BIT(0)
80 #define HOST_INTR_UPLD_RDY				BIT(1)
81 #define HOST_INTR_CMD_DONE				BIT(2)
82 #define HOST_INTR_EVENT_RDY				BIT(3)
83 #define HOST_INTR_MASK					(HOST_INTR_DNLD_DONE | \
84 							 HOST_INTR_UPLD_RDY  | \
85 							 HOST_INTR_CMD_DONE  | \
86 							 HOST_INTR_EVENT_RDY)
87 
88 #define MWIFIEX_BD_FLAG_ROLLOVER_IND			BIT(7)
89 #define MWIFIEX_BD_FLAG_FIRST_DESC			BIT(0)
90 #define MWIFIEX_BD_FLAG_LAST_DESC			BIT(1)
91 #define MWIFIEX_BD_FLAG_SOP				BIT(0)
92 #define MWIFIEX_BD_FLAG_EOP				BIT(1)
93 #define MWIFIEX_BD_FLAG_XS_SOP				BIT(2)
94 #define MWIFIEX_BD_FLAG_XS_EOP				BIT(3)
95 #define MWIFIEX_BD_FLAG_EVT_ROLLOVER_IND		BIT(7)
96 #define MWIFIEX_BD_FLAG_RX_ROLLOVER_IND			BIT(10)
97 #define MWIFIEX_BD_FLAG_TX_START_PTR			BIT(16)
98 #define MWIFIEX_BD_FLAG_TX_ROLLOVER_IND			BIT(26)
99 
100 /* Max retry number of command write */
101 #define MAX_WRITE_IOMEM_RETRY				2
102 /* Define PCIE block size for firmware download */
103 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD		256
104 /* FW awake cookie after FW ready */
105 #define FW_AWAKE_COOKIE						(0xAA55AA55)
106 #define MWIFIEX_DEF_SLEEP_COOKIE			0xBEEFBEEF
107 #define MWIFIEX_SLEEP_COOKIE_SIZE			4
108 #define MWIFIEX_MAX_DELAY_COUNT				100
109 
110 #define MWIFIEX_PCIE_FLR_HAPPENS 0xFEDCBABA
111 
112 struct mwifiex_pcie_card_reg {
113 	u16 cmd_addr_lo;
114 	u16 cmd_addr_hi;
115 	u16 fw_status;
116 	u16 cmd_size;
117 	u16 cmdrsp_addr_lo;
118 	u16 cmdrsp_addr_hi;
119 	u16 tx_rdptr;
120 	u16 tx_wrptr;
121 	u16 rx_rdptr;
122 	u16 rx_wrptr;
123 	u16 evt_rdptr;
124 	u16 evt_wrptr;
125 	u16 drv_rdy;
126 	u16 tx_start_ptr;
127 	u32 tx_mask;
128 	u32 tx_wrap_mask;
129 	u32 rx_mask;
130 	u32 rx_wrap_mask;
131 	u32 tx_rollover_ind;
132 	u32 rx_rollover_ind;
133 	u32 evt_rollover_ind;
134 	u8 ring_flag_sop;
135 	u8 ring_flag_eop;
136 	u8 ring_flag_xs_sop;
137 	u8 ring_flag_xs_eop;
138 	u32 ring_tx_start_ptr;
139 	u8 pfu_enabled;
140 	u8 sleep_cookie;
141 	u16 fw_dump_ctrl;
142 	u16 fw_dump_start;
143 	u16 fw_dump_end;
144 	u8 fw_dump_host_ready;
145 	u8 fw_dump_read_done;
146 	u8 msix_support;
147 };
148 
149 struct mwifiex_pcie_device {
150 	const struct mwifiex_pcie_card_reg *reg;
151 	u16 blksz_fw_dl;
152 	u16 tx_buf_size;
153 	bool can_dump_fw;
154 	struct memory_type_mapping *mem_type_mapping_tbl;
155 	u8 num_mem_types;
156 	bool can_ext_scan;
157 };
158 
159 struct mwifiex_evt_buf_desc {
160 	u64 paddr;
161 	u16 len;
162 	u16 flags;
163 } __packed;
164 
165 struct mwifiex_pcie_buf_desc {
166 	u64 paddr;
167 	u16 len;
168 	u16 flags;
169 } __packed;
170 
171 struct mwifiex_pfu_buf_desc {
172 	u16 flags;
173 	u16 offset;
174 	u16 frag_len;
175 	u16 len;
176 	u64 paddr;
177 	u32 reserved;
178 } __packed;
179 
180 #define MWIFIEX_NUM_MSIX_VECTORS   4
181 
182 struct mwifiex_msix_context {
183 	struct pci_dev *dev;
184 	u16 msg_id;
185 };
186 
187 struct pcie_service_card {
188 	struct pci_dev *dev;
189 	struct mwifiex_adapter *adapter;
190 	struct mwifiex_pcie_device pcie;
191 	struct completion fw_done;
192 
193 	u8 txbd_flush;
194 	u32 txbd_wrptr;
195 	u32 txbd_rdptr;
196 	u32 txbd_ring_size;
197 	u8 *txbd_ring_vbase;
198 	dma_addr_t txbd_ring_pbase;
199 	void *txbd_ring[MWIFIEX_MAX_TXRX_BD];
200 	struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
201 
202 	u32 rxbd_wrptr;
203 	u32 rxbd_rdptr;
204 	u32 rxbd_ring_size;
205 	u8 *rxbd_ring_vbase;
206 	dma_addr_t rxbd_ring_pbase;
207 	void *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
208 	struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
209 
210 	u32 evtbd_wrptr;
211 	u32 evtbd_rdptr;
212 	u32 evtbd_ring_size;
213 	u8 *evtbd_ring_vbase;
214 	dma_addr_t evtbd_ring_pbase;
215 	void *evtbd_ring[MWIFIEX_MAX_EVT_BD];
216 	struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
217 
218 	struct sk_buff *cmd_buf;
219 	struct sk_buff *cmdrsp_buf;
220 	u8 *sleep_cookie_vbase;
221 	dma_addr_t sleep_cookie_pbase;
222 	void __iomem *pci_mmap;
223 	void __iomem *pci_mmap1;
224 	int msi_enable;
225 	int msix_enable;
226 #ifdef CONFIG_PCI
227 	struct msix_entry msix_entries[MWIFIEX_NUM_MSIX_VECTORS];
228 #endif
229 	struct mwifiex_msix_context msix_ctx[MWIFIEX_NUM_MSIX_VECTORS];
230 	struct mwifiex_msix_context share_irq_ctx;
231 	struct work_struct work;
232 	unsigned long work_flags;
233 
234 	bool pci_reset_ongoing;
235 	unsigned long quirks;
236 };
237 
238 static inline int
mwifiex_pcie_txbd_empty(struct pcie_service_card * card,u32 rdptr)239 mwifiex_pcie_txbd_empty(struct pcie_service_card *card, u32 rdptr)
240 {
241 	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
242 
243 	switch (card->dev->device) {
244 	case PCIE_DEVICE_ID_MARVELL_88W8766P:
245 		if (((card->txbd_wrptr & reg->tx_mask) ==
246 		     (rdptr & reg->tx_mask)) &&
247 		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
248 		     (rdptr & reg->tx_rollover_ind)))
249 			return 1;
250 		break;
251 	case PCIE_DEVICE_ID_MARVELL_88W8897:
252 	case PCIE_DEVICE_ID_MARVELL_88W8997:
253 		if (((card->txbd_wrptr & reg->tx_mask) ==
254 		     (rdptr & reg->tx_mask)) &&
255 		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
256 			(rdptr & reg->tx_rollover_ind)))
257 			return 1;
258 		break;
259 	}
260 
261 	return 0;
262 }
263 
264 static inline int
mwifiex_pcie_txbd_not_full(struct pcie_service_card * card)265 mwifiex_pcie_txbd_not_full(struct pcie_service_card *card)
266 {
267 	const struct mwifiex_pcie_card_reg *reg = card->pcie.reg;
268 
269 	switch (card->dev->device) {
270 	case PCIE_DEVICE_ID_MARVELL_88W8766P:
271 		if (((card->txbd_wrptr & reg->tx_mask) !=
272 		     (card->txbd_rdptr & reg->tx_mask)) ||
273 		    ((card->txbd_wrptr & reg->tx_rollover_ind) !=
274 		     (card->txbd_rdptr & reg->tx_rollover_ind)))
275 			return 1;
276 		break;
277 	case PCIE_DEVICE_ID_MARVELL_88W8897:
278 	case PCIE_DEVICE_ID_MARVELL_88W8997:
279 		if (((card->txbd_wrptr & reg->tx_mask) !=
280 		     (card->txbd_rdptr & reg->tx_mask)) ||
281 		    ((card->txbd_wrptr & reg->tx_rollover_ind) ==
282 		     (card->txbd_rdptr & reg->tx_rollover_ind)))
283 			return 1;
284 		break;
285 	}
286 
287 	return 0;
288 }
289 
290 #endif /* _MWIFIEX_PCIE_H */
291