xref: /openbmc/linux/drivers/tty/serial/msm_serial.c (revision 7aa34bb3)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for msm7k serial device and console
4  *
5  * Copyright (C) 2007 Google, Inc.
6  * Author: Robert Love <rlove@google.com>
7  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8  */
9 
10 #include <linux/kernel.h>
11 #include <linux/atomic.h>
12 #include <linux/dma/qcom_adm.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmaengine.h>
15 #include <linux/module.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/interrupt.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial_core.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/of.h>
29 #include <linux/of_device.h>
30 #include <linux/wait.h>
31 
32 #define MSM_UART_MR1			0x0000
33 
34 #define MSM_UART_MR1_AUTO_RFR_LEVEL0	0x3F
35 #define MSM_UART_MR1_AUTO_RFR_LEVEL1	0x3FF00
36 #define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1	0xFFFFFF00
37 #define MSM_UART_MR1_RX_RDY_CTL		BIT(7)
38 #define MSM_UART_MR1_CTS_CTL		BIT(6)
39 
40 #define MSM_UART_MR2			0x0004
41 #define MSM_UART_MR2_ERROR_MODE		BIT(6)
42 #define MSM_UART_MR2_BITS_PER_CHAR	0x30
43 #define MSM_UART_MR2_BITS_PER_CHAR_5	(0x0 << 4)
44 #define MSM_UART_MR2_BITS_PER_CHAR_6	(0x1 << 4)
45 #define MSM_UART_MR2_BITS_PER_CHAR_7	(0x2 << 4)
46 #define MSM_UART_MR2_BITS_PER_CHAR_8	(0x3 << 4)
47 #define MSM_UART_MR2_STOP_BIT_LEN_ONE	(0x1 << 2)
48 #define MSM_UART_MR2_STOP_BIT_LEN_TWO	(0x3 << 2)
49 #define MSM_UART_MR2_PARITY_MODE_NONE	0x0
50 #define MSM_UART_MR2_PARITY_MODE_ODD	0x1
51 #define MSM_UART_MR2_PARITY_MODE_EVEN	0x2
52 #define MSM_UART_MR2_PARITY_MODE_SPACE	0x3
53 #define MSM_UART_MR2_PARITY_MODE	0x3
54 
55 #define MSM_UART_CSR			0x0008
56 
57 #define MSM_UART_TF			0x000C
58 #define UARTDM_TF			0x0070
59 
60 #define MSM_UART_CR				0x0010
61 #define MSM_UART_CR_CMD_NULL			(0 << 4)
62 #define MSM_UART_CR_CMD_RESET_RX		(1 << 4)
63 #define MSM_UART_CR_CMD_RESET_TX		(2 << 4)
64 #define MSM_UART_CR_CMD_RESET_ERR		(3 << 4)
65 #define MSM_UART_CR_CMD_RESET_BREAK_INT		(4 << 4)
66 #define MSM_UART_CR_CMD_START_BREAK		(5 << 4)
67 #define MSM_UART_CR_CMD_STOP_BREAK		(6 << 4)
68 #define MSM_UART_CR_CMD_RESET_CTS		(7 << 4)
69 #define MSM_UART_CR_CMD_RESET_STALE_INT		(8 << 4)
70 #define MSM_UART_CR_CMD_PACKET_MODE		(9 << 4)
71 #define MSM_UART_CR_CMD_MODE_RESET		(12 << 4)
72 #define MSM_UART_CR_CMD_SET_RFR			(13 << 4)
73 #define MSM_UART_CR_CMD_RESET_RFR		(14 << 4)
74 #define MSM_UART_CR_CMD_PROTECTION_EN		(16 << 4)
75 #define MSM_UART_CR_CMD_STALE_EVENT_DISABLE	(6 << 8)
76 #define MSM_UART_CR_CMD_STALE_EVENT_ENABLE	(80 << 4)
77 #define MSM_UART_CR_CMD_FORCE_STALE		(4 << 8)
78 #define MSM_UART_CR_CMD_RESET_TX_READY		(3 << 8)
79 #define MSM_UART_CR_TX_DISABLE			BIT(3)
80 #define MSM_UART_CR_TX_ENABLE			BIT(2)
81 #define MSM_UART_CR_RX_DISABLE			BIT(1)
82 #define MSM_UART_CR_RX_ENABLE			BIT(0)
83 #define MSM_UART_CR_CMD_RESET_RXBREAK_START	((1 << 11) | (2 << 4))
84 
85 #define MSM_UART_IMR			0x0014
86 #define MSM_UART_IMR_TXLEV		BIT(0)
87 #define MSM_UART_IMR_RXSTALE		BIT(3)
88 #define MSM_UART_IMR_RXLEV		BIT(4)
89 #define MSM_UART_IMR_DELTA_CTS		BIT(5)
90 #define MSM_UART_IMR_CURRENT_CTS	BIT(6)
91 #define MSM_UART_IMR_RXBREAK_START	BIT(10)
92 
93 #define MSM_UART_IPR_RXSTALE_LAST		0x20
94 #define MSM_UART_IPR_STALE_LSB			0x1F
95 #define MSM_UART_IPR_STALE_TIMEOUT_MSB		0x3FF80
96 #define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB	0xFFFFFF80
97 
98 #define MSM_UART_IPR			0x0018
99 #define MSM_UART_TFWR			0x001C
100 #define MSM_UART_RFWR			0x0020
101 #define MSM_UART_HCR			0x0024
102 
103 #define MSM_UART_MREG			0x0028
104 #define MSM_UART_NREG			0x002C
105 #define MSM_UART_DREG			0x0030
106 #define MSM_UART_MNDREG			0x0034
107 #define MSM_UART_IRDA			0x0038
108 #define MSM_UART_MISR_MODE		0x0040
109 #define MSM_UART_MISR_RESET		0x0044
110 #define MSM_UART_MISR_EXPORT		0x0048
111 #define MSM_UART_MISR_VAL		0x004C
112 #define MSM_UART_TEST_CTRL		0x0050
113 
114 #define MSM_UART_SR			0x0008
115 #define MSM_UART_SR_HUNT_CHAR		BIT(7)
116 #define MSM_UART_SR_RX_BREAK		BIT(6)
117 #define MSM_UART_SR_PAR_FRAME_ERR	BIT(5)
118 #define MSM_UART_SR_OVERRUN		BIT(4)
119 #define MSM_UART_SR_TX_EMPTY		BIT(3)
120 #define MSM_UART_SR_TX_READY		BIT(2)
121 #define MSM_UART_SR_RX_FULL		BIT(1)
122 #define MSM_UART_SR_RX_READY		BIT(0)
123 
124 #define MSM_UART_RF			0x000C
125 #define UARTDM_RF			0x0070
126 #define MSM_UART_MISR			0x0010
127 #define MSM_UART_ISR			0x0014
128 #define MSM_UART_ISR_TX_READY		BIT(7)
129 
130 #define UARTDM_RXFS			0x50
131 #define UARTDM_RXFS_BUF_SHIFT		0x7
132 #define UARTDM_RXFS_BUF_MASK		0x7
133 
134 #define UARTDM_DMEN			0x3C
135 #define UARTDM_DMEN_RX_SC_ENABLE	BIT(5)
136 #define UARTDM_DMEN_TX_SC_ENABLE	BIT(4)
137 
138 #define UARTDM_DMEN_TX_BAM_ENABLE	BIT(2)	/* UARTDM_1P4 */
139 #define UARTDM_DMEN_TX_DM_ENABLE	BIT(0)	/* < UARTDM_1P4 */
140 
141 #define UARTDM_DMEN_RX_BAM_ENABLE	BIT(3)	/* UARTDM_1P4 */
142 #define UARTDM_DMEN_RX_DM_ENABLE	BIT(1)	/* < UARTDM_1P4 */
143 
144 #define UARTDM_DMRX			0x34
145 #define UARTDM_NCF_TX			0x40
146 #define UARTDM_RX_TOTAL_SNAP		0x38
147 
148 #define UARTDM_BURST_SIZE		16   /* in bytes */
149 #define UARTDM_TX_AIGN(x)		((x) & ~0x3) /* valid for > 1p3 */
150 #define UARTDM_TX_MAX			256   /* in bytes, valid for <= 1p3 */
151 #define UARTDM_RX_SIZE			(UART_XMIT_SIZE / 4)
152 
153 enum {
154 	UARTDM_1P1 = 1,
155 	UARTDM_1P2,
156 	UARTDM_1P3,
157 	UARTDM_1P4,
158 };
159 
160 struct msm_dma {
161 	struct dma_chan		*chan;
162 	enum dma_data_direction dir;
163 	dma_addr_t		phys;
164 	unsigned char		*virt;
165 	dma_cookie_t		cookie;
166 	u32			enable_bit;
167 	unsigned int		count;
168 	struct dma_async_tx_descriptor	*desc;
169 };
170 
171 struct msm_port {
172 	struct uart_port	uart;
173 	char			name[16];
174 	struct clk		*clk;
175 	struct clk		*pclk;
176 	unsigned int		imr;
177 	int			is_uartdm;
178 	unsigned int		old_snap_state;
179 	bool			break_detected;
180 	struct msm_dma		tx_dma;
181 	struct msm_dma		rx_dma;
182 };
183 
to_msm_port(struct uart_port * up)184 static inline struct msm_port *to_msm_port(struct uart_port *up)
185 {
186 	return container_of(up, struct msm_port, uart);
187 }
188 
189 static
msm_write(struct uart_port * port,unsigned int val,unsigned int off)190 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
191 {
192 	writel_relaxed(val, port->membase + off);
193 }
194 
195 static
msm_read(struct uart_port * port,unsigned int off)196 unsigned int msm_read(struct uart_port *port, unsigned int off)
197 {
198 	return readl_relaxed(port->membase + off);
199 }
200 
201 /*
202  * Setup the MND registers to use the TCXO clock.
203  */
msm_serial_set_mnd_regs_tcxo(struct uart_port * port)204 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
205 {
206 	msm_write(port, 0x06, MSM_UART_MREG);
207 	msm_write(port, 0xF1, MSM_UART_NREG);
208 	msm_write(port, 0x0F, MSM_UART_DREG);
209 	msm_write(port, 0x1A, MSM_UART_MNDREG);
210 	port->uartclk = 1843200;
211 }
212 
213 /*
214  * Setup the MND registers to use the TCXO clock divided by 4.
215  */
msm_serial_set_mnd_regs_tcxoby4(struct uart_port * port)216 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
217 {
218 	msm_write(port, 0x18, MSM_UART_MREG);
219 	msm_write(port, 0xF6, MSM_UART_NREG);
220 	msm_write(port, 0x0F, MSM_UART_DREG);
221 	msm_write(port, 0x0A, MSM_UART_MNDREG);
222 	port->uartclk = 1843200;
223 }
224 
msm_serial_set_mnd_regs(struct uart_port * port)225 static void msm_serial_set_mnd_regs(struct uart_port *port)
226 {
227 	struct msm_port *msm_port = to_msm_port(port);
228 
229 	/*
230 	 * These registers don't exist so we change the clk input rate
231 	 * on uartdm hardware instead
232 	 */
233 	if (msm_port->is_uartdm)
234 		return;
235 
236 	if (port->uartclk == 19200000)
237 		msm_serial_set_mnd_regs_tcxo(port);
238 	else if (port->uartclk == 4800000)
239 		msm_serial_set_mnd_regs_tcxoby4(port);
240 }
241 
242 static void msm_handle_tx(struct uart_port *port);
243 static void msm_start_rx_dma(struct msm_port *msm_port);
244 
msm_stop_dma(struct uart_port * port,struct msm_dma * dma)245 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
246 {
247 	struct device *dev = port->dev;
248 	unsigned int mapped;
249 	u32 val;
250 
251 	mapped = dma->count;
252 	dma->count = 0;
253 
254 	dmaengine_terminate_all(dma->chan);
255 
256 	/*
257 	 * DMA Stall happens if enqueue and flush command happens concurrently.
258 	 * For example before changing the baud rate/protocol configuration and
259 	 * sending flush command to ADM, disable the channel of UARTDM.
260 	 * Note: should not reset the receiver here immediately as it is not
261 	 * suggested to do disable/reset or reset/disable at the same time.
262 	 */
263 	val = msm_read(port, UARTDM_DMEN);
264 	val &= ~dma->enable_bit;
265 	msm_write(port, val, UARTDM_DMEN);
266 
267 	if (mapped)
268 		dma_unmap_single(dev, dma->phys, mapped, dma->dir);
269 }
270 
msm_release_dma(struct msm_port * msm_port)271 static void msm_release_dma(struct msm_port *msm_port)
272 {
273 	struct msm_dma *dma;
274 
275 	dma = &msm_port->tx_dma;
276 	if (dma->chan) {
277 		msm_stop_dma(&msm_port->uart, dma);
278 		dma_release_channel(dma->chan);
279 	}
280 
281 	memset(dma, 0, sizeof(*dma));
282 
283 	dma = &msm_port->rx_dma;
284 	if (dma->chan) {
285 		msm_stop_dma(&msm_port->uart, dma);
286 		dma_release_channel(dma->chan);
287 		kfree(dma->virt);
288 	}
289 
290 	memset(dma, 0, sizeof(*dma));
291 }
292 
msm_request_tx_dma(struct msm_port * msm_port,resource_size_t base)293 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
294 {
295 	struct device *dev = msm_port->uart.dev;
296 	struct dma_slave_config conf;
297 	struct qcom_adm_peripheral_config periph_conf = {};
298 	struct msm_dma *dma;
299 	u32 crci = 0;
300 	int ret;
301 
302 	dma = &msm_port->tx_dma;
303 
304 	/* allocate DMA resources, if available */
305 	dma->chan = dma_request_chan(dev, "tx");
306 	if (IS_ERR(dma->chan))
307 		goto no_tx;
308 
309 	of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
310 
311 	memset(&conf, 0, sizeof(conf));
312 	conf.direction = DMA_MEM_TO_DEV;
313 	conf.device_fc = true;
314 	conf.dst_addr = base + UARTDM_TF;
315 	conf.dst_maxburst = UARTDM_BURST_SIZE;
316 	if (crci) {
317 		conf.peripheral_config = &periph_conf;
318 		conf.peripheral_size = sizeof(periph_conf);
319 		periph_conf.crci = crci;
320 	}
321 
322 	ret = dmaengine_slave_config(dma->chan, &conf);
323 	if (ret)
324 		goto rel_tx;
325 
326 	dma->dir = DMA_TO_DEVICE;
327 
328 	if (msm_port->is_uartdm < UARTDM_1P4)
329 		dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
330 	else
331 		dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
332 
333 	return;
334 
335 rel_tx:
336 	dma_release_channel(dma->chan);
337 no_tx:
338 	memset(dma, 0, sizeof(*dma));
339 }
340 
msm_request_rx_dma(struct msm_port * msm_port,resource_size_t base)341 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
342 {
343 	struct device *dev = msm_port->uart.dev;
344 	struct dma_slave_config conf;
345 	struct qcom_adm_peripheral_config periph_conf = {};
346 	struct msm_dma *dma;
347 	u32 crci = 0;
348 	int ret;
349 
350 	dma = &msm_port->rx_dma;
351 
352 	/* allocate DMA resources, if available */
353 	dma->chan = dma_request_chan(dev, "rx");
354 	if (IS_ERR(dma->chan))
355 		goto no_rx;
356 
357 	of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
358 
359 	dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
360 	if (!dma->virt)
361 		goto rel_rx;
362 
363 	memset(&conf, 0, sizeof(conf));
364 	conf.direction = DMA_DEV_TO_MEM;
365 	conf.device_fc = true;
366 	conf.src_addr = base + UARTDM_RF;
367 	conf.src_maxburst = UARTDM_BURST_SIZE;
368 	if (crci) {
369 		conf.peripheral_config = &periph_conf;
370 		conf.peripheral_size = sizeof(periph_conf);
371 		periph_conf.crci = crci;
372 	}
373 
374 	ret = dmaengine_slave_config(dma->chan, &conf);
375 	if (ret)
376 		goto err;
377 
378 	dma->dir = DMA_FROM_DEVICE;
379 
380 	if (msm_port->is_uartdm < UARTDM_1P4)
381 		dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
382 	else
383 		dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
384 
385 	return;
386 err:
387 	kfree(dma->virt);
388 rel_rx:
389 	dma_release_channel(dma->chan);
390 no_rx:
391 	memset(dma, 0, sizeof(*dma));
392 }
393 
msm_wait_for_xmitr(struct uart_port * port)394 static inline void msm_wait_for_xmitr(struct uart_port *port)
395 {
396 	unsigned int timeout = 500000;
397 
398 	while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) {
399 		if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY)
400 			break;
401 		udelay(1);
402 		if (!timeout--)
403 			break;
404 	}
405 	msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR);
406 }
407 
msm_stop_tx(struct uart_port * port)408 static void msm_stop_tx(struct uart_port *port)
409 {
410 	struct msm_port *msm_port = to_msm_port(port);
411 
412 	msm_port->imr &= ~MSM_UART_IMR_TXLEV;
413 	msm_write(port, msm_port->imr, MSM_UART_IMR);
414 }
415 
msm_start_tx(struct uart_port * port)416 static void msm_start_tx(struct uart_port *port)
417 {
418 	struct msm_port *msm_port = to_msm_port(port);
419 	struct msm_dma *dma = &msm_port->tx_dma;
420 
421 	/* Already started in DMA mode */
422 	if (dma->count)
423 		return;
424 
425 	msm_port->imr |= MSM_UART_IMR_TXLEV;
426 	msm_write(port, msm_port->imr, MSM_UART_IMR);
427 }
428 
msm_reset_dm_count(struct uart_port * port,int count)429 static void msm_reset_dm_count(struct uart_port *port, int count)
430 {
431 	msm_wait_for_xmitr(port);
432 	msm_write(port, count, UARTDM_NCF_TX);
433 	msm_read(port, UARTDM_NCF_TX);
434 }
435 
msm_complete_tx_dma(void * args)436 static void msm_complete_tx_dma(void *args)
437 {
438 	struct msm_port *msm_port = args;
439 	struct uart_port *port = &msm_port->uart;
440 	struct circ_buf *xmit = &port->state->xmit;
441 	struct msm_dma *dma = &msm_port->tx_dma;
442 	struct dma_tx_state state;
443 	unsigned long flags;
444 	unsigned int count;
445 	u32 val;
446 
447 	spin_lock_irqsave(&port->lock, flags);
448 
449 	/* Already stopped */
450 	if (!dma->count)
451 		goto done;
452 
453 	dmaengine_tx_status(dma->chan, dma->cookie, &state);
454 
455 	dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
456 
457 	val = msm_read(port, UARTDM_DMEN);
458 	val &= ~dma->enable_bit;
459 	msm_write(port, val, UARTDM_DMEN);
460 
461 	if (msm_port->is_uartdm > UARTDM_1P3) {
462 		msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
463 		msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR);
464 	}
465 
466 	count = dma->count - state.residue;
467 	uart_xmit_advance(port, count);
468 	dma->count = 0;
469 
470 	/* Restore "Tx FIFO below watermark" interrupt */
471 	msm_port->imr |= MSM_UART_IMR_TXLEV;
472 	msm_write(port, msm_port->imr, MSM_UART_IMR);
473 
474 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
475 		uart_write_wakeup(port);
476 
477 	msm_handle_tx(port);
478 done:
479 	spin_unlock_irqrestore(&port->lock, flags);
480 }
481 
msm_handle_tx_dma(struct msm_port * msm_port,unsigned int count)482 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
483 {
484 	struct circ_buf *xmit = &msm_port->uart.state->xmit;
485 	struct uart_port *port = &msm_port->uart;
486 	struct msm_dma *dma = &msm_port->tx_dma;
487 	void *cpu_addr;
488 	int ret;
489 	u32 val;
490 
491 	cpu_addr = &xmit->buf[xmit->tail];
492 
493 	dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
494 	ret = dma_mapping_error(port->dev, dma->phys);
495 	if (ret)
496 		return ret;
497 
498 	dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
499 						count, DMA_MEM_TO_DEV,
500 						DMA_PREP_INTERRUPT |
501 						DMA_PREP_FENCE);
502 	if (!dma->desc) {
503 		ret = -EIO;
504 		goto unmap;
505 	}
506 
507 	dma->desc->callback = msm_complete_tx_dma;
508 	dma->desc->callback_param = msm_port;
509 
510 	dma->cookie = dmaengine_submit(dma->desc);
511 	ret = dma_submit_error(dma->cookie);
512 	if (ret)
513 		goto unmap;
514 
515 	/*
516 	 * Using DMA complete for Tx FIFO reload, no need for
517 	 * "Tx FIFO below watermark" one, disable it
518 	 */
519 	msm_port->imr &= ~MSM_UART_IMR_TXLEV;
520 	msm_write(port, msm_port->imr, MSM_UART_IMR);
521 
522 	dma->count = count;
523 
524 	val = msm_read(port, UARTDM_DMEN);
525 	val |= dma->enable_bit;
526 
527 	if (msm_port->is_uartdm < UARTDM_1P4)
528 		msm_write(port, val, UARTDM_DMEN);
529 
530 	msm_reset_dm_count(port, count);
531 
532 	if (msm_port->is_uartdm > UARTDM_1P3)
533 		msm_write(port, val, UARTDM_DMEN);
534 
535 	dma_async_issue_pending(dma->chan);
536 	return 0;
537 unmap:
538 	dma_unmap_single(port->dev, dma->phys, count, dma->dir);
539 	return ret;
540 }
541 
msm_complete_rx_dma(void * args)542 static void msm_complete_rx_dma(void *args)
543 {
544 	struct msm_port *msm_port = args;
545 	struct uart_port *port = &msm_port->uart;
546 	struct tty_port *tport = &port->state->port;
547 	struct msm_dma *dma = &msm_port->rx_dma;
548 	int count = 0, i, sysrq;
549 	unsigned long flags;
550 	u32 val;
551 
552 	spin_lock_irqsave(&port->lock, flags);
553 
554 	/* Already stopped */
555 	if (!dma->count)
556 		goto done;
557 
558 	val = msm_read(port, UARTDM_DMEN);
559 	val &= ~dma->enable_bit;
560 	msm_write(port, val, UARTDM_DMEN);
561 
562 	if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) {
563 		port->icount.overrun++;
564 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
565 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
566 	}
567 
568 	count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
569 
570 	port->icount.rx += count;
571 
572 	dma->count = 0;
573 
574 	dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
575 
576 	for (i = 0; i < count; i++) {
577 		char flag = TTY_NORMAL;
578 
579 		if (msm_port->break_detected && dma->virt[i] == 0) {
580 			port->icount.brk++;
581 			flag = TTY_BREAK;
582 			msm_port->break_detected = false;
583 			if (uart_handle_break(port))
584 				continue;
585 		}
586 
587 		if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
588 			flag = TTY_NORMAL;
589 
590 		spin_unlock_irqrestore(&port->lock, flags);
591 		sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
592 		spin_lock_irqsave(&port->lock, flags);
593 		if (!sysrq)
594 			tty_insert_flip_char(tport, dma->virt[i], flag);
595 	}
596 
597 	msm_start_rx_dma(msm_port);
598 done:
599 	spin_unlock_irqrestore(&port->lock, flags);
600 
601 	if (count)
602 		tty_flip_buffer_push(tport);
603 }
604 
msm_start_rx_dma(struct msm_port * msm_port)605 static void msm_start_rx_dma(struct msm_port *msm_port)
606 {
607 	struct msm_dma *dma = &msm_port->rx_dma;
608 	struct uart_port *uart = &msm_port->uart;
609 	u32 val;
610 	int ret;
611 
612 	if (IS_ENABLED(CONFIG_CONSOLE_POLL))
613 		return;
614 
615 	if (!dma->chan)
616 		return;
617 
618 	dma->phys = dma_map_single(uart->dev, dma->virt,
619 				   UARTDM_RX_SIZE, dma->dir);
620 	ret = dma_mapping_error(uart->dev, dma->phys);
621 	if (ret)
622 		goto sw_mode;
623 
624 	dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
625 						UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
626 						DMA_PREP_INTERRUPT);
627 	if (!dma->desc)
628 		goto unmap;
629 
630 	dma->desc->callback = msm_complete_rx_dma;
631 	dma->desc->callback_param = msm_port;
632 
633 	dma->cookie = dmaengine_submit(dma->desc);
634 	ret = dma_submit_error(dma->cookie);
635 	if (ret)
636 		goto unmap;
637 	/*
638 	 * Using DMA for FIFO off-load, no need for "Rx FIFO over
639 	 * watermark" or "stale" interrupts, disable them
640 	 */
641 	msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
642 
643 	/*
644 	 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
645 	 * we need RXSTALE to flush input DMA fifo to memory
646 	 */
647 	if (msm_port->is_uartdm < UARTDM_1P4)
648 		msm_port->imr |= MSM_UART_IMR_RXSTALE;
649 
650 	msm_write(uart, msm_port->imr, MSM_UART_IMR);
651 
652 	dma->count = UARTDM_RX_SIZE;
653 
654 	dma_async_issue_pending(dma->chan);
655 
656 	msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
657 	msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
658 
659 	val = msm_read(uart, UARTDM_DMEN);
660 	val |= dma->enable_bit;
661 
662 	if (msm_port->is_uartdm < UARTDM_1P4)
663 		msm_write(uart, val, UARTDM_DMEN);
664 
665 	msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
666 
667 	if (msm_port->is_uartdm > UARTDM_1P3)
668 		msm_write(uart, val, UARTDM_DMEN);
669 
670 	return;
671 unmap:
672 	dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
673 
674 sw_mode:
675 	/*
676 	 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
677 	 * receiver must be reset.
678 	 */
679 	msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
680 	msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
681 
682 	msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
683 	msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
684 	msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
685 
686 	/* Re-enable RX interrupts */
687 	msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE;
688 	msm_write(uart, msm_port->imr, MSM_UART_IMR);
689 }
690 
msm_stop_rx(struct uart_port * port)691 static void msm_stop_rx(struct uart_port *port)
692 {
693 	struct msm_port *msm_port = to_msm_port(port);
694 	struct msm_dma *dma = &msm_port->rx_dma;
695 
696 	msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE);
697 	msm_write(port, msm_port->imr, MSM_UART_IMR);
698 
699 	if (dma->chan)
700 		msm_stop_dma(port, dma);
701 }
702 
msm_enable_ms(struct uart_port * port)703 static void msm_enable_ms(struct uart_port *port)
704 {
705 	struct msm_port *msm_port = to_msm_port(port);
706 
707 	msm_port->imr |= MSM_UART_IMR_DELTA_CTS;
708 	msm_write(port, msm_port->imr, MSM_UART_IMR);
709 }
710 
msm_handle_rx_dm(struct uart_port * port,unsigned int misr)711 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
712 	__must_hold(&port->lock)
713 {
714 	struct tty_port *tport = &port->state->port;
715 	unsigned int sr;
716 	int count = 0;
717 	struct msm_port *msm_port = to_msm_port(port);
718 
719 	if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
720 		port->icount.overrun++;
721 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
722 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
723 	}
724 
725 	if (misr & MSM_UART_IMR_RXSTALE) {
726 		count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
727 			msm_port->old_snap_state;
728 		msm_port->old_snap_state = 0;
729 	} else {
730 		count = 4 * (msm_read(port, MSM_UART_RFWR));
731 		msm_port->old_snap_state += count;
732 	}
733 
734 	/* TODO: Precise error reporting */
735 
736 	port->icount.rx += count;
737 
738 	while (count > 0) {
739 		unsigned char buf[4];
740 		int sysrq, r_count, i;
741 
742 		sr = msm_read(port, MSM_UART_SR);
743 		if ((sr & MSM_UART_SR_RX_READY) == 0) {
744 			msm_port->old_snap_state -= count;
745 			break;
746 		}
747 
748 		ioread32_rep(port->membase + UARTDM_RF, buf, 1);
749 		r_count = min_t(int, count, sizeof(buf));
750 
751 		for (i = 0; i < r_count; i++) {
752 			char flag = TTY_NORMAL;
753 
754 			if (msm_port->break_detected && buf[i] == 0) {
755 				port->icount.brk++;
756 				flag = TTY_BREAK;
757 				msm_port->break_detected = false;
758 				if (uart_handle_break(port))
759 					continue;
760 			}
761 
762 			if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK))
763 				flag = TTY_NORMAL;
764 
765 			spin_unlock(&port->lock);
766 			sysrq = uart_handle_sysrq_char(port, buf[i]);
767 			spin_lock(&port->lock);
768 			if (!sysrq)
769 				tty_insert_flip_char(tport, buf[i], flag);
770 		}
771 		count -= r_count;
772 	}
773 
774 	tty_flip_buffer_push(tport);
775 
776 	if (misr & (MSM_UART_IMR_RXSTALE))
777 		msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
778 	msm_write(port, 0xFFFFFF, UARTDM_DMRX);
779 	msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
780 
781 	/* Try to use DMA */
782 	msm_start_rx_dma(msm_port);
783 }
784 
msm_handle_rx(struct uart_port * port)785 static void msm_handle_rx(struct uart_port *port)
786 	__must_hold(&port->lock)
787 {
788 	struct tty_port *tport = &port->state->port;
789 	unsigned int sr;
790 
791 	/*
792 	 * Handle overrun. My understanding of the hardware is that overrun
793 	 * is not tied to the RX buffer, so we handle the case out of band.
794 	 */
795 	if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) {
796 		port->icount.overrun++;
797 		tty_insert_flip_char(tport, 0, TTY_OVERRUN);
798 		msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
799 	}
800 
801 	/* and now the main RX loop */
802 	while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) {
803 		unsigned int c;
804 		char flag = TTY_NORMAL;
805 		int sysrq;
806 
807 		c = msm_read(port, MSM_UART_RF);
808 
809 		if (sr & MSM_UART_SR_RX_BREAK) {
810 			port->icount.brk++;
811 			if (uart_handle_break(port))
812 				continue;
813 		} else if (sr & MSM_UART_SR_PAR_FRAME_ERR) {
814 			port->icount.frame++;
815 		} else {
816 			port->icount.rx++;
817 		}
818 
819 		/* Mask conditions we're ignoring. */
820 		sr &= port->read_status_mask;
821 
822 		if (sr & MSM_UART_SR_RX_BREAK)
823 			flag = TTY_BREAK;
824 		else if (sr & MSM_UART_SR_PAR_FRAME_ERR)
825 			flag = TTY_FRAME;
826 
827 		spin_unlock(&port->lock);
828 		sysrq = uart_handle_sysrq_char(port, c);
829 		spin_lock(&port->lock);
830 		if (!sysrq)
831 			tty_insert_flip_char(tport, c, flag);
832 	}
833 
834 	tty_flip_buffer_push(tport);
835 }
836 
msm_handle_tx_pio(struct uart_port * port,unsigned int tx_count)837 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
838 {
839 	struct circ_buf *xmit = &port->state->xmit;
840 	struct msm_port *msm_port = to_msm_port(port);
841 	unsigned int num_chars;
842 	unsigned int tf_pointer = 0;
843 	void __iomem *tf;
844 
845 	if (msm_port->is_uartdm)
846 		tf = port->membase + UARTDM_TF;
847 	else
848 		tf = port->membase + MSM_UART_TF;
849 
850 	if (tx_count && msm_port->is_uartdm)
851 		msm_reset_dm_count(port, tx_count);
852 
853 	while (tf_pointer < tx_count) {
854 		int i;
855 		char buf[4] = { 0 };
856 
857 		if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
858 			break;
859 
860 		if (msm_port->is_uartdm)
861 			num_chars = min(tx_count - tf_pointer,
862 					(unsigned int)sizeof(buf));
863 		else
864 			num_chars = 1;
865 
866 		for (i = 0; i < num_chars; i++)
867 			buf[i] = xmit->buf[xmit->tail + i];
868 
869 		iowrite32_rep(tf, buf, 1);
870 		uart_xmit_advance(port, num_chars);
871 		tf_pointer += num_chars;
872 	}
873 
874 	/* disable tx interrupts if nothing more to send */
875 	if (uart_circ_empty(xmit))
876 		msm_stop_tx(port);
877 
878 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
879 		uart_write_wakeup(port);
880 }
881 
msm_handle_tx(struct uart_port * port)882 static void msm_handle_tx(struct uart_port *port)
883 {
884 	struct msm_port *msm_port = to_msm_port(port);
885 	struct circ_buf *xmit = &msm_port->uart.state->xmit;
886 	struct msm_dma *dma = &msm_port->tx_dma;
887 	unsigned int pio_count, dma_count, dma_min;
888 	char buf[4] = { 0 };
889 	void __iomem *tf;
890 	int err = 0;
891 
892 	if (port->x_char) {
893 		if (msm_port->is_uartdm)
894 			tf = port->membase + UARTDM_TF;
895 		else
896 			tf = port->membase + MSM_UART_TF;
897 
898 		buf[0] = port->x_char;
899 
900 		if (msm_port->is_uartdm)
901 			msm_reset_dm_count(port, 1);
902 
903 		iowrite32_rep(tf, buf, 1);
904 		port->icount.tx++;
905 		port->x_char = 0;
906 		return;
907 	}
908 
909 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
910 		msm_stop_tx(port);
911 		return;
912 	}
913 
914 	pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
915 	dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
916 
917 	dma_min = 1;	/* Always DMA */
918 	if (msm_port->is_uartdm > UARTDM_1P3) {
919 		dma_count = UARTDM_TX_AIGN(dma_count);
920 		dma_min = UARTDM_BURST_SIZE;
921 	} else {
922 		if (dma_count > UARTDM_TX_MAX)
923 			dma_count = UARTDM_TX_MAX;
924 	}
925 
926 	if (pio_count > port->fifosize)
927 		pio_count = port->fifosize;
928 
929 	if (!dma->chan || dma_count < dma_min)
930 		msm_handle_tx_pio(port, pio_count);
931 	else
932 		err = msm_handle_tx_dma(msm_port, dma_count);
933 
934 	if (err)	/* fall back to PIO mode */
935 		msm_handle_tx_pio(port, pio_count);
936 }
937 
msm_handle_delta_cts(struct uart_port * port)938 static void msm_handle_delta_cts(struct uart_port *port)
939 {
940 	msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
941 	port->icount.cts++;
942 	wake_up_interruptible(&port->state->port.delta_msr_wait);
943 }
944 
msm_uart_irq(int irq,void * dev_id)945 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
946 {
947 	struct uart_port *port = dev_id;
948 	struct msm_port *msm_port = to_msm_port(port);
949 	struct msm_dma *dma = &msm_port->rx_dma;
950 	unsigned long flags;
951 	unsigned int misr;
952 	u32 val;
953 
954 	spin_lock_irqsave(&port->lock, flags);
955 	misr = msm_read(port, MSM_UART_MISR);
956 	msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */
957 
958 	if (misr & MSM_UART_IMR_RXBREAK_START) {
959 		msm_port->break_detected = true;
960 		msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR);
961 	}
962 
963 	if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) {
964 		if (dma->count) {
965 			val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE;
966 			msm_write(port, val, MSM_UART_CR);
967 			val = MSM_UART_CR_CMD_RESET_STALE_INT;
968 			msm_write(port, val, MSM_UART_CR);
969 			/*
970 			 * Flush DMA input fifo to memory, this will also
971 			 * trigger DMA RX completion
972 			 */
973 			dmaengine_terminate_all(dma->chan);
974 		} else if (msm_port->is_uartdm) {
975 			msm_handle_rx_dm(port, misr);
976 		} else {
977 			msm_handle_rx(port);
978 		}
979 	}
980 	if (misr & MSM_UART_IMR_TXLEV)
981 		msm_handle_tx(port);
982 	if (misr & MSM_UART_IMR_DELTA_CTS)
983 		msm_handle_delta_cts(port);
984 
985 	msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */
986 	spin_unlock_irqrestore(&port->lock, flags);
987 
988 	return IRQ_HANDLED;
989 }
990 
msm_tx_empty(struct uart_port * port)991 static unsigned int msm_tx_empty(struct uart_port *port)
992 {
993 	return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
994 }
995 
msm_get_mctrl(struct uart_port * port)996 static unsigned int msm_get_mctrl(struct uart_port *port)
997 {
998 	return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
999 }
1000 
msm_reset(struct uart_port * port)1001 static void msm_reset(struct uart_port *port)
1002 {
1003 	struct msm_port *msm_port = to_msm_port(port);
1004 	unsigned int mr;
1005 
1006 	/* reset everything */
1007 	msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR);
1008 	msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR);
1009 	msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR);
1010 	msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR);
1011 	msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR);
1012 	msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1013 	mr = msm_read(port, MSM_UART_MR1);
1014 	mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1015 	msm_write(port, mr, MSM_UART_MR1);
1016 
1017 	/* Disable DM modes */
1018 	if (msm_port->is_uartdm)
1019 		msm_write(port, 0, UARTDM_DMEN);
1020 }
1021 
msm_set_mctrl(struct uart_port * port,unsigned int mctrl)1022 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1023 {
1024 	unsigned int mr;
1025 
1026 	mr = msm_read(port, MSM_UART_MR1);
1027 
1028 	if (!(mctrl & TIOCM_RTS)) {
1029 		mr &= ~MSM_UART_MR1_RX_RDY_CTL;
1030 		msm_write(port, mr, MSM_UART_MR1);
1031 		msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR);
1032 	} else {
1033 		mr |= MSM_UART_MR1_RX_RDY_CTL;
1034 		msm_write(port, mr, MSM_UART_MR1);
1035 	}
1036 }
1037 
msm_break_ctl(struct uart_port * port,int break_ctl)1038 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1039 {
1040 	if (break_ctl)
1041 		msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR);
1042 	else
1043 		msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR);
1044 }
1045 
1046 struct msm_baud_map {
1047 	u16	divisor;
1048 	u8	code;
1049 	u8	rxstale;
1050 };
1051 
1052 static const struct msm_baud_map *
msm_find_best_baud(struct uart_port * port,unsigned int baud,unsigned long * rate)1053 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1054 		   unsigned long *rate)
1055 {
1056 	struct msm_port *msm_port = to_msm_port(port);
1057 	unsigned int divisor, result;
1058 	unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1059 	const struct msm_baud_map *entry, *end, *best;
1060 	static const struct msm_baud_map table[] = {
1061 		{    1, 0xff, 31 },
1062 		{    2, 0xee, 16 },
1063 		{    3, 0xdd,  8 },
1064 		{    4, 0xcc,  6 },
1065 		{    6, 0xbb,  6 },
1066 		{    8, 0xaa,  6 },
1067 		{   12, 0x99,  6 },
1068 		{   16, 0x88,  1 },
1069 		{   24, 0x77,  1 },
1070 		{   32, 0x66,  1 },
1071 		{   48, 0x55,  1 },
1072 		{   96, 0x44,  1 },
1073 		{  192, 0x33,  1 },
1074 		{  384, 0x22,  1 },
1075 		{  768, 0x11,  1 },
1076 		{ 1536, 0x00,  1 },
1077 	};
1078 
1079 	best = table; /* Default to smallest divider */
1080 	target = clk_round_rate(msm_port->clk, 16 * baud);
1081 	divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1082 
1083 	end = table + ARRAY_SIZE(table);
1084 	entry = table;
1085 	while (entry < end) {
1086 		if (entry->divisor <= divisor) {
1087 			result = target / entry->divisor / 16;
1088 			diff = abs(result - baud);
1089 
1090 			/* Keep track of best entry */
1091 			if (diff < best_diff) {
1092 				best_diff = diff;
1093 				best = entry;
1094 				best_rate = target;
1095 			}
1096 
1097 			if (result == baud)
1098 				break;
1099 		} else if (entry->divisor > divisor) {
1100 			old = target;
1101 			target = clk_round_rate(msm_port->clk, old + 1);
1102 			/*
1103 			 * The rate didn't get any faster so we can't do
1104 			 * better at dividing it down
1105 			 */
1106 			if (target == old)
1107 				break;
1108 
1109 			/* Start the divisor search over at this new rate */
1110 			entry = table;
1111 			divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1112 			continue;
1113 		}
1114 		entry++;
1115 	}
1116 
1117 	*rate = best_rate;
1118 	return best;
1119 }
1120 
msm_set_baud_rate(struct uart_port * port,unsigned int baud,unsigned long * saved_flags)1121 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1122 			     unsigned long *saved_flags)
1123 	__must_hold(&port->lock)
1124 {
1125 	unsigned int rxstale, watermark, mask;
1126 	struct msm_port *msm_port = to_msm_port(port);
1127 	const struct msm_baud_map *entry;
1128 	unsigned long flags, rate;
1129 
1130 	flags = *saved_flags;
1131 	spin_unlock_irqrestore(&port->lock, flags);
1132 
1133 	entry = msm_find_best_baud(port, baud, &rate);
1134 	clk_set_rate(msm_port->clk, rate);
1135 	baud = rate / 16 / entry->divisor;
1136 
1137 	spin_lock_irqsave(&port->lock, flags);
1138 	*saved_flags = flags;
1139 	port->uartclk = rate;
1140 
1141 	msm_write(port, entry->code, MSM_UART_CSR);
1142 
1143 	/* RX stale watermark */
1144 	rxstale = entry->rxstale;
1145 	watermark = MSM_UART_IPR_STALE_LSB & rxstale;
1146 	if (msm_port->is_uartdm) {
1147 		mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB;
1148 	} else {
1149 		watermark |= MSM_UART_IPR_RXSTALE_LAST;
1150 		mask = MSM_UART_IPR_STALE_TIMEOUT_MSB;
1151 	}
1152 
1153 	watermark |= mask & (rxstale << 2);
1154 
1155 	msm_write(port, watermark, MSM_UART_IPR);
1156 
1157 	/* set RX watermark */
1158 	watermark = (port->fifosize * 3) / 4;
1159 	msm_write(port, watermark, MSM_UART_RFWR);
1160 
1161 	/* set TX watermark */
1162 	msm_write(port, 10, MSM_UART_TFWR);
1163 
1164 	msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR);
1165 	msm_reset(port);
1166 
1167 	/* Enable RX and TX */
1168 	msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR);
1169 
1170 	/* turn on RX and CTS interrupts */
1171 	msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE |
1172 			MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START;
1173 
1174 	msm_write(port, msm_port->imr, MSM_UART_IMR);
1175 
1176 	if (msm_port->is_uartdm) {
1177 		msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1178 		msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1179 		msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1180 	}
1181 
1182 	return baud;
1183 }
1184 
msm_init_clock(struct uart_port * port)1185 static void msm_init_clock(struct uart_port *port)
1186 {
1187 	struct msm_port *msm_port = to_msm_port(port);
1188 
1189 	clk_prepare_enable(msm_port->clk);
1190 	clk_prepare_enable(msm_port->pclk);
1191 	msm_serial_set_mnd_regs(port);
1192 }
1193 
msm_startup(struct uart_port * port)1194 static int msm_startup(struct uart_port *port)
1195 {
1196 	struct msm_port *msm_port = to_msm_port(port);
1197 	unsigned int data, rfr_level, mask;
1198 	int ret;
1199 
1200 	snprintf(msm_port->name, sizeof(msm_port->name),
1201 		 "msm_serial%d", port->line);
1202 
1203 	msm_init_clock(port);
1204 
1205 	if (likely(port->fifosize > 12))
1206 		rfr_level = port->fifosize - 12;
1207 	else
1208 		rfr_level = port->fifosize;
1209 
1210 	/* set automatic RFR level */
1211 	data = msm_read(port, MSM_UART_MR1);
1212 
1213 	if (msm_port->is_uartdm)
1214 		mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1;
1215 	else
1216 		mask = MSM_UART_MR1_AUTO_RFR_LEVEL1;
1217 
1218 	data &= ~mask;
1219 	data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0;
1220 	data |= mask & (rfr_level << 2);
1221 	data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1222 	msm_write(port, data, MSM_UART_MR1);
1223 
1224 	if (msm_port->is_uartdm) {
1225 		msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1226 		msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1227 	}
1228 
1229 	ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1230 			  msm_port->name, port);
1231 	if (unlikely(ret))
1232 		goto err_irq;
1233 
1234 	return 0;
1235 
1236 err_irq:
1237 	if (msm_port->is_uartdm)
1238 		msm_release_dma(msm_port);
1239 
1240 	clk_disable_unprepare(msm_port->pclk);
1241 	clk_disable_unprepare(msm_port->clk);
1242 
1243 	return ret;
1244 }
1245 
msm_shutdown(struct uart_port * port)1246 static void msm_shutdown(struct uart_port *port)
1247 {
1248 	struct msm_port *msm_port = to_msm_port(port);
1249 
1250 	msm_port->imr = 0;
1251 	msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */
1252 
1253 	if (msm_port->is_uartdm)
1254 		msm_release_dma(msm_port);
1255 
1256 	clk_disable_unprepare(msm_port->clk);
1257 
1258 	free_irq(port->irq, port);
1259 }
1260 
msm_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1261 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1262 			    const struct ktermios *old)
1263 {
1264 	struct msm_port *msm_port = to_msm_port(port);
1265 	struct msm_dma *dma = &msm_port->rx_dma;
1266 	unsigned long flags;
1267 	unsigned int baud, mr;
1268 
1269 	spin_lock_irqsave(&port->lock, flags);
1270 
1271 	if (dma->chan) /* Terminate if any */
1272 		msm_stop_dma(port, dma);
1273 
1274 	/* calculate and set baud rate */
1275 	baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1276 	baud = msm_set_baud_rate(port, baud, &flags);
1277 	if (tty_termios_baud_rate(termios))
1278 		tty_termios_encode_baud_rate(termios, baud, baud);
1279 
1280 	/* calculate parity */
1281 	mr = msm_read(port, MSM_UART_MR2);
1282 	mr &= ~MSM_UART_MR2_PARITY_MODE;
1283 	if (termios->c_cflag & PARENB) {
1284 		if (termios->c_cflag & PARODD)
1285 			mr |= MSM_UART_MR2_PARITY_MODE_ODD;
1286 		else if (termios->c_cflag & CMSPAR)
1287 			mr |= MSM_UART_MR2_PARITY_MODE_SPACE;
1288 		else
1289 			mr |= MSM_UART_MR2_PARITY_MODE_EVEN;
1290 	}
1291 
1292 	/* calculate bits per char */
1293 	mr &= ~MSM_UART_MR2_BITS_PER_CHAR;
1294 	switch (termios->c_cflag & CSIZE) {
1295 	case CS5:
1296 		mr |= MSM_UART_MR2_BITS_PER_CHAR_5;
1297 		break;
1298 	case CS6:
1299 		mr |= MSM_UART_MR2_BITS_PER_CHAR_6;
1300 		break;
1301 	case CS7:
1302 		mr |= MSM_UART_MR2_BITS_PER_CHAR_7;
1303 		break;
1304 	case CS8:
1305 	default:
1306 		mr |= MSM_UART_MR2_BITS_PER_CHAR_8;
1307 		break;
1308 	}
1309 
1310 	/* calculate stop bits */
1311 	mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO);
1312 	if (termios->c_cflag & CSTOPB)
1313 		mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO;
1314 	else
1315 		mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE;
1316 
1317 	/* set parity, bits per char, and stop bit */
1318 	msm_write(port, mr, MSM_UART_MR2);
1319 
1320 	/* calculate and set hardware flow control */
1321 	mr = msm_read(port, MSM_UART_MR1);
1322 	mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL);
1323 	if (termios->c_cflag & CRTSCTS) {
1324 		mr |= MSM_UART_MR1_CTS_CTL;
1325 		mr |= MSM_UART_MR1_RX_RDY_CTL;
1326 	}
1327 	msm_write(port, mr, MSM_UART_MR1);
1328 
1329 	/* Configure status bits to ignore based on termio flags. */
1330 	port->read_status_mask = 0;
1331 	if (termios->c_iflag & INPCK)
1332 		port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR;
1333 	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1334 		port->read_status_mask |= MSM_UART_SR_RX_BREAK;
1335 
1336 	uart_update_timeout(port, termios->c_cflag, baud);
1337 
1338 	/* Try to use DMA */
1339 	msm_start_rx_dma(msm_port);
1340 
1341 	spin_unlock_irqrestore(&port->lock, flags);
1342 }
1343 
msm_type(struct uart_port * port)1344 static const char *msm_type(struct uart_port *port)
1345 {
1346 	return "MSM";
1347 }
1348 
msm_release_port(struct uart_port * port)1349 static void msm_release_port(struct uart_port *port)
1350 {
1351 	struct platform_device *pdev = to_platform_device(port->dev);
1352 	struct resource *uart_resource;
1353 	resource_size_t size;
1354 
1355 	uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356 	if (unlikely(!uart_resource))
1357 		return;
1358 	size = resource_size(uart_resource);
1359 
1360 	release_mem_region(port->mapbase, size);
1361 	iounmap(port->membase);
1362 	port->membase = NULL;
1363 }
1364 
msm_request_port(struct uart_port * port)1365 static int msm_request_port(struct uart_port *port)
1366 {
1367 	struct platform_device *pdev = to_platform_device(port->dev);
1368 	struct resource *uart_resource;
1369 	resource_size_t size;
1370 	int ret;
1371 
1372 	uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1373 	if (unlikely(!uart_resource))
1374 		return -ENXIO;
1375 
1376 	size = resource_size(uart_resource);
1377 
1378 	if (!request_mem_region(port->mapbase, size, "msm_serial"))
1379 		return -EBUSY;
1380 
1381 	port->membase = ioremap(port->mapbase, size);
1382 	if (!port->membase) {
1383 		ret = -EBUSY;
1384 		goto fail_release_port;
1385 	}
1386 
1387 	return 0;
1388 
1389 fail_release_port:
1390 	release_mem_region(port->mapbase, size);
1391 	return ret;
1392 }
1393 
msm_config_port(struct uart_port * port,int flags)1394 static void msm_config_port(struct uart_port *port, int flags)
1395 {
1396 	int ret;
1397 
1398 	if (flags & UART_CONFIG_TYPE) {
1399 		port->type = PORT_MSM;
1400 		ret = msm_request_port(port);
1401 		if (ret)
1402 			return;
1403 	}
1404 }
1405 
msm_verify_port(struct uart_port * port,struct serial_struct * ser)1406 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1407 {
1408 	if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1409 		return -EINVAL;
1410 	if (unlikely(port->irq != ser->irq))
1411 		return -EINVAL;
1412 	return 0;
1413 }
1414 
msm_power(struct uart_port * port,unsigned int state,unsigned int oldstate)1415 static void msm_power(struct uart_port *port, unsigned int state,
1416 		      unsigned int oldstate)
1417 {
1418 	struct msm_port *msm_port = to_msm_port(port);
1419 
1420 	switch (state) {
1421 	case 0:
1422 		clk_prepare_enable(msm_port->clk);
1423 		clk_prepare_enable(msm_port->pclk);
1424 		break;
1425 	case 3:
1426 		clk_disable_unprepare(msm_port->clk);
1427 		clk_disable_unprepare(msm_port->pclk);
1428 		break;
1429 	default:
1430 		pr_err("msm_serial: Unknown PM state %d\n", state);
1431 	}
1432 }
1433 
1434 #ifdef CONFIG_CONSOLE_POLL
msm_poll_get_char_single(struct uart_port * port)1435 static int msm_poll_get_char_single(struct uart_port *port)
1436 {
1437 	struct msm_port *msm_port = to_msm_port(port);
1438 	unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF;
1439 
1440 	if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY))
1441 		return NO_POLL_CHAR;
1442 
1443 	return msm_read(port, rf_reg) & 0xff;
1444 }
1445 
msm_poll_get_char_dm(struct uart_port * port)1446 static int msm_poll_get_char_dm(struct uart_port *port)
1447 {
1448 	int c;
1449 	static u32 slop;
1450 	static int count;
1451 	unsigned char *sp = (unsigned char *)&slop;
1452 
1453 	/* Check if a previous read had more than one char */
1454 	if (count) {
1455 		c = sp[sizeof(slop) - count];
1456 		count--;
1457 	/* Or if FIFO is empty */
1458 	} else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) {
1459 		/*
1460 		 * If RX packing buffer has less than a word, force stale to
1461 		 * push contents into RX FIFO
1462 		 */
1463 		count = msm_read(port, UARTDM_RXFS);
1464 		count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1465 		if (count) {
1466 			msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR);
1467 			slop = msm_read(port, UARTDM_RF);
1468 			c = sp[0];
1469 			count--;
1470 			msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR);
1471 			msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1472 			msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR);
1473 		} else {
1474 			c = NO_POLL_CHAR;
1475 		}
1476 	/* FIFO has a word */
1477 	} else {
1478 		slop = msm_read(port, UARTDM_RF);
1479 		c = sp[0];
1480 		count = sizeof(slop) - 1;
1481 	}
1482 
1483 	return c;
1484 }
1485 
msm_poll_get_char(struct uart_port * port)1486 static int msm_poll_get_char(struct uart_port *port)
1487 {
1488 	u32 imr;
1489 	int c;
1490 	struct msm_port *msm_port = to_msm_port(port);
1491 
1492 	/* Disable all interrupts */
1493 	imr = msm_read(port, MSM_UART_IMR);
1494 	msm_write(port, 0, MSM_UART_IMR);
1495 
1496 	if (msm_port->is_uartdm)
1497 		c = msm_poll_get_char_dm(port);
1498 	else
1499 		c = msm_poll_get_char_single(port);
1500 
1501 	/* Enable interrupts */
1502 	msm_write(port, imr, MSM_UART_IMR);
1503 
1504 	return c;
1505 }
1506 
msm_poll_put_char(struct uart_port * port,unsigned char c)1507 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1508 {
1509 	u32 imr;
1510 	struct msm_port *msm_port = to_msm_port(port);
1511 
1512 	/* Disable all interrupts */
1513 	imr = msm_read(port, MSM_UART_IMR);
1514 	msm_write(port, 0, MSM_UART_IMR);
1515 
1516 	if (msm_port->is_uartdm)
1517 		msm_reset_dm_count(port, 1);
1518 
1519 	/* Wait until FIFO is empty */
1520 	while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1521 		cpu_relax();
1522 
1523 	/* Write a character */
1524 	msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF);
1525 
1526 	/* Wait until FIFO is empty */
1527 	while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1528 		cpu_relax();
1529 
1530 	/* Enable interrupts */
1531 	msm_write(port, imr, MSM_UART_IMR);
1532 }
1533 #endif
1534 
1535 static const struct uart_ops msm_uart_pops = {
1536 	.tx_empty = msm_tx_empty,
1537 	.set_mctrl = msm_set_mctrl,
1538 	.get_mctrl = msm_get_mctrl,
1539 	.stop_tx = msm_stop_tx,
1540 	.start_tx = msm_start_tx,
1541 	.stop_rx = msm_stop_rx,
1542 	.enable_ms = msm_enable_ms,
1543 	.break_ctl = msm_break_ctl,
1544 	.startup = msm_startup,
1545 	.shutdown = msm_shutdown,
1546 	.set_termios = msm_set_termios,
1547 	.type = msm_type,
1548 	.release_port = msm_release_port,
1549 	.request_port = msm_request_port,
1550 	.config_port = msm_config_port,
1551 	.verify_port = msm_verify_port,
1552 	.pm = msm_power,
1553 #ifdef CONFIG_CONSOLE_POLL
1554 	.poll_get_char	= msm_poll_get_char,
1555 	.poll_put_char	= msm_poll_put_char,
1556 #endif
1557 };
1558 
1559 static struct msm_port msm_uart_ports[] = {
1560 	{
1561 		.uart = {
1562 			.iotype = UPIO_MEM,
1563 			.ops = &msm_uart_pops,
1564 			.flags = UPF_BOOT_AUTOCONF,
1565 			.fifosize = 64,
1566 			.line = 0,
1567 		},
1568 	},
1569 	{
1570 		.uart = {
1571 			.iotype = UPIO_MEM,
1572 			.ops = &msm_uart_pops,
1573 			.flags = UPF_BOOT_AUTOCONF,
1574 			.fifosize = 64,
1575 			.line = 1,
1576 		},
1577 	},
1578 	{
1579 		.uart = {
1580 			.iotype = UPIO_MEM,
1581 			.ops = &msm_uart_pops,
1582 			.flags = UPF_BOOT_AUTOCONF,
1583 			.fifosize = 64,
1584 			.line = 2,
1585 		},
1586 	},
1587 };
1588 
1589 #define MSM_UART_NR	ARRAY_SIZE(msm_uart_ports)
1590 
msm_get_port_from_line(unsigned int line)1591 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1592 {
1593 	return &msm_uart_ports[line].uart;
1594 }
1595 
1596 #ifdef CONFIG_SERIAL_MSM_CONSOLE
__msm_console_write(struct uart_port * port,const char * s,unsigned int count,bool is_uartdm)1597 static void __msm_console_write(struct uart_port *port, const char *s,
1598 				unsigned int count, bool is_uartdm)
1599 {
1600 	unsigned long flags;
1601 	int i;
1602 	int num_newlines = 0;
1603 	bool replaced = false;
1604 	void __iomem *tf;
1605 	int locked = 1;
1606 
1607 	if (is_uartdm)
1608 		tf = port->membase + UARTDM_TF;
1609 	else
1610 		tf = port->membase + MSM_UART_TF;
1611 
1612 	/* Account for newlines that will get a carriage return added */
1613 	for (i = 0; i < count; i++)
1614 		if (s[i] == '\n')
1615 			num_newlines++;
1616 	count += num_newlines;
1617 
1618 	local_irq_save(flags);
1619 
1620 	if (port->sysrq)
1621 		locked = 0;
1622 	else if (oops_in_progress)
1623 		locked = spin_trylock(&port->lock);
1624 	else
1625 		spin_lock(&port->lock);
1626 
1627 	if (is_uartdm)
1628 		msm_reset_dm_count(port, count);
1629 
1630 	i = 0;
1631 	while (i < count) {
1632 		int j;
1633 		unsigned int num_chars;
1634 		char buf[4] = { 0 };
1635 
1636 		if (is_uartdm)
1637 			num_chars = min(count - i, (unsigned int)sizeof(buf));
1638 		else
1639 			num_chars = 1;
1640 
1641 		for (j = 0; j < num_chars; j++) {
1642 			char c = *s;
1643 
1644 			if (c == '\n' && !replaced) {
1645 				buf[j] = '\r';
1646 				j++;
1647 				replaced = true;
1648 			}
1649 			if (j < num_chars) {
1650 				buf[j] = c;
1651 				s++;
1652 				replaced = false;
1653 			}
1654 		}
1655 
1656 		while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY))
1657 			cpu_relax();
1658 
1659 		iowrite32_rep(tf, buf, 1);
1660 		i += num_chars;
1661 	}
1662 
1663 	if (locked)
1664 		spin_unlock(&port->lock);
1665 
1666 	local_irq_restore(flags);
1667 }
1668 
msm_console_write(struct console * co,const char * s,unsigned int count)1669 static void msm_console_write(struct console *co, const char *s,
1670 			      unsigned int count)
1671 {
1672 	struct uart_port *port;
1673 	struct msm_port *msm_port;
1674 
1675 	BUG_ON(co->index < 0 || co->index >= MSM_UART_NR);
1676 
1677 	port = msm_get_port_from_line(co->index);
1678 	msm_port = to_msm_port(port);
1679 
1680 	__msm_console_write(port, s, count, msm_port->is_uartdm);
1681 }
1682 
msm_console_setup(struct console * co,char * options)1683 static int msm_console_setup(struct console *co, char *options)
1684 {
1685 	struct uart_port *port;
1686 	int baud = 115200;
1687 	int bits = 8;
1688 	int parity = 'n';
1689 	int flow = 'n';
1690 
1691 	if (unlikely(co->index >= MSM_UART_NR || co->index < 0))
1692 		return -ENXIO;
1693 
1694 	port = msm_get_port_from_line(co->index);
1695 
1696 	if (unlikely(!port->membase))
1697 		return -ENXIO;
1698 
1699 	msm_init_clock(port);
1700 
1701 	if (options)
1702 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1703 
1704 	pr_info("msm_serial: console setup on port #%d\n", port->line);
1705 
1706 	return uart_set_options(port, co, baud, parity, bits, flow);
1707 }
1708 
1709 static void
msm_serial_early_write(struct console * con,const char * s,unsigned n)1710 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1711 {
1712 	struct earlycon_device *dev = con->data;
1713 
1714 	__msm_console_write(&dev->port, s, n, false);
1715 }
1716 
1717 static int __init
msm_serial_early_console_setup(struct earlycon_device * device,const char * opt)1718 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1719 {
1720 	if (!device->port.membase)
1721 		return -ENODEV;
1722 
1723 	device->con->write = msm_serial_early_write;
1724 	return 0;
1725 }
1726 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1727 		    msm_serial_early_console_setup);
1728 
1729 static void
msm_serial_early_write_dm(struct console * con,const char * s,unsigned n)1730 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1731 {
1732 	struct earlycon_device *dev = con->data;
1733 
1734 	__msm_console_write(&dev->port, s, n, true);
1735 }
1736 
1737 static int __init
msm_serial_early_console_setup_dm(struct earlycon_device * device,const char * opt)1738 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1739 				  const char *opt)
1740 {
1741 	if (!device->port.membase)
1742 		return -ENODEV;
1743 
1744 	device->con->write = msm_serial_early_write_dm;
1745 	return 0;
1746 }
1747 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1748 		    msm_serial_early_console_setup_dm);
1749 
1750 static struct uart_driver msm_uart_driver;
1751 
1752 static struct console msm_console = {
1753 	.name = "ttyMSM",
1754 	.write = msm_console_write,
1755 	.device = uart_console_device,
1756 	.setup = msm_console_setup,
1757 	.flags = CON_PRINTBUFFER,
1758 	.index = -1,
1759 	.data = &msm_uart_driver,
1760 };
1761 
1762 #define MSM_CONSOLE	(&msm_console)
1763 
1764 #else
1765 #define MSM_CONSOLE	NULL
1766 #endif
1767 
1768 static struct uart_driver msm_uart_driver = {
1769 	.owner = THIS_MODULE,
1770 	.driver_name = "msm_serial",
1771 	.dev_name = "ttyMSM",
1772 	.nr = MSM_UART_NR,
1773 	.cons = MSM_CONSOLE,
1774 };
1775 
1776 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1777 
1778 static const struct of_device_id msm_uartdm_table[] = {
1779 	{ .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1780 	{ .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1781 	{ .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1782 	{ .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1783 	{ }
1784 };
1785 
msm_serial_probe(struct platform_device * pdev)1786 static int msm_serial_probe(struct platform_device *pdev)
1787 {
1788 	struct msm_port *msm_port;
1789 	struct resource *resource;
1790 	struct uart_port *port;
1791 	const struct of_device_id *id;
1792 	int irq, line;
1793 
1794 	if (pdev->dev.of_node)
1795 		line = of_alias_get_id(pdev->dev.of_node, "serial");
1796 	else
1797 		line = pdev->id;
1798 
1799 	if (line < 0)
1800 		line = atomic_inc_return(&msm_uart_next_id) - 1;
1801 
1802 	if (unlikely(line < 0 || line >= MSM_UART_NR))
1803 		return -ENXIO;
1804 
1805 	dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1806 
1807 	port = msm_get_port_from_line(line);
1808 	port->dev = &pdev->dev;
1809 	msm_port = to_msm_port(port);
1810 
1811 	id = of_match_device(msm_uartdm_table, &pdev->dev);
1812 	if (id)
1813 		msm_port->is_uartdm = (unsigned long)id->data;
1814 	else
1815 		msm_port->is_uartdm = 0;
1816 
1817 	msm_port->clk = devm_clk_get(&pdev->dev, "core");
1818 	if (IS_ERR(msm_port->clk))
1819 		return PTR_ERR(msm_port->clk);
1820 
1821 	if (msm_port->is_uartdm) {
1822 		msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1823 		if (IS_ERR(msm_port->pclk))
1824 			return PTR_ERR(msm_port->pclk);
1825 	}
1826 
1827 	port->uartclk = clk_get_rate(msm_port->clk);
1828 	dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1829 
1830 	resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1831 	if (unlikely(!resource))
1832 		return -ENXIO;
1833 	port->mapbase = resource->start;
1834 
1835 	irq = platform_get_irq(pdev, 0);
1836 	if (unlikely(irq < 0))
1837 		return -ENXIO;
1838 	port->irq = irq;
1839 	port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1840 
1841 	platform_set_drvdata(pdev, port);
1842 
1843 	return uart_add_one_port(&msm_uart_driver, port);
1844 }
1845 
msm_serial_remove(struct platform_device * pdev)1846 static int msm_serial_remove(struct platform_device *pdev)
1847 {
1848 	struct uart_port *port = platform_get_drvdata(pdev);
1849 
1850 	uart_remove_one_port(&msm_uart_driver, port);
1851 
1852 	return 0;
1853 }
1854 
1855 static const struct of_device_id msm_match_table[] = {
1856 	{ .compatible = "qcom,msm-uart" },
1857 	{ .compatible = "qcom,msm-uartdm" },
1858 	{}
1859 };
1860 MODULE_DEVICE_TABLE(of, msm_match_table);
1861 
msm_serial_suspend(struct device * dev)1862 static int __maybe_unused msm_serial_suspend(struct device *dev)
1863 {
1864 	struct msm_port *port = dev_get_drvdata(dev);
1865 
1866 	uart_suspend_port(&msm_uart_driver, &port->uart);
1867 
1868 	return 0;
1869 }
1870 
msm_serial_resume(struct device * dev)1871 static int __maybe_unused msm_serial_resume(struct device *dev)
1872 {
1873 	struct msm_port *port = dev_get_drvdata(dev);
1874 
1875 	uart_resume_port(&msm_uart_driver, &port->uart);
1876 
1877 	return 0;
1878 }
1879 
1880 static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1881 	SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1882 };
1883 
1884 static struct platform_driver msm_platform_driver = {
1885 	.remove = msm_serial_remove,
1886 	.probe = msm_serial_probe,
1887 	.driver = {
1888 		.name = "msm_serial",
1889 		.pm = &msm_serial_dev_pm_ops,
1890 		.of_match_table = msm_match_table,
1891 	},
1892 };
1893 
msm_serial_init(void)1894 static int __init msm_serial_init(void)
1895 {
1896 	int ret;
1897 
1898 	ret = uart_register_driver(&msm_uart_driver);
1899 	if (unlikely(ret))
1900 		return ret;
1901 
1902 	ret = platform_driver_register(&msm_platform_driver);
1903 	if (unlikely(ret))
1904 		uart_unregister_driver(&msm_uart_driver);
1905 
1906 	pr_info("msm_serial: driver initialized\n");
1907 
1908 	return ret;
1909 }
1910 
msm_serial_exit(void)1911 static void __exit msm_serial_exit(void)
1912 {
1913 	platform_driver_unregister(&msm_platform_driver);
1914 	uart_unregister_driver(&msm_uart_driver);
1915 }
1916 
1917 module_init(msm_serial_init);
1918 module_exit(msm_serial_exit);
1919 
1920 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1921 MODULE_DESCRIPTION("Driver for msm7x serial device");
1922 MODULE_LICENSE("GPL");
1923