xref: /openbmc/linux/include/uapi/drm/msm_drm.h (revision f1af066b)
1 /*
2  * Copyright (C) 2013 Red Hat
3  * Author: Rob Clark <robdclark@gmail.com>
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22  * SOFTWARE.
23  */
24 
25 #ifndef __MSM_DRM_H__
26 #define __MSM_DRM_H__
27 
28 #include "drm.h"
29 
30 #if defined(__cplusplus)
31 extern "C" {
32 #endif
33 
34 /* Please note that modifications to all structs defined here are
35  * subject to backwards-compatibility constraints:
36  *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
37  *     user/kernel compatibility
38  *  2) Keep fields aligned to their size
39  *  3) Because of how drm_ioctl() works, we can add new fields at
40  *     the end of an ioctl if some care is taken: drm_ioctl() will
41  *     zero out the new fields at the tail of the ioctl, so a zero
42  *     value should have a backwards compatible meaning.  And for
43  *     output params, userspace won't see the newly added output
44  *     fields.. so that has to be somehow ok.
45  */
46 
47 #define MSM_PIPE_NONE        0x00
48 #define MSM_PIPE_2D0         0x01
49 #define MSM_PIPE_2D1         0x02
50 #define MSM_PIPE_3D0         0x10
51 
52 /* The pipe-id just uses the lower bits, so can be OR'd with flags in
53  * the upper 16 bits (which could be extended further, if needed, maybe
54  * we extend/overload the pipe-id some day to deal with multiple rings,
55  * but even then I don't think we need the full lower 16 bits).
56  */
57 #define MSM_PIPE_ID_MASK     0xffff
58 #define MSM_PIPE_ID(x)       ((x) & MSM_PIPE_ID_MASK)
59 #define MSM_PIPE_FLAGS(x)    ((x) & ~MSM_PIPE_ID_MASK)
60 
61 /* timeouts are specified in clock-monotonic absolute times (to simplify
62  * restarting interrupted ioctls).  The following struct is logically the
63  * same as 'struct timespec' but 32/64b ABI safe.
64  */
65 struct drm_msm_timespec {
66 	__s64 tv_sec;          /* seconds */
67 	__s64 tv_nsec;         /* nanoseconds */
68 };
69 
70 /* Below "RO" indicates a read-only param, "WO" indicates write-only, and
71  * "RW" indicates a param that can be both read (GET_PARAM) and written
72  * (SET_PARAM)
73  */
74 #define MSM_PARAM_GPU_ID     0x01  /* RO */
75 #define MSM_PARAM_GMEM_SIZE  0x02  /* RO */
76 #define MSM_PARAM_CHIP_ID    0x03  /* RO */
77 #define MSM_PARAM_MAX_FREQ   0x04  /* RO */
78 #define MSM_PARAM_TIMESTAMP  0x05  /* RO */
79 #define MSM_PARAM_GMEM_BASE  0x06  /* RO */
80 #define MSM_PARAM_PRIORITIES 0x07  /* RO: The # of priority levels */
81 #define MSM_PARAM_PP_PGTABLE 0x08  /* RO: Deprecated, always returns zero */
82 #define MSM_PARAM_FAULTS     0x09  /* RO */
83 #define MSM_PARAM_SUSPENDS   0x0a  /* RO */
84 #define MSM_PARAM_SYSPROF    0x0b  /* WO: 1 preserves perfcntrs, 2 also disables suspend */
85 #define MSM_PARAM_COMM       0x0c  /* WO: override for task->comm */
86 #define MSM_PARAM_CMDLINE    0x0d  /* WO: override for task cmdline */
87 #define MSM_PARAM_VA_START   0x0e  /* RO: start of valid GPU iova range */
88 #define MSM_PARAM_VA_SIZE    0x0f  /* RO: size of valid GPU iova range (bytes) */
89 
90 /* For backwards compat.  The original support for preemption was based on
91  * a single ring per priority level so # of priority levels equals the #
92  * of rings.  With drm/scheduler providing additional levels of priority,
93  * the number of priorities is greater than the # of rings.  The param is
94  * renamed to better reflect this.
95  */
96 #define MSM_PARAM_NR_RINGS   MSM_PARAM_PRIORITIES
97 
98 struct drm_msm_param {
99 	__u32 pipe;           /* in, MSM_PIPE_x */
100 	__u32 param;          /* in, MSM_PARAM_x */
101 	__u64 value;          /* out (get_param) or in (set_param) */
102 	__u32 len;            /* zero for non-pointer params */
103 	__u32 pad;            /* must be zero */
104 };
105 
106 /*
107  * GEM buffers:
108  */
109 
110 #define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
111 #define MSM_BO_GPU_READONLY  0x00000002
112 #define MSM_BO_CACHE_MASK    0x000f0000
113 /* cache modes */
114 #define MSM_BO_CACHED        0x00010000
115 #define MSM_BO_WC            0x00020000
116 #define MSM_BO_UNCACHED      0x00040000 /* deprecated, use MSM_BO_WC */
117 #define MSM_BO_CACHED_COHERENT 0x080000
118 
119 #define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
120                               MSM_BO_GPU_READONLY | \
121                               MSM_BO_CACHE_MASK)
122 
123 struct drm_msm_gem_new {
124 	__u64 size;           /* in */
125 	__u32 flags;          /* in, mask of MSM_BO_x */
126 	__u32 handle;         /* out */
127 };
128 
129 /* Get or set GEM buffer info.  The requested value can be passed
130  * directly in 'value', or for data larger than 64b 'value' is a
131  * pointer to userspace buffer, with 'len' specifying the number of
132  * bytes copied into that buffer.  For info returned by pointer,
133  * calling the GEM_INFO ioctl with null 'value' will return the
134  * required buffer size in 'len'
135  */
136 #define MSM_INFO_GET_OFFSET	0x00   /* get mmap() offset, returned by value */
137 #define MSM_INFO_GET_IOVA	0x01   /* get iova, returned by value */
138 #define MSM_INFO_SET_NAME	0x02   /* set the debug name (by pointer) */
139 #define MSM_INFO_GET_NAME	0x03   /* get debug name, returned by pointer */
140 #define MSM_INFO_SET_IOVA	0x04   /* set the iova, passed by value */
141 #define MSM_INFO_GET_FLAGS	0x05   /* get the MSM_BO_x flags */
142 
143 struct drm_msm_gem_info {
144 	__u32 handle;         /* in */
145 	__u32 info;           /* in - one of MSM_INFO_* */
146 	__u64 value;          /* in or out */
147 	__u32 len;            /* in or out */
148 	__u32 pad;
149 };
150 
151 #define MSM_PREP_READ        0x01
152 #define MSM_PREP_WRITE       0x02
153 #define MSM_PREP_NOSYNC      0x04
154 #define MSM_PREP_BOOST       0x08
155 
156 #define MSM_PREP_FLAGS       (MSM_PREP_READ | \
157 			      MSM_PREP_WRITE | \
158 			      MSM_PREP_NOSYNC | \
159 			      MSM_PREP_BOOST | \
160 			      0)
161 
162 struct drm_msm_gem_cpu_prep {
163 	__u32 handle;         /* in */
164 	__u32 op;             /* in, mask of MSM_PREP_x */
165 	struct drm_msm_timespec timeout;   /* in */
166 };
167 
168 struct drm_msm_gem_cpu_fini {
169 	__u32 handle;         /* in */
170 };
171 
172 /*
173  * Cmdstream Submission:
174  */
175 
176 /* The value written into the cmdstream is logically:
177  *
178  *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
179  *
180  * When we have GPU's w/ >32bit ptrs, it should be possible to deal
181  * with this by emit'ing two reloc entries with appropriate shift
182  * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
183  *
184  * NOTE that reloc's must be sorted by order of increasing submit_offset,
185  * otherwise EINVAL.
186  */
187 struct drm_msm_gem_submit_reloc {
188 	__u32 submit_offset;  /* in, offset from submit_bo */
189 #ifdef __cplusplus
190 	__u32 _or;            /* in, value OR'd with result */
191 #else
192 	__u32 or;             /* in, value OR'd with result */
193 #endif
194 	__s32 shift;          /* in, amount of left shift (can be negative) */
195 	__u32 reloc_idx;      /* in, index of reloc_bo buffer */
196 	__u64 reloc_offset;   /* in, offset from start of reloc_bo */
197 };
198 
199 /* submit-types:
200  *   BUF - this cmd buffer is executed normally.
201  *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
202  *      processed normally, but the kernel does not setup an IB to
203  *      this buffer in the first-level ringbuffer
204  *   CTX_RESTORE_BUF - only executed if there has been a GPU context
205  *      switch since the last SUBMIT ioctl
206  */
207 #define MSM_SUBMIT_CMD_BUF             0x0001
208 #define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
209 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
210 struct drm_msm_gem_submit_cmd {
211 	__u32 type;           /* in, one of MSM_SUBMIT_CMD_x */
212 	__u32 submit_idx;     /* in, index of submit_bo cmdstream buffer */
213 	__u32 submit_offset;  /* in, offset into submit_bo */
214 	__u32 size;           /* in, cmdstream size */
215 	__u32 pad;
216 	__u32 nr_relocs;      /* in, number of submit_reloc's */
217 	__u64 relocs;         /* in, ptr to array of submit_reloc's */
218 };
219 
220 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
221  * cmdstream buffer(s) themselves or reloc entries) has one (and only
222  * one) entry in the submit->bos[] table.
223  *
224  * As a optimization, the current buffer (gpu virtual address) can be
225  * passed back through the 'presumed' field.  If on a subsequent reloc,
226  * userspace passes back a 'presumed' address that is still valid,
227  * then patching the cmdstream for this entry is skipped.  This can
228  * avoid kernel needing to map/access the cmdstream bo in the common
229  * case.
230  */
231 #define MSM_SUBMIT_BO_READ             0x0001
232 #define MSM_SUBMIT_BO_WRITE            0x0002
233 #define MSM_SUBMIT_BO_DUMP             0x0004
234 #define MSM_SUBMIT_BO_NO_IMPLICIT      0x0008
235 
236 #define MSM_SUBMIT_BO_FLAGS            (MSM_SUBMIT_BO_READ | \
237 					MSM_SUBMIT_BO_WRITE | \
238 					MSM_SUBMIT_BO_DUMP | \
239 					MSM_SUBMIT_BO_NO_IMPLICIT)
240 
241 struct drm_msm_gem_submit_bo {
242 	__u32 flags;          /* in, mask of MSM_SUBMIT_BO_x */
243 	__u32 handle;         /* in, GEM handle */
244 	__u64 presumed;       /* in/out, presumed buffer address */
245 };
246 
247 /* Valid submit ioctl flags: */
248 #define MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */
249 #define MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */
250 #define MSM_SUBMIT_FENCE_FD_OUT  0x20000000 /* enable output fence_fd */
251 #define MSM_SUBMIT_SUDO          0x10000000 /* run submitted cmds from RB */
252 #define MSM_SUBMIT_SYNCOBJ_IN    0x08000000 /* enable input syncobj */
253 #define MSM_SUBMIT_SYNCOBJ_OUT   0x04000000 /* enable output syncobj */
254 #define MSM_SUBMIT_FENCE_SN_IN   0x02000000 /* userspace passes in seqno fence */
255 #define MSM_SUBMIT_FLAGS                ( \
256 		MSM_SUBMIT_NO_IMPLICIT   | \
257 		MSM_SUBMIT_FENCE_FD_IN   | \
258 		MSM_SUBMIT_FENCE_FD_OUT  | \
259 		MSM_SUBMIT_SUDO          | \
260 		MSM_SUBMIT_SYNCOBJ_IN    | \
261 		MSM_SUBMIT_SYNCOBJ_OUT   | \
262 		MSM_SUBMIT_FENCE_SN_IN   | \
263 		0)
264 
265 #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
266 #define MSM_SUBMIT_SYNCOBJ_FLAGS        ( \
267 		MSM_SUBMIT_SYNCOBJ_RESET | \
268 		0)
269 
270 struct drm_msm_gem_submit_syncobj {
271 	__u32 handle;     /* in, syncobj handle. */
272 	__u32 flags;      /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
273 	__u64 point;      /* in, timepoint for timeline syncobjs. */
274 };
275 
276 /* Each cmdstream submit consists of a table of buffers involved, and
277  * one or more cmdstream buffers.  This allows for conditional execution
278  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
279  */
280 struct drm_msm_gem_submit {
281 	__u32 flags;          /* MSM_PIPE_x | MSM_SUBMIT_x */
282 	__u32 fence;          /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
283 	__u32 nr_bos;         /* in, number of submit_bo's */
284 	__u32 nr_cmds;        /* in, number of submit_cmd's */
285 	__u64 bos;            /* in, ptr to array of submit_bo's */
286 	__u64 cmds;           /* in, ptr to array of submit_cmd's */
287 	__s32 fence_fd;       /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
288 	__u32 queueid;        /* in, submitqueue id */
289 	__u64 in_syncobjs;    /* in, ptr to array of drm_msm_gem_submit_syncobj */
290 	__u64 out_syncobjs;   /* in, ptr to array of drm_msm_gem_submit_syncobj */
291 	__u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
292 	__u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
293 	__u32 syncobj_stride; /* in, stride of syncobj arrays. */
294 	__u32 pad;            /*in, reserved for future use, always 0. */
295 
296 };
297 
298 #define MSM_WAIT_FENCE_BOOST	0x00000001
299 #define MSM_WAIT_FENCE_FLAGS	( \
300 		MSM_WAIT_FENCE_BOOST | \
301 		0)
302 
303 /* The normal way to synchronize with the GPU is just to CPU_PREP on
304  * a buffer if you need to access it from the CPU (other cmdstream
305  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
306  * handle the required synchronization under the hood).  This ioctl
307  * mainly just exists as a way to implement the gallium pipe_fence
308  * APIs without requiring a dummy bo to synchronize on.
309  */
310 struct drm_msm_wait_fence {
311 	__u32 fence;          /* in */
312 	__u32 flags;          /* in, bitmask of MSM_WAIT_FENCE_x */
313 	struct drm_msm_timespec timeout;   /* in */
314 	__u32 queueid;         /* in, submitqueue id */
315 };
316 
317 /* madvise provides a way to tell the kernel in case a buffers contents
318  * can be discarded under memory pressure, which is useful for userspace
319  * bo cache where we want to optimistically hold on to buffer allocate
320  * and potential mmap, but allow the pages to be discarded under memory
321  * pressure.
322  *
323  * Typical usage would involve madvise(DONTNEED) when buffer enters BO
324  * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
325  * In the WILLNEED case, 'retained' indicates to userspace whether the
326  * backing pages still exist.
327  */
328 #define MSM_MADV_WILLNEED 0       /* backing pages are needed, status returned in 'retained' */
329 #define MSM_MADV_DONTNEED 1       /* backing pages not needed */
330 #define __MSM_MADV_PURGED 2       /* internal state */
331 
332 struct drm_msm_gem_madvise {
333 	__u32 handle;         /* in, GEM handle */
334 	__u32 madv;           /* in, MSM_MADV_x */
335 	__u32 retained;       /* out, whether backing store still exists */
336 };
337 
338 /*
339  * Draw queues allow the user to set specific submission parameter. Command
340  * submissions specify a specific submitqueue to use.  ID 0 is reserved for
341  * backwards compatibility as a "default" submitqueue
342  */
343 
344 #define MSM_SUBMITQUEUE_FLAGS (0)
345 
346 /*
347  * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
348  * a lower numeric value is higher priority.
349  */
350 struct drm_msm_submitqueue {
351 	__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
352 	__u32 prio;    /* in, Priority level */
353 	__u32 id;      /* out, identifier */
354 };
355 
356 #define MSM_SUBMITQUEUE_PARAM_FAULTS   0
357 
358 struct drm_msm_submitqueue_query {
359 	__u64 data;
360 	__u32 id;
361 	__u32 param;
362 	__u32 len;
363 	__u32 pad;
364 };
365 
366 #define DRM_MSM_GET_PARAM              0x00
367 #define DRM_MSM_SET_PARAM              0x01
368 #define DRM_MSM_GEM_NEW                0x02
369 #define DRM_MSM_GEM_INFO               0x03
370 #define DRM_MSM_GEM_CPU_PREP           0x04
371 #define DRM_MSM_GEM_CPU_FINI           0x05
372 #define DRM_MSM_GEM_SUBMIT             0x06
373 #define DRM_MSM_WAIT_FENCE             0x07
374 #define DRM_MSM_GEM_MADVISE            0x08
375 /* placeholder:
376 #define DRM_MSM_GEM_SVM_NEW            0x09
377  */
378 #define DRM_MSM_SUBMITQUEUE_NEW        0x0A
379 #define DRM_MSM_SUBMITQUEUE_CLOSE      0x0B
380 #define DRM_MSM_SUBMITQUEUE_QUERY      0x0C
381 
382 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
383 #define DRM_IOCTL_MSM_SET_PARAM        DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
384 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
385 #define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
386 #define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
387 #define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
388 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
389 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
390 #define DRM_IOCTL_MSM_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
391 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW    DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
392 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
393 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
394 
395 #if defined(__cplusplus)
396 }
397 #endif
398 
399 #endif /* __MSM_DRM_H__ */
400