1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of.h>
16 #include <linux/of_gpio.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pm_wakeirq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/reset.h>
27
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include "cqhci.h"
37
38 #define MAX_BD_NUM 1024
39 #define MSDC_NR_CLOCKS 3
40
41 /*--------------------------------------------------------------------------*/
42 /* Common Definition */
43 /*--------------------------------------------------------------------------*/
44 #define MSDC_BUS_1BITS 0x0
45 #define MSDC_BUS_4BITS 0x1
46 #define MSDC_BUS_8BITS 0x2
47
48 #define MSDC_BURST_64B 0x6
49
50 /*--------------------------------------------------------------------------*/
51 /* Register Offset */
52 /*--------------------------------------------------------------------------*/
53 #define MSDC_CFG 0x0
54 #define MSDC_IOCON 0x04
55 #define MSDC_PS 0x08
56 #define MSDC_INT 0x0c
57 #define MSDC_INTEN 0x10
58 #define MSDC_FIFOCS 0x14
59 #define SDC_CFG 0x30
60 #define SDC_CMD 0x34
61 #define SDC_ARG 0x38
62 #define SDC_STS 0x3c
63 #define SDC_RESP0 0x40
64 #define SDC_RESP1 0x44
65 #define SDC_RESP2 0x48
66 #define SDC_RESP3 0x4c
67 #define SDC_BLK_NUM 0x50
68 #define SDC_ADV_CFG0 0x64
69 #define EMMC_IOCON 0x7c
70 #define SDC_ACMD_RESP 0x80
71 #define DMA_SA_H4BIT 0x8c
72 #define MSDC_DMA_SA 0x90
73 #define MSDC_DMA_CTRL 0x98
74 #define MSDC_DMA_CFG 0x9c
75 #define MSDC_PATCH_BIT 0xb0
76 #define MSDC_PATCH_BIT1 0xb4
77 #define MSDC_PATCH_BIT2 0xb8
78 #define MSDC_PAD_TUNE 0xec
79 #define MSDC_PAD_TUNE0 0xf0
80 #define PAD_DS_TUNE 0x188
81 #define PAD_CMD_TUNE 0x18c
82 #define EMMC51_CFG0 0x204
83 #define EMMC50_CFG0 0x208
84 #define EMMC50_CFG1 0x20c
85 #define EMMC50_CFG3 0x220
86 #define SDC_FIFO_CFG 0x228
87 #define CQHCI_SETTING 0x7fc
88
89 /*--------------------------------------------------------------------------*/
90 /* Top Pad Register Offset */
91 /*--------------------------------------------------------------------------*/
92 #define EMMC_TOP_CONTROL 0x00
93 #define EMMC_TOP_CMD 0x04
94 #define EMMC50_PAD_DS_TUNE 0x0c
95
96 /*--------------------------------------------------------------------------*/
97 /* Register Mask */
98 /*--------------------------------------------------------------------------*/
99
100 /* MSDC_CFG mask */
101 #define MSDC_CFG_MODE BIT(0) /* RW */
102 #define MSDC_CFG_CKPDN BIT(1) /* RW */
103 #define MSDC_CFG_RST BIT(2) /* RW */
104 #define MSDC_CFG_PIO BIT(3) /* RW */
105 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */
106 #define MSDC_CFG_BV18SDT BIT(5) /* RW */
107 #define MSDC_CFG_BV18PSS BIT(6) /* R */
108 #define MSDC_CFG_CKSTB BIT(7) /* R */
109 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */
110 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */
111 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */
112 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */
113 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */
114 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */
115
116 /* MSDC_IOCON mask */
117 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */
118 #define MSDC_IOCON_RSPL BIT(1) /* RW */
119 #define MSDC_IOCON_DSPL BIT(2) /* RW */
120 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */
121 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */
122 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */
123 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */
124 #define MSDC_IOCON_D0SPL BIT(16) /* RW */
125 #define MSDC_IOCON_D1SPL BIT(17) /* RW */
126 #define MSDC_IOCON_D2SPL BIT(18) /* RW */
127 #define MSDC_IOCON_D3SPL BIT(19) /* RW */
128 #define MSDC_IOCON_D4SPL BIT(20) /* RW */
129 #define MSDC_IOCON_D5SPL BIT(21) /* RW */
130 #define MSDC_IOCON_D6SPL BIT(22) /* RW */
131 #define MSDC_IOCON_D7SPL BIT(23) /* RW */
132 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */
133
134 /* MSDC_PS mask */
135 #define MSDC_PS_CDEN BIT(0) /* RW */
136 #define MSDC_PS_CDSTS BIT(1) /* R */
137 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */
138 #define MSDC_PS_DAT GENMASK(23, 16) /* R */
139 #define MSDC_PS_DATA1 BIT(17) /* R */
140 #define MSDC_PS_CMD BIT(24) /* R */
141 #define MSDC_PS_WP BIT(31) /* R */
142
143 /* MSDC_INT mask */
144 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */
145 #define MSDC_INT_CDSC BIT(1) /* W1C */
146 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */
147 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */
148 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */
149 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */
150 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */
151 #define MSDC_INT_CMDRDY BIT(8) /* W1C */
152 #define MSDC_INT_CMDTMO BIT(9) /* W1C */
153 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */
154 #define MSDC_INT_CSTA BIT(11) /* R */
155 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */
156 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */
157 #define MSDC_INT_DATTMO BIT(14) /* W1C */
158 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */
159 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */
160 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */
161 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */
162 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */
163 #define MSDC_INT_CMDQ BIT(28) /* W1C */
164
165 /* MSDC_INTEN mask */
166 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */
167 #define MSDC_INTEN_CDSC BIT(1) /* RW */
168 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */
169 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */
170 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */
171 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */
172 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */
173 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */
174 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */
175 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */
176 #define MSDC_INTEN_CSTA BIT(11) /* RW */
177 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */
178 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */
179 #define MSDC_INTEN_DATTMO BIT(14) /* RW */
180 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */
181 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */
182 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */
183 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
184 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */
185
186 /* MSDC_FIFOCS mask */
187 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */
188 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */
189 #define MSDC_FIFOCS_CLR BIT(31) /* RW */
190
191 /* SDC_CFG mask */
192 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */
193 #define SDC_CFG_INSWKUP BIT(1) /* RW */
194 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */
195 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */
196 #define SDC_CFG_SDIO BIT(19) /* RW */
197 #define SDC_CFG_SDIOIDE BIT(20) /* RW */
198 #define SDC_CFG_INTATGAP BIT(21) /* RW */
199 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */
200
201 /* SDC_STS mask */
202 #define SDC_STS_SDCBUSY BIT(0) /* RW */
203 #define SDC_STS_CMDBUSY BIT(1) /* RW */
204 #define SDC_STS_SWR_COMPL BIT(31) /* RW */
205
206 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
207 /* SDC_ADV_CFG0 mask */
208 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */
209
210 /* DMA_SA_H4BIT mask */
211 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */
212
213 /* MSDC_DMA_CTRL mask */
214 #define MSDC_DMA_CTRL_START BIT(0) /* W */
215 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */
216 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */
217 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */
218 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */
219 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */
220
221 /* MSDC_DMA_CFG mask */
222 #define MSDC_DMA_CFG_STS BIT(0) /* R */
223 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */
224 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */
225 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */
226 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */
227
228 /* MSDC_PATCH_BIT mask */
229 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */
230 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
231 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)
232 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */
233 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */
234 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */
235 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */
236 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */
237 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */
238 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */
239 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */
240 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */
241
242 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */
243 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */
244 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */
245
246 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */
247 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */
248 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
249 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
250 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
251 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
252
253 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
254 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */
255 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */
256 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */
257 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */
258 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */
259 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */
260 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */
261
262 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */
263 #define PAD_DS_TUNE_DLY2_SEL BIT(1) /* RW */
264 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */
265 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */
266 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */
267
268 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */
269
270 /* EMMC51_CFG0 mask */
271 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */
272
273 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */
274 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */
275 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */
276 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */
277
278 /* EMMC50_CFG1 mask */
279 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
280
281 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
282
283 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
284 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
285
286 /* CQHCI_SETTING */
287 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */
288 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */
289
290 /* EMMC_TOP_CONTROL mask */
291 #define PAD_RXDLY_SEL BIT(0) /* RW */
292 #define DELAY_EN BIT(1) /* RW */
293 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */
294 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */
295 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */
296 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */
297 #define DATA_K_VALUE_SEL BIT(14) /* RW */
298 #define SDC_RX_ENH_EN BIT(15) /* TW */
299
300 /* EMMC_TOP_CMD mask */
301 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */
302 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */
303 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */
304 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */
305 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */
306
307 /* EMMC50_PAD_DS_TUNE mask */
308 #define PAD_DS_DLY_SEL BIT(16) /* RW */
309 #define PAD_DS_DLY2_SEL BIT(15) /* RW */
310 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */
311 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */
312
313 #define REQ_CMD_EIO BIT(0)
314 #define REQ_CMD_TMO BIT(1)
315 #define REQ_DAT_ERR BIT(2)
316 #define REQ_STOP_EIO BIT(3)
317 #define REQ_STOP_TMO BIT(4)
318 #define REQ_CMD_BUSY BIT(5)
319
320 #define MSDC_PREPARE_FLAG BIT(0)
321 #define MSDC_ASYNC_FLAG BIT(1)
322 #define MSDC_MMAP_FLAG BIT(2)
323
324 #define MTK_MMC_AUTOSUSPEND_DELAY 50
325 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
326 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
327
328 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
329
330 #define PAD_DELAY_MAX 32 /* PAD delay cells */
331 /*--------------------------------------------------------------------------*/
332 /* Descriptor Structure */
333 /*--------------------------------------------------------------------------*/
334 struct mt_gpdma_desc {
335 u32 gpd_info;
336 #define GPDMA_DESC_HWO BIT(0)
337 #define GPDMA_DESC_BDP BIT(1)
338 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8)
339 #define GPDMA_DESC_INT BIT(16)
340 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24)
341 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28)
342 u32 next;
343 u32 ptr;
344 u32 gpd_data_len;
345 #define GPDMA_DESC_BUFLEN GENMASK(15, 0)
346 #define GPDMA_DESC_EXTLEN GENMASK(23, 16)
347 u32 arg;
348 u32 blknum;
349 u32 cmd;
350 };
351
352 struct mt_bdma_desc {
353 u32 bd_info;
354 #define BDMA_DESC_EOL BIT(0)
355 #define BDMA_DESC_CHECKSUM GENMASK(15, 8)
356 #define BDMA_DESC_BLKPAD BIT(17)
357 #define BDMA_DESC_DWPAD BIT(18)
358 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24)
359 #define BDMA_DESC_PTR_H4 GENMASK(31, 28)
360 u32 next;
361 u32 ptr;
362 u32 bd_data_len;
363 #define BDMA_DESC_BUFLEN GENMASK(15, 0)
364 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0)
365 };
366
367 struct msdc_dma {
368 struct scatterlist *sg; /* I/O scatter list */
369 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
370 struct mt_bdma_desc *bd; /* pointer to bd array */
371 dma_addr_t gpd_addr; /* the physical address of gpd array */
372 dma_addr_t bd_addr; /* the physical address of bd array */
373 };
374
375 struct msdc_save_para {
376 u32 msdc_cfg;
377 u32 iocon;
378 u32 sdc_cfg;
379 u32 pad_tune;
380 u32 patch_bit0;
381 u32 patch_bit1;
382 u32 patch_bit2;
383 u32 pad_ds_tune;
384 u32 pad_cmd_tune;
385 u32 emmc50_cfg0;
386 u32 emmc50_cfg3;
387 u32 sdc_fifo_cfg;
388 u32 emmc_top_control;
389 u32 emmc_top_cmd;
390 u32 emmc50_pad_ds_tune;
391 };
392
393 struct mtk_mmc_compatible {
394 u8 clk_div_bits;
395 bool recheck_sdio_irq;
396 bool hs400_tune; /* only used for MT8173 */
397 u32 pad_tune_reg;
398 bool async_fifo;
399 bool data_tune;
400 bool busy_check;
401 bool stop_clk_fix;
402 bool enhance_rx;
403 bool support_64g;
404 bool use_internal_cd;
405 };
406
407 struct msdc_tune_para {
408 u32 iocon;
409 u32 pad_tune;
410 u32 pad_cmd_tune;
411 u32 emmc_top_control;
412 u32 emmc_top_cmd;
413 };
414
415 struct msdc_delay_phase {
416 u8 maxlen;
417 u8 start;
418 u8 final_phase;
419 };
420
421 struct msdc_host {
422 struct device *dev;
423 const struct mtk_mmc_compatible *dev_comp;
424 int cmd_rsp;
425
426 spinlock_t lock;
427 struct mmc_request *mrq;
428 struct mmc_command *cmd;
429 struct mmc_data *data;
430 int error;
431
432 void __iomem *base; /* host base address */
433 void __iomem *top_base; /* host top register base address */
434
435 struct msdc_dma dma; /* dma channel */
436 u64 dma_mask;
437
438 u32 timeout_ns; /* data timeout ns */
439 u32 timeout_clks; /* data timeout clks */
440
441 struct pinctrl *pinctrl;
442 struct pinctrl_state *pins_default;
443 struct pinctrl_state *pins_uhs;
444 struct pinctrl_state *pins_eint;
445 struct delayed_work req_timeout;
446 int irq; /* host interrupt */
447 int eint_irq; /* interrupt from sdio device for waking up system */
448 struct reset_control *reset;
449
450 struct clk *src_clk; /* msdc source clock */
451 struct clk *h_clk; /* msdc h_clk */
452 struct clk *bus_clk; /* bus clock which used to access register */
453 struct clk *src_clk_cg; /* msdc source clock control gate */
454 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
455 struct clk *crypto_clk; /* msdc crypto clock control gate */
456 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
457 u32 mclk; /* mmc subsystem clock frequency */
458 u32 src_clk_freq; /* source clock frequency */
459 unsigned char timing;
460 bool vqmmc_enabled;
461 u32 latch_ck;
462 u32 hs400_ds_delay;
463 u32 hs400_ds_dly3;
464 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
465 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
466 bool hs400_cmd_resp_sel_rising;
467 /* cmd response sample selection for HS400 */
468 bool hs400_mode; /* current eMMC will run at hs400 mode */
469 bool hs400_tuning; /* hs400 mode online tuning */
470 bool internal_cd; /* Use internal card-detect logic */
471 bool cqhci; /* support eMMC hw cmdq */
472 struct msdc_save_para save_para; /* used when gate HCLK */
473 struct msdc_tune_para def_tune_para; /* default tune setting */
474 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
475 struct cqhci_host *cq_host;
476 u32 cq_ssc1_time;
477 };
478
479 static const struct mtk_mmc_compatible mt2701_compat = {
480 .clk_div_bits = 12,
481 .recheck_sdio_irq = true,
482 .hs400_tune = false,
483 .pad_tune_reg = MSDC_PAD_TUNE0,
484 .async_fifo = true,
485 .data_tune = true,
486 .busy_check = false,
487 .stop_clk_fix = false,
488 .enhance_rx = false,
489 .support_64g = false,
490 };
491
492 static const struct mtk_mmc_compatible mt2712_compat = {
493 .clk_div_bits = 12,
494 .recheck_sdio_irq = false,
495 .hs400_tune = false,
496 .pad_tune_reg = MSDC_PAD_TUNE0,
497 .async_fifo = true,
498 .data_tune = true,
499 .busy_check = true,
500 .stop_clk_fix = true,
501 .enhance_rx = true,
502 .support_64g = true,
503 };
504
505 static const struct mtk_mmc_compatible mt6779_compat = {
506 .clk_div_bits = 12,
507 .recheck_sdio_irq = false,
508 .hs400_tune = false,
509 .pad_tune_reg = MSDC_PAD_TUNE0,
510 .async_fifo = true,
511 .data_tune = true,
512 .busy_check = true,
513 .stop_clk_fix = true,
514 .enhance_rx = true,
515 .support_64g = true,
516 };
517
518 static const struct mtk_mmc_compatible mt6795_compat = {
519 .clk_div_bits = 8,
520 .recheck_sdio_irq = false,
521 .hs400_tune = true,
522 .pad_tune_reg = MSDC_PAD_TUNE,
523 .async_fifo = false,
524 .data_tune = false,
525 .busy_check = false,
526 .stop_clk_fix = false,
527 .enhance_rx = false,
528 .support_64g = false,
529 };
530
531 static const struct mtk_mmc_compatible mt7620_compat = {
532 .clk_div_bits = 8,
533 .recheck_sdio_irq = true,
534 .hs400_tune = false,
535 .pad_tune_reg = MSDC_PAD_TUNE,
536 .async_fifo = false,
537 .data_tune = false,
538 .busy_check = false,
539 .stop_clk_fix = false,
540 .enhance_rx = false,
541 .use_internal_cd = true,
542 };
543
544 static const struct mtk_mmc_compatible mt7622_compat = {
545 .clk_div_bits = 12,
546 .recheck_sdio_irq = true,
547 .hs400_tune = false,
548 .pad_tune_reg = MSDC_PAD_TUNE0,
549 .async_fifo = true,
550 .data_tune = true,
551 .busy_check = true,
552 .stop_clk_fix = true,
553 .enhance_rx = true,
554 .support_64g = false,
555 };
556
557 static const struct mtk_mmc_compatible mt7986_compat = {
558 .clk_div_bits = 12,
559 .recheck_sdio_irq = true,
560 .hs400_tune = false,
561 .pad_tune_reg = MSDC_PAD_TUNE0,
562 .async_fifo = true,
563 .data_tune = true,
564 .busy_check = true,
565 .stop_clk_fix = true,
566 .enhance_rx = true,
567 .support_64g = true,
568 };
569
570 static const struct mtk_mmc_compatible mt8135_compat = {
571 .clk_div_bits = 8,
572 .recheck_sdio_irq = true,
573 .hs400_tune = false,
574 .pad_tune_reg = MSDC_PAD_TUNE,
575 .async_fifo = false,
576 .data_tune = false,
577 .busy_check = false,
578 .stop_clk_fix = false,
579 .enhance_rx = false,
580 .support_64g = false,
581 };
582
583 static const struct mtk_mmc_compatible mt8173_compat = {
584 .clk_div_bits = 8,
585 .recheck_sdio_irq = true,
586 .hs400_tune = true,
587 .pad_tune_reg = MSDC_PAD_TUNE,
588 .async_fifo = false,
589 .data_tune = false,
590 .busy_check = false,
591 .stop_clk_fix = false,
592 .enhance_rx = false,
593 .support_64g = false,
594 };
595
596 static const struct mtk_mmc_compatible mt8183_compat = {
597 .clk_div_bits = 12,
598 .recheck_sdio_irq = false,
599 .hs400_tune = false,
600 .pad_tune_reg = MSDC_PAD_TUNE0,
601 .async_fifo = true,
602 .data_tune = true,
603 .busy_check = true,
604 .stop_clk_fix = true,
605 .enhance_rx = true,
606 .support_64g = true,
607 };
608
609 static const struct mtk_mmc_compatible mt8516_compat = {
610 .clk_div_bits = 12,
611 .recheck_sdio_irq = true,
612 .hs400_tune = false,
613 .pad_tune_reg = MSDC_PAD_TUNE0,
614 .async_fifo = true,
615 .data_tune = true,
616 .busy_check = true,
617 .stop_clk_fix = true,
618 };
619
620 static const struct of_device_id msdc_of_ids[] = {
621 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
622 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
623 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
624 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
625 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
626 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
627 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
628 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
629 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
630 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
631 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
632
633 {}
634 };
635 MODULE_DEVICE_TABLE(of, msdc_of_ids);
636
sdr_set_bits(void __iomem * reg,u32 bs)637 static void sdr_set_bits(void __iomem *reg, u32 bs)
638 {
639 u32 val = readl(reg);
640
641 val |= bs;
642 writel(val, reg);
643 }
644
sdr_clr_bits(void __iomem * reg,u32 bs)645 static void sdr_clr_bits(void __iomem *reg, u32 bs)
646 {
647 u32 val = readl(reg);
648
649 val &= ~bs;
650 writel(val, reg);
651 }
652
sdr_set_field(void __iomem * reg,u32 field,u32 val)653 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
654 {
655 unsigned int tv = readl(reg);
656
657 tv &= ~field;
658 tv |= ((val) << (ffs((unsigned int)field) - 1));
659 writel(tv, reg);
660 }
661
sdr_get_field(void __iomem * reg,u32 field,u32 * val)662 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
663 {
664 unsigned int tv = readl(reg);
665
666 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
667 }
668
msdc_reset_hw(struct msdc_host * host)669 static void msdc_reset_hw(struct msdc_host *host)
670 {
671 u32 val;
672
673 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
674 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
675
676 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
677 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
678 !(val & MSDC_FIFOCS_CLR), 0, 0);
679
680 val = readl(host->base + MSDC_INT);
681 writel(val, host->base + MSDC_INT);
682 }
683
684 static void msdc_cmd_next(struct msdc_host *host,
685 struct mmc_request *mrq, struct mmc_command *cmd);
686 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
687
688 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
689 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
690 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
691 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
692 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
693 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
694
msdc_dma_calcs(u8 * buf,u32 len)695 static u8 msdc_dma_calcs(u8 *buf, u32 len)
696 {
697 u32 i, sum = 0;
698
699 for (i = 0; i < len; i++)
700 sum += buf[i];
701 return 0xff - (u8) sum;
702 }
703
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)704 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
705 struct mmc_data *data)
706 {
707 unsigned int j, dma_len;
708 dma_addr_t dma_address;
709 u32 dma_ctrl;
710 struct scatterlist *sg;
711 struct mt_gpdma_desc *gpd;
712 struct mt_bdma_desc *bd;
713
714 sg = data->sg;
715
716 gpd = dma->gpd;
717 bd = dma->bd;
718
719 /* modify gpd */
720 gpd->gpd_info |= GPDMA_DESC_HWO;
721 gpd->gpd_info |= GPDMA_DESC_BDP;
722 /* need to clear first. use these bits to calc checksum */
723 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
724 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
725
726 /* modify bd */
727 for_each_sg(data->sg, sg, data->sg_count, j) {
728 dma_address = sg_dma_address(sg);
729 dma_len = sg_dma_len(sg);
730
731 /* init bd */
732 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
733 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
734 bd[j].ptr = lower_32_bits(dma_address);
735 if (host->dev_comp->support_64g) {
736 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
737 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
738 << 28;
739 }
740
741 if (host->dev_comp->support_64g) {
742 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
743 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
744 } else {
745 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
746 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
747 }
748
749 if (j == data->sg_count - 1) /* the last bd */
750 bd[j].bd_info |= BDMA_DESC_EOL;
751 else
752 bd[j].bd_info &= ~BDMA_DESC_EOL;
753
754 /* checksum need to clear first */
755 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
756 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
757 }
758
759 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
760 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
761 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
762 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
763 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
764 if (host->dev_comp->support_64g)
765 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
766 upper_32_bits(dma->gpd_addr) & 0xf);
767 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
768 }
769
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)770 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
771 {
772 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
773 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
774 mmc_get_dma_dir(data));
775 if (data->sg_count)
776 data->host_cookie |= MSDC_PREPARE_FLAG;
777 }
778 }
779
msdc_data_prepared(struct mmc_data * data)780 static bool msdc_data_prepared(struct mmc_data *data)
781 {
782 return data->host_cookie & MSDC_PREPARE_FLAG;
783 }
784
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)785 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
786 {
787 if (data->host_cookie & MSDC_ASYNC_FLAG)
788 return;
789
790 if (data->host_cookie & MSDC_PREPARE_FLAG) {
791 dma_unmap_sg(host->dev, data->sg, data->sg_len,
792 mmc_get_dma_dir(data));
793 data->host_cookie &= ~MSDC_PREPARE_FLAG;
794 }
795 }
796
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)797 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
798 {
799 struct mmc_host *mmc = mmc_from_priv(host);
800 u64 timeout, clk_ns;
801 u32 mode = 0;
802
803 if (mmc->actual_clock == 0) {
804 timeout = 0;
805 } else {
806 clk_ns = 1000000000ULL;
807 do_div(clk_ns, mmc->actual_clock);
808 timeout = ns + clk_ns - 1;
809 do_div(timeout, clk_ns);
810 timeout += clks;
811 /* in 1048576 sclk cycle unit */
812 timeout = DIV_ROUND_UP(timeout, BIT(20));
813 if (host->dev_comp->clk_div_bits == 8)
814 sdr_get_field(host->base + MSDC_CFG,
815 MSDC_CFG_CKMOD, &mode);
816 else
817 sdr_get_field(host->base + MSDC_CFG,
818 MSDC_CFG_CKMOD_EXTRA, &mode);
819 /*DDR mode will double the clk cycles for data timeout */
820 timeout = mode >= 2 ? timeout * 2 : timeout;
821 timeout = timeout > 1 ? timeout - 1 : 0;
822 }
823 return timeout;
824 }
825
826 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)827 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
828 {
829 u64 timeout;
830
831 host->timeout_ns = ns;
832 host->timeout_clks = clks;
833
834 timeout = msdc_timeout_cal(host, ns, clks);
835 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
836 (u32)(timeout > 255 ? 255 : timeout));
837 }
838
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)839 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
840 {
841 u64 timeout;
842
843 timeout = msdc_timeout_cal(host, ns, clks);
844 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
845 (u32)(timeout > 8191 ? 8191 : timeout));
846 }
847
msdc_gate_clock(struct msdc_host * host)848 static void msdc_gate_clock(struct msdc_host *host)
849 {
850 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
851 clk_disable_unprepare(host->crypto_clk);
852 clk_disable_unprepare(host->src_clk_cg);
853 clk_disable_unprepare(host->src_clk);
854 clk_disable_unprepare(host->bus_clk);
855 clk_disable_unprepare(host->h_clk);
856 }
857
msdc_ungate_clock(struct msdc_host * host)858 static int msdc_ungate_clock(struct msdc_host *host)
859 {
860 u32 val;
861 int ret;
862
863 clk_prepare_enable(host->h_clk);
864 clk_prepare_enable(host->bus_clk);
865 clk_prepare_enable(host->src_clk);
866 clk_prepare_enable(host->src_clk_cg);
867 clk_prepare_enable(host->crypto_clk);
868 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
869 if (ret) {
870 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
871 return ret;
872 }
873
874 return readl_poll_timeout(host->base + MSDC_CFG, val,
875 (val & MSDC_CFG_CKSTB), 1, 20000);
876 }
877
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)878 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
879 {
880 struct mmc_host *mmc = mmc_from_priv(host);
881 u32 mode;
882 u32 flags;
883 u32 div;
884 u32 sclk;
885 u32 tune_reg = host->dev_comp->pad_tune_reg;
886 u32 val;
887
888 if (!hz) {
889 dev_dbg(host->dev, "set mclk to 0\n");
890 host->mclk = 0;
891 mmc->actual_clock = 0;
892 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
893 return;
894 }
895
896 flags = readl(host->base + MSDC_INTEN);
897 sdr_clr_bits(host->base + MSDC_INTEN, flags);
898 if (host->dev_comp->clk_div_bits == 8)
899 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
900 else
901 sdr_clr_bits(host->base + MSDC_CFG,
902 MSDC_CFG_HS400_CK_MODE_EXTRA);
903 if (timing == MMC_TIMING_UHS_DDR50 ||
904 timing == MMC_TIMING_MMC_DDR52 ||
905 timing == MMC_TIMING_MMC_HS400) {
906 if (timing == MMC_TIMING_MMC_HS400)
907 mode = 0x3;
908 else
909 mode = 0x2; /* ddr mode and use divisor */
910
911 if (hz >= (host->src_clk_freq >> 2)) {
912 div = 0; /* mean div = 1/4 */
913 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
914 } else {
915 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
916 sclk = (host->src_clk_freq >> 2) / div;
917 div = (div >> 1);
918 }
919
920 if (timing == MMC_TIMING_MMC_HS400 &&
921 hz >= (host->src_clk_freq >> 1)) {
922 if (host->dev_comp->clk_div_bits == 8)
923 sdr_set_bits(host->base + MSDC_CFG,
924 MSDC_CFG_HS400_CK_MODE);
925 else
926 sdr_set_bits(host->base + MSDC_CFG,
927 MSDC_CFG_HS400_CK_MODE_EXTRA);
928 sclk = host->src_clk_freq >> 1;
929 div = 0; /* div is ignore when bit18 is set */
930 }
931 } else if (hz >= host->src_clk_freq) {
932 mode = 0x1; /* no divisor */
933 div = 0;
934 sclk = host->src_clk_freq;
935 } else {
936 mode = 0x0; /* use divisor */
937 if (hz >= (host->src_clk_freq >> 1)) {
938 div = 0; /* mean div = 1/2 */
939 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
940 } else {
941 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
942 sclk = (host->src_clk_freq >> 2) / div;
943 }
944 }
945 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
946
947 clk_disable_unprepare(host->src_clk_cg);
948 if (host->dev_comp->clk_div_bits == 8)
949 sdr_set_field(host->base + MSDC_CFG,
950 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
951 (mode << 8) | div);
952 else
953 sdr_set_field(host->base + MSDC_CFG,
954 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
955 (mode << 12) | div);
956
957 clk_prepare_enable(host->src_clk_cg);
958 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
959 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
960 mmc->actual_clock = sclk;
961 host->mclk = hz;
962 host->timing = timing;
963 /* need because clk changed. */
964 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
965 sdr_set_bits(host->base + MSDC_INTEN, flags);
966
967 /*
968 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
969 * tune result of hs200/200Mhz is not suitable for 50Mhz
970 */
971 if (mmc->actual_clock <= 52000000) {
972 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
973 if (host->top_base) {
974 writel(host->def_tune_para.emmc_top_control,
975 host->top_base + EMMC_TOP_CONTROL);
976 writel(host->def_tune_para.emmc_top_cmd,
977 host->top_base + EMMC_TOP_CMD);
978 } else {
979 writel(host->def_tune_para.pad_tune,
980 host->base + tune_reg);
981 }
982 } else {
983 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
984 writel(host->saved_tune_para.pad_cmd_tune,
985 host->base + PAD_CMD_TUNE);
986 if (host->top_base) {
987 writel(host->saved_tune_para.emmc_top_control,
988 host->top_base + EMMC_TOP_CONTROL);
989 writel(host->saved_tune_para.emmc_top_cmd,
990 host->top_base + EMMC_TOP_CMD);
991 } else {
992 writel(host->saved_tune_para.pad_tune,
993 host->base + tune_reg);
994 }
995 }
996
997 if (timing == MMC_TIMING_MMC_HS400 &&
998 host->dev_comp->hs400_tune)
999 sdr_set_field(host->base + tune_reg,
1000 MSDC_PAD_TUNE_CMDRRDLY,
1001 host->hs400_cmd_int_delay);
1002 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1003 timing);
1004 }
1005
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_command * cmd)1006 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1007 struct mmc_command *cmd)
1008 {
1009 u32 resp;
1010
1011 switch (mmc_resp_type(cmd)) {
1012 /* Actually, R1, R5, R6, R7 are the same */
1013 case MMC_RSP_R1:
1014 resp = 0x1;
1015 break;
1016 case MMC_RSP_R1B:
1017 resp = 0x7;
1018 break;
1019 case MMC_RSP_R2:
1020 resp = 0x2;
1021 break;
1022 case MMC_RSP_R3:
1023 resp = 0x3;
1024 break;
1025 case MMC_RSP_NONE:
1026 default:
1027 resp = 0x0;
1028 break;
1029 }
1030
1031 return resp;
1032 }
1033
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1034 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1035 struct mmc_request *mrq, struct mmc_command *cmd)
1036 {
1037 struct mmc_host *mmc = mmc_from_priv(host);
1038 /* rawcmd :
1039 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1040 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1041 */
1042 u32 opcode = cmd->opcode;
1043 u32 resp = msdc_cmd_find_resp(host, cmd);
1044 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1045
1046 host->cmd_rsp = resp;
1047
1048 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1049 opcode == MMC_STOP_TRANSMISSION)
1050 rawcmd |= BIT(14);
1051 else if (opcode == SD_SWITCH_VOLTAGE)
1052 rawcmd |= BIT(30);
1053 else if (opcode == SD_APP_SEND_SCR ||
1054 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1055 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1056 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1057 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1058 rawcmd |= BIT(11);
1059
1060 if (cmd->data) {
1061 struct mmc_data *data = cmd->data;
1062
1063 if (mmc_op_multi(opcode)) {
1064 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1065 !(mrq->sbc->arg & 0xFFFF0000))
1066 rawcmd |= BIT(29); /* AutoCMD23 */
1067 }
1068
1069 rawcmd |= ((data->blksz & 0xFFF) << 16);
1070 if (data->flags & MMC_DATA_WRITE)
1071 rawcmd |= BIT(13);
1072 if (data->blocks > 1)
1073 rawcmd |= BIT(12);
1074 else
1075 rawcmd |= BIT(11);
1076 /* Always use dma mode */
1077 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1078
1079 if (host->timeout_ns != data->timeout_ns ||
1080 host->timeout_clks != data->timeout_clks)
1081 msdc_set_timeout(host, data->timeout_ns,
1082 data->timeout_clks);
1083
1084 writel(data->blocks, host->base + SDC_BLK_NUM);
1085 }
1086 return rawcmd;
1087 }
1088
msdc_start_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1089 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1090 struct mmc_data *data)
1091 {
1092 bool read;
1093
1094 WARN_ON(host->data);
1095 host->data = data;
1096 read = data->flags & MMC_DATA_READ;
1097
1098 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1099 msdc_dma_setup(host, &host->dma, data);
1100 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1101 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1102 dev_dbg(host->dev, "DMA start\n");
1103 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1104 __func__, cmd->opcode, data->blocks, read);
1105 }
1106
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1107 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1108 struct mmc_command *cmd)
1109 {
1110 u32 *rsp = cmd->resp;
1111
1112 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1113
1114 if (events & MSDC_INT_ACMDRDY) {
1115 cmd->error = 0;
1116 } else {
1117 msdc_reset_hw(host);
1118 if (events & MSDC_INT_ACMDCRCERR) {
1119 cmd->error = -EILSEQ;
1120 host->error |= REQ_STOP_EIO;
1121 } else if (events & MSDC_INT_ACMDTMO) {
1122 cmd->error = -ETIMEDOUT;
1123 host->error |= REQ_STOP_TMO;
1124 }
1125 dev_err(host->dev,
1126 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1127 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1128 }
1129 return cmd->error;
1130 }
1131
1132 /*
1133 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1134 *
1135 * Host controller may lost interrupt in some special case.
1136 * Add SDIO irq recheck mechanism to make sure all interrupts
1137 * can be processed immediately
1138 */
msdc_recheck_sdio_irq(struct msdc_host * host)1139 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1140 {
1141 struct mmc_host *mmc = mmc_from_priv(host);
1142 u32 reg_int, reg_inten, reg_ps;
1143
1144 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1145 reg_inten = readl(host->base + MSDC_INTEN);
1146 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1147 reg_int = readl(host->base + MSDC_INT);
1148 reg_ps = readl(host->base + MSDC_PS);
1149 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1150 reg_ps & MSDC_PS_DATA1)) {
1151 __msdc_enable_sdio_irq(host, 0);
1152 sdio_signal_irq(mmc);
1153 }
1154 }
1155 }
1156 }
1157
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd)1158 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1159 {
1160 if (host->error)
1161 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1162 __func__, cmd->opcode, cmd->arg, host->error);
1163 }
1164
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1165 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1166 {
1167 unsigned long flags;
1168
1169 /*
1170 * No need check the return value of cancel_delayed_work, as only ONE
1171 * path will go here!
1172 */
1173 cancel_delayed_work(&host->req_timeout);
1174
1175 spin_lock_irqsave(&host->lock, flags);
1176 host->mrq = NULL;
1177 spin_unlock_irqrestore(&host->lock, flags);
1178
1179 msdc_track_cmd_data(host, mrq->cmd);
1180 if (mrq->data)
1181 msdc_unprepare_data(host, mrq->data);
1182 if (host->error)
1183 msdc_reset_hw(host);
1184 mmc_request_done(mmc_from_priv(host), mrq);
1185 if (host->dev_comp->recheck_sdio_irq)
1186 msdc_recheck_sdio_irq(host);
1187 }
1188
1189 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1190 static bool msdc_cmd_done(struct msdc_host *host, int events,
1191 struct mmc_request *mrq, struct mmc_command *cmd)
1192 {
1193 bool done = false;
1194 bool sbc_error;
1195 unsigned long flags;
1196 u32 *rsp;
1197
1198 if (mrq->sbc && cmd == mrq->cmd &&
1199 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1200 | MSDC_INT_ACMDTMO)))
1201 msdc_auto_cmd_done(host, events, mrq->sbc);
1202
1203 sbc_error = mrq->sbc && mrq->sbc->error;
1204
1205 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1206 | MSDC_INT_RSPCRCERR
1207 | MSDC_INT_CMDTMO)))
1208 return done;
1209
1210 spin_lock_irqsave(&host->lock, flags);
1211 done = !host->cmd;
1212 host->cmd = NULL;
1213 spin_unlock_irqrestore(&host->lock, flags);
1214
1215 if (done)
1216 return true;
1217 rsp = cmd->resp;
1218
1219 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1220
1221 if (cmd->flags & MMC_RSP_PRESENT) {
1222 if (cmd->flags & MMC_RSP_136) {
1223 rsp[0] = readl(host->base + SDC_RESP3);
1224 rsp[1] = readl(host->base + SDC_RESP2);
1225 rsp[2] = readl(host->base + SDC_RESP1);
1226 rsp[3] = readl(host->base + SDC_RESP0);
1227 } else {
1228 rsp[0] = readl(host->base + SDC_RESP0);
1229 }
1230 }
1231
1232 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1233 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1234 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1235 /*
1236 * should not clear fifo/interrupt as the tune data
1237 * may have already come when cmd19/cmd21 gets response
1238 * CRC error.
1239 */
1240 msdc_reset_hw(host);
1241 if (events & MSDC_INT_RSPCRCERR) {
1242 cmd->error = -EILSEQ;
1243 host->error |= REQ_CMD_EIO;
1244 } else if (events & MSDC_INT_CMDTMO) {
1245 cmd->error = -ETIMEDOUT;
1246 host->error |= REQ_CMD_TMO;
1247 }
1248 }
1249 if (cmd->error)
1250 dev_dbg(host->dev,
1251 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1252 __func__, cmd->opcode, cmd->arg, rsp[0],
1253 cmd->error);
1254
1255 msdc_cmd_next(host, mrq, cmd);
1256 return true;
1257 }
1258
1259 /* It is the core layer's responsibility to ensure card status
1260 * is correct before issue a request. but host design do below
1261 * checks recommended.
1262 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1263 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1264 struct mmc_request *mrq, struct mmc_command *cmd)
1265 {
1266 u32 val;
1267 int ret;
1268
1269 /* The max busy time we can endure is 20ms */
1270 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1271 !(val & SDC_STS_CMDBUSY), 1, 20000);
1272 if (ret) {
1273 dev_err(host->dev, "CMD bus busy detected\n");
1274 host->error |= REQ_CMD_BUSY;
1275 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1276 return false;
1277 }
1278
1279 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1280 /* R1B or with data, should check SDCBUSY */
1281 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1282 !(val & SDC_STS_SDCBUSY), 1, 20000);
1283 if (ret) {
1284 dev_err(host->dev, "Controller busy detected\n");
1285 host->error |= REQ_CMD_BUSY;
1286 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1287 return false;
1288 }
1289 }
1290 return true;
1291 }
1292
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1293 static void msdc_start_command(struct msdc_host *host,
1294 struct mmc_request *mrq, struct mmc_command *cmd)
1295 {
1296 u32 rawcmd;
1297 unsigned long flags;
1298
1299 WARN_ON(host->cmd);
1300 host->cmd = cmd;
1301
1302 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1303 if (!msdc_cmd_is_ready(host, mrq, cmd))
1304 return;
1305
1306 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1307 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1308 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1309 msdc_reset_hw(host);
1310 }
1311
1312 cmd->error = 0;
1313 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1314
1315 spin_lock_irqsave(&host->lock, flags);
1316 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1317 spin_unlock_irqrestore(&host->lock, flags);
1318
1319 writel(cmd->arg, host->base + SDC_ARG);
1320 writel(rawcmd, host->base + SDC_CMD);
1321 }
1322
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1323 static void msdc_cmd_next(struct msdc_host *host,
1324 struct mmc_request *mrq, struct mmc_command *cmd)
1325 {
1326 if ((cmd->error && !host->hs400_tuning &&
1327 !(cmd->error == -EILSEQ &&
1328 mmc_op_tuning(cmd->opcode))) ||
1329 (mrq->sbc && mrq->sbc->error))
1330 msdc_request_done(host, mrq);
1331 else if (cmd == mrq->sbc)
1332 msdc_start_command(host, mrq, mrq->cmd);
1333 else if (!cmd->data)
1334 msdc_request_done(host, mrq);
1335 else
1336 msdc_start_data(host, cmd, cmd->data);
1337 }
1338
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1339 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1340 {
1341 struct msdc_host *host = mmc_priv(mmc);
1342
1343 host->error = 0;
1344 WARN_ON(host->mrq);
1345 host->mrq = mrq;
1346
1347 if (mrq->data) {
1348 msdc_prepare_data(host, mrq->data);
1349 if (!msdc_data_prepared(mrq->data)) {
1350 host->mrq = NULL;
1351 /*
1352 * Failed to prepare DMA area, fail fast before
1353 * starting any commands.
1354 */
1355 mrq->cmd->error = -ENOSPC;
1356 mmc_request_done(mmc_from_priv(host), mrq);
1357 return;
1358 }
1359 }
1360
1361 /* if SBC is required, we have HW option and SW option.
1362 * if HW option is enabled, and SBC does not have "special" flags,
1363 * use HW option, otherwise use SW option
1364 */
1365 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1366 (mrq->sbc->arg & 0xFFFF0000)))
1367 msdc_start_command(host, mrq, mrq->sbc);
1368 else
1369 msdc_start_command(host, mrq, mrq->cmd);
1370 }
1371
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1372 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1373 {
1374 struct msdc_host *host = mmc_priv(mmc);
1375 struct mmc_data *data = mrq->data;
1376
1377 if (!data)
1378 return;
1379
1380 msdc_prepare_data(host, data);
1381 data->host_cookie |= MSDC_ASYNC_FLAG;
1382 }
1383
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1384 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1385 int err)
1386 {
1387 struct msdc_host *host = mmc_priv(mmc);
1388 struct mmc_data *data = mrq->data;
1389
1390 if (!data)
1391 return;
1392
1393 if (data->host_cookie) {
1394 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1395 msdc_unprepare_data(host, data);
1396 }
1397 }
1398
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1399 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1400 {
1401 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1402 !mrq->sbc)
1403 msdc_start_command(host, mrq, mrq->stop);
1404 else
1405 msdc_request_done(host, mrq);
1406 }
1407
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1408 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1409 struct mmc_request *mrq, struct mmc_data *data)
1410 {
1411 struct mmc_command *stop;
1412 unsigned long flags;
1413 bool done;
1414 unsigned int check_data = events &
1415 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1416 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1417 | MSDC_INT_DMA_PROTECT);
1418 u32 val;
1419 int ret;
1420
1421 spin_lock_irqsave(&host->lock, flags);
1422 done = !host->data;
1423 if (check_data)
1424 host->data = NULL;
1425 spin_unlock_irqrestore(&host->lock, flags);
1426
1427 if (done)
1428 return;
1429 stop = data->stop;
1430
1431 if (check_data || (stop && stop->error)) {
1432 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1433 readl(host->base + MSDC_DMA_CFG));
1434 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1435 1);
1436
1437 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1438 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1439 if (ret)
1440 dev_dbg(host->dev, "DMA stop timed out\n");
1441
1442 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1443 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1444 if (ret)
1445 dev_dbg(host->dev, "DMA inactive timed out\n");
1446
1447 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1448 dev_dbg(host->dev, "DMA stop\n");
1449
1450 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1451 data->bytes_xfered = data->blocks * data->blksz;
1452 } else {
1453 dev_dbg(host->dev, "interrupt events: %x\n", events);
1454 msdc_reset_hw(host);
1455 host->error |= REQ_DAT_ERR;
1456 data->bytes_xfered = 0;
1457
1458 if (events & MSDC_INT_DATTMO)
1459 data->error = -ETIMEDOUT;
1460 else if (events & MSDC_INT_DATCRCERR)
1461 data->error = -EILSEQ;
1462
1463 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1464 __func__, mrq->cmd->opcode, data->blocks);
1465 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1466 (int)data->error, data->bytes_xfered);
1467 }
1468
1469 msdc_data_xfer_next(host, mrq);
1470 }
1471 }
1472
msdc_set_buswidth(struct msdc_host * host,u32 width)1473 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1474 {
1475 u32 val = readl(host->base + SDC_CFG);
1476
1477 val &= ~SDC_CFG_BUSWIDTH;
1478
1479 switch (width) {
1480 default:
1481 case MMC_BUS_WIDTH_1:
1482 val |= (MSDC_BUS_1BITS << 16);
1483 break;
1484 case MMC_BUS_WIDTH_4:
1485 val |= (MSDC_BUS_4BITS << 16);
1486 break;
1487 case MMC_BUS_WIDTH_8:
1488 val |= (MSDC_BUS_8BITS << 16);
1489 break;
1490 }
1491
1492 writel(val, host->base + SDC_CFG);
1493 dev_dbg(host->dev, "Bus Width = %d", width);
1494 }
1495
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1496 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1497 {
1498 struct msdc_host *host = mmc_priv(mmc);
1499 int ret;
1500
1501 if (!IS_ERR(mmc->supply.vqmmc)) {
1502 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1503 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1504 dev_err(host->dev, "Unsupported signal voltage!\n");
1505 return -EINVAL;
1506 }
1507
1508 ret = mmc_regulator_set_vqmmc(mmc, ios);
1509 if (ret < 0) {
1510 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1511 ret, ios->signal_voltage);
1512 return ret;
1513 }
1514
1515 /* Apply different pinctrl settings for different signal voltage */
1516 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1517 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1518 else
1519 pinctrl_select_state(host->pinctrl, host->pins_default);
1520 }
1521 return 0;
1522 }
1523
msdc_card_busy(struct mmc_host * mmc)1524 static int msdc_card_busy(struct mmc_host *mmc)
1525 {
1526 struct msdc_host *host = mmc_priv(mmc);
1527 u32 status = readl(host->base + MSDC_PS);
1528
1529 /* only check if data0 is low */
1530 return !(status & BIT(16));
1531 }
1532
msdc_request_timeout(struct work_struct * work)1533 static void msdc_request_timeout(struct work_struct *work)
1534 {
1535 struct msdc_host *host = container_of(work, struct msdc_host,
1536 req_timeout.work);
1537
1538 /* simulate HW timeout status */
1539 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1540 if (host->mrq) {
1541 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1542 host->mrq, host->mrq->cmd->opcode);
1543 if (host->cmd) {
1544 dev_err(host->dev, "%s: aborting cmd=%d\n",
1545 __func__, host->cmd->opcode);
1546 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1547 host->cmd);
1548 } else if (host->data) {
1549 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1550 __func__, host->mrq->cmd->opcode,
1551 host->data->blocks);
1552 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1553 host->data);
1554 }
1555 }
1556 }
1557
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1558 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1559 {
1560 if (enb) {
1561 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1562 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1563 if (host->dev_comp->recheck_sdio_irq)
1564 msdc_recheck_sdio_irq(host);
1565 } else {
1566 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1567 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1568 }
1569 }
1570
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1571 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1572 {
1573 struct msdc_host *host = mmc_priv(mmc);
1574 unsigned long flags;
1575 int ret;
1576
1577 spin_lock_irqsave(&host->lock, flags);
1578 __msdc_enable_sdio_irq(host, enb);
1579 spin_unlock_irqrestore(&host->lock, flags);
1580
1581 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1582 if (enb) {
1583 /*
1584 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1585 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1586 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1587 * affect successfully, we change the pinstate to pins_eint firstly.
1588 */
1589 pinctrl_select_state(host->pinctrl, host->pins_eint);
1590 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1591
1592 if (ret) {
1593 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1594 host->pins_eint = NULL;
1595 pm_runtime_get_noresume(host->dev);
1596 } else {
1597 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1598 }
1599
1600 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1601 } else {
1602 dev_pm_clear_wake_irq(host->dev);
1603 }
1604 } else {
1605 if (enb) {
1606 /* Ensure host->pins_eint is NULL */
1607 host->pins_eint = NULL;
1608 pm_runtime_get_noresume(host->dev);
1609 } else {
1610 pm_runtime_put_noidle(host->dev);
1611 }
1612 }
1613 }
1614
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1615 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1616 {
1617 struct mmc_host *mmc = mmc_from_priv(host);
1618 int cmd_err = 0, dat_err = 0;
1619
1620 if (intsts & MSDC_INT_RSPCRCERR) {
1621 cmd_err = -EILSEQ;
1622 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1623 } else if (intsts & MSDC_INT_CMDTMO) {
1624 cmd_err = -ETIMEDOUT;
1625 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1626 }
1627
1628 if (intsts & MSDC_INT_DATCRCERR) {
1629 dat_err = -EILSEQ;
1630 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1631 } else if (intsts & MSDC_INT_DATTMO) {
1632 dat_err = -ETIMEDOUT;
1633 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1634 }
1635
1636 if (cmd_err || dat_err) {
1637 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x",
1638 cmd_err, dat_err, intsts);
1639 }
1640
1641 return cqhci_irq(mmc, 0, cmd_err, dat_err);
1642 }
1643
msdc_irq(int irq,void * dev_id)1644 static irqreturn_t msdc_irq(int irq, void *dev_id)
1645 {
1646 struct msdc_host *host = (struct msdc_host *) dev_id;
1647 struct mmc_host *mmc = mmc_from_priv(host);
1648
1649 while (true) {
1650 struct mmc_request *mrq;
1651 struct mmc_command *cmd;
1652 struct mmc_data *data;
1653 u32 events, event_mask;
1654
1655 spin_lock(&host->lock);
1656 events = readl(host->base + MSDC_INT);
1657 event_mask = readl(host->base + MSDC_INTEN);
1658 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1659 __msdc_enable_sdio_irq(host, 0);
1660 /* clear interrupts */
1661 writel(events & event_mask, host->base + MSDC_INT);
1662
1663 mrq = host->mrq;
1664 cmd = host->cmd;
1665 data = host->data;
1666 spin_unlock(&host->lock);
1667
1668 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1669 sdio_signal_irq(mmc);
1670
1671 if ((events & event_mask) & MSDC_INT_CDSC) {
1672 if (host->internal_cd)
1673 mmc_detect_change(mmc, msecs_to_jiffies(20));
1674 events &= ~MSDC_INT_CDSC;
1675 }
1676
1677 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1678 break;
1679
1680 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1681 (events & MSDC_INT_CMDQ)) {
1682 msdc_cmdq_irq(host, events);
1683 /* clear interrupts */
1684 writel(events, host->base + MSDC_INT);
1685 return IRQ_HANDLED;
1686 }
1687
1688 if (!mrq) {
1689 dev_err(host->dev,
1690 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1691 __func__, events, event_mask);
1692 WARN_ON(1);
1693 break;
1694 }
1695
1696 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1697
1698 if (cmd)
1699 msdc_cmd_done(host, events, mrq, cmd);
1700 else if (data)
1701 msdc_data_xfer_done(host, events, mrq, data);
1702 }
1703
1704 return IRQ_HANDLED;
1705 }
1706
msdc_init_hw(struct msdc_host * host)1707 static void msdc_init_hw(struct msdc_host *host)
1708 {
1709 u32 val;
1710 u32 tune_reg = host->dev_comp->pad_tune_reg;
1711 struct mmc_host *mmc = mmc_from_priv(host);
1712
1713 if (host->reset) {
1714 reset_control_assert(host->reset);
1715 usleep_range(10, 50);
1716 reset_control_deassert(host->reset);
1717 }
1718
1719 /* Configure to MMC/SD mode, clock free running */
1720 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1721
1722 /* Reset */
1723 msdc_reset_hw(host);
1724
1725 /* Disable and clear all interrupts */
1726 writel(0, host->base + MSDC_INTEN);
1727 val = readl(host->base + MSDC_INT);
1728 writel(val, host->base + MSDC_INT);
1729
1730 /* Configure card detection */
1731 if (host->internal_cd) {
1732 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1733 DEFAULT_DEBOUNCE);
1734 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1735 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1736 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1737 } else {
1738 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1739 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1740 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1741 }
1742
1743 if (host->top_base) {
1744 writel(0, host->top_base + EMMC_TOP_CONTROL);
1745 writel(0, host->top_base + EMMC_TOP_CMD);
1746 } else {
1747 writel(0, host->base + tune_reg);
1748 }
1749 writel(0, host->base + MSDC_IOCON);
1750 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1751 writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1752 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1753 writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1754 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1755
1756 if (host->dev_comp->stop_clk_fix) {
1757 sdr_set_field(host->base + MSDC_PATCH_BIT1,
1758 MSDC_PATCH_BIT1_STOP_DLY, 3);
1759 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1760 SDC_FIFO_CFG_WRVALIDSEL);
1761 sdr_clr_bits(host->base + SDC_FIFO_CFG,
1762 SDC_FIFO_CFG_RDVALIDSEL);
1763 }
1764
1765 if (host->dev_comp->busy_check)
1766 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1767
1768 if (host->dev_comp->async_fifo) {
1769 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1770 MSDC_PB2_RESPWAIT, 3);
1771 if (host->dev_comp->enhance_rx) {
1772 if (host->top_base)
1773 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1774 SDC_RX_ENH_EN);
1775 else
1776 sdr_set_bits(host->base + SDC_ADV_CFG0,
1777 SDC_RX_ENHANCE_EN);
1778 } else {
1779 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1780 MSDC_PB2_RESPSTSENSEL, 2);
1781 sdr_set_field(host->base + MSDC_PATCH_BIT2,
1782 MSDC_PB2_CRCSTSENSEL, 2);
1783 }
1784 /* use async fifo, then no need tune internal delay */
1785 sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1786 MSDC_PATCH_BIT2_CFGRESP);
1787 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1788 MSDC_PATCH_BIT2_CFGCRCSTS);
1789 }
1790
1791 if (host->dev_comp->support_64g)
1792 sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1793 MSDC_PB2_SUPPORT_64G);
1794 if (host->dev_comp->data_tune) {
1795 if (host->top_base) {
1796 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1797 PAD_DAT_RD_RXDLY_SEL);
1798 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1799 DATA_K_VALUE_SEL);
1800 sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1801 PAD_CMD_RD_RXDLY_SEL);
1802 } else {
1803 sdr_set_bits(host->base + tune_reg,
1804 MSDC_PAD_TUNE_RD_SEL |
1805 MSDC_PAD_TUNE_CMD_SEL);
1806 }
1807 } else {
1808 /* choose clock tune */
1809 if (host->top_base)
1810 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1811 PAD_RXDLY_SEL);
1812 else
1813 sdr_set_bits(host->base + tune_reg,
1814 MSDC_PAD_TUNE_RXDLYSEL);
1815 }
1816
1817 if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1818 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1819 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1820 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1821 } else {
1822 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1823 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1824
1825 /* Config SDIO device detect interrupt function */
1826 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1827 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1828 }
1829
1830 /* Configure to default data timeout */
1831 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1832
1833 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1834 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1835 if (host->top_base) {
1836 host->def_tune_para.emmc_top_control =
1837 readl(host->top_base + EMMC_TOP_CONTROL);
1838 host->def_tune_para.emmc_top_cmd =
1839 readl(host->top_base + EMMC_TOP_CMD);
1840 host->saved_tune_para.emmc_top_control =
1841 readl(host->top_base + EMMC_TOP_CONTROL);
1842 host->saved_tune_para.emmc_top_cmd =
1843 readl(host->top_base + EMMC_TOP_CMD);
1844 } else {
1845 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1846 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1847 }
1848 dev_dbg(host->dev, "init hardware done!");
1849 }
1850
msdc_deinit_hw(struct msdc_host * host)1851 static void msdc_deinit_hw(struct msdc_host *host)
1852 {
1853 u32 val;
1854
1855 if (host->internal_cd) {
1856 /* Disabled card-detect */
1857 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1858 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1859 }
1860
1861 /* Disable and clear all interrupts */
1862 writel(0, host->base + MSDC_INTEN);
1863
1864 val = readl(host->base + MSDC_INT);
1865 writel(val, host->base + MSDC_INT);
1866 }
1867
1868 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)1869 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1870 {
1871 struct mt_gpdma_desc *gpd = dma->gpd;
1872 struct mt_bdma_desc *bd = dma->bd;
1873 dma_addr_t dma_addr;
1874 int i;
1875
1876 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1877
1878 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1879 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1880 /* gpd->next is must set for desc DMA
1881 * That's why must alloc 2 gpd structure.
1882 */
1883 gpd->next = lower_32_bits(dma_addr);
1884 if (host->dev_comp->support_64g)
1885 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1886
1887 dma_addr = dma->bd_addr;
1888 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1889 if (host->dev_comp->support_64g)
1890 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1891
1892 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1893 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1894 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1895 bd[i].next = lower_32_bits(dma_addr);
1896 if (host->dev_comp->support_64g)
1897 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1898 }
1899 }
1900
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1901 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1902 {
1903 struct msdc_host *host = mmc_priv(mmc);
1904 int ret;
1905
1906 msdc_set_buswidth(host, ios->bus_width);
1907
1908 /* Suspend/Resume will do power off/on */
1909 switch (ios->power_mode) {
1910 case MMC_POWER_UP:
1911 if (!IS_ERR(mmc->supply.vmmc)) {
1912 msdc_init_hw(host);
1913 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1914 ios->vdd);
1915 if (ret) {
1916 dev_err(host->dev, "Failed to set vmmc power!\n");
1917 return;
1918 }
1919 }
1920 break;
1921 case MMC_POWER_ON:
1922 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1923 ret = regulator_enable(mmc->supply.vqmmc);
1924 if (ret)
1925 dev_err(host->dev, "Failed to set vqmmc power!\n");
1926 else
1927 host->vqmmc_enabled = true;
1928 }
1929 break;
1930 case MMC_POWER_OFF:
1931 if (!IS_ERR(mmc->supply.vmmc))
1932 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1933
1934 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1935 regulator_disable(mmc->supply.vqmmc);
1936 host->vqmmc_enabled = false;
1937 }
1938 break;
1939 default:
1940 break;
1941 }
1942
1943 if (host->mclk != ios->clock || host->timing != ios->timing)
1944 msdc_set_mclk(host, ios->timing, ios->clock);
1945 }
1946
test_delay_bit(u32 delay,u32 bit)1947 static u32 test_delay_bit(u32 delay, u32 bit)
1948 {
1949 bit %= PAD_DELAY_MAX;
1950 return delay & BIT(bit);
1951 }
1952
get_delay_len(u32 delay,u32 start_bit)1953 static int get_delay_len(u32 delay, u32 start_bit)
1954 {
1955 int i;
1956
1957 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) {
1958 if (test_delay_bit(delay, start_bit + i) == 0)
1959 return i;
1960 }
1961 return PAD_DELAY_MAX - start_bit;
1962 }
1963
get_best_delay(struct msdc_host * host,u32 delay)1964 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay)
1965 {
1966 int start = 0, len = 0;
1967 int start_final = 0, len_final = 0;
1968 u8 final_phase = 0xff;
1969 struct msdc_delay_phase delay_phase = { 0, };
1970
1971 if (delay == 0) {
1972 dev_err(host->dev, "phase error: [map:%x]\n", delay);
1973 delay_phase.final_phase = final_phase;
1974 return delay_phase;
1975 }
1976
1977 while (start < PAD_DELAY_MAX) {
1978 len = get_delay_len(delay, start);
1979 if (len_final < len) {
1980 start_final = start;
1981 len_final = len;
1982 }
1983 start += len ? len : 1;
1984 if (len >= 12 && start_final < 4)
1985 break;
1986 }
1987
1988 /* The rule is that to find the smallest delay cell */
1989 if (start_final == 0)
1990 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX;
1991 else
1992 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX;
1993 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n",
1994 delay, len_final, final_phase);
1995
1996 delay_phase.maxlen = len_final;
1997 delay_phase.start = start_final;
1998 delay_phase.final_phase = final_phase;
1999 return delay_phase;
2000 }
2001
msdc_set_cmd_delay(struct msdc_host * host,u32 value)2002 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2003 {
2004 u32 tune_reg = host->dev_comp->pad_tune_reg;
2005
2006 if (host->top_base)
2007 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
2008 value);
2009 else
2010 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2011 value);
2012 }
2013
msdc_set_data_delay(struct msdc_host * host,u32 value)2014 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2015 {
2016 u32 tune_reg = host->dev_comp->pad_tune_reg;
2017
2018 if (host->top_base)
2019 sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2020 PAD_DAT_RD_RXDLY, value);
2021 else
2022 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2023 value);
2024 }
2025
msdc_tune_response(struct mmc_host * mmc,u32 opcode)2026 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2027 {
2028 struct msdc_host *host = mmc_priv(mmc);
2029 u32 rise_delay = 0, fall_delay = 0;
2030 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2031 struct msdc_delay_phase internal_delay_phase;
2032 u8 final_delay, final_maxlen;
2033 u32 internal_delay = 0;
2034 u32 tune_reg = host->dev_comp->pad_tune_reg;
2035 int cmd_err;
2036 int i, j;
2037
2038 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2039 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2040 sdr_set_field(host->base + tune_reg,
2041 MSDC_PAD_TUNE_CMDRRDLY,
2042 host->hs200_cmd_int_delay);
2043
2044 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2045 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2046 msdc_set_cmd_delay(host, i);
2047 /*
2048 * Using the same parameters, it may sometimes pass the test,
2049 * but sometimes it may fail. To make sure the parameters are
2050 * more stable, we test each set of parameters 3 times.
2051 */
2052 for (j = 0; j < 3; j++) {
2053 mmc_send_tuning(mmc, opcode, &cmd_err);
2054 if (!cmd_err) {
2055 rise_delay |= BIT(i);
2056 } else {
2057 rise_delay &= ~BIT(i);
2058 break;
2059 }
2060 }
2061 }
2062 final_rise_delay = get_best_delay(host, rise_delay);
2063 /* if rising edge has enough margin, then do not scan falling edge */
2064 if (final_rise_delay.maxlen >= 12 ||
2065 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2066 goto skip_fall;
2067
2068 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2069 for (i = 0; i < PAD_DELAY_MAX; i++) {
2070 msdc_set_cmd_delay(host, i);
2071 /*
2072 * Using the same parameters, it may sometimes pass the test,
2073 * but sometimes it may fail. To make sure the parameters are
2074 * more stable, we test each set of parameters 3 times.
2075 */
2076 for (j = 0; j < 3; j++) {
2077 mmc_send_tuning(mmc, opcode, &cmd_err);
2078 if (!cmd_err) {
2079 fall_delay |= BIT(i);
2080 } else {
2081 fall_delay &= ~BIT(i);
2082 break;
2083 }
2084 }
2085 }
2086 final_fall_delay = get_best_delay(host, fall_delay);
2087
2088 skip_fall:
2089 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2090 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2091 final_maxlen = final_fall_delay.maxlen;
2092 if (final_maxlen == final_rise_delay.maxlen) {
2093 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2094 final_delay = final_rise_delay.final_phase;
2095 } else {
2096 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2097 final_delay = final_fall_delay.final_phase;
2098 }
2099 msdc_set_cmd_delay(host, final_delay);
2100
2101 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2102 goto skip_internal;
2103
2104 for (i = 0; i < PAD_DELAY_MAX; i++) {
2105 sdr_set_field(host->base + tune_reg,
2106 MSDC_PAD_TUNE_CMDRRDLY, i);
2107 mmc_send_tuning(mmc, opcode, &cmd_err);
2108 if (!cmd_err)
2109 internal_delay |= BIT(i);
2110 }
2111 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2112 internal_delay_phase = get_best_delay(host, internal_delay);
2113 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2114 internal_delay_phase.final_phase);
2115 skip_internal:
2116 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2117 return final_delay == 0xff ? -EIO : 0;
2118 }
2119
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2120 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2121 {
2122 struct msdc_host *host = mmc_priv(mmc);
2123 u32 cmd_delay = 0;
2124 struct msdc_delay_phase final_cmd_delay = { 0,};
2125 u8 final_delay;
2126 int cmd_err;
2127 int i, j;
2128
2129 /* select EMMC50 PAD CMD tune */
2130 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2131 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2132
2133 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2134 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2135 sdr_set_field(host->base + MSDC_PAD_TUNE,
2136 MSDC_PAD_TUNE_CMDRRDLY,
2137 host->hs200_cmd_int_delay);
2138
2139 if (host->hs400_cmd_resp_sel_rising)
2140 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2141 else
2142 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2143 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2144 sdr_set_field(host->base + PAD_CMD_TUNE,
2145 PAD_CMD_TUNE_RX_DLY3, i);
2146 /*
2147 * Using the same parameters, it may sometimes pass the test,
2148 * but sometimes it may fail. To make sure the parameters are
2149 * more stable, we test each set of parameters 3 times.
2150 */
2151 for (j = 0; j < 3; j++) {
2152 mmc_send_tuning(mmc, opcode, &cmd_err);
2153 if (!cmd_err) {
2154 cmd_delay |= BIT(i);
2155 } else {
2156 cmd_delay &= ~BIT(i);
2157 break;
2158 }
2159 }
2160 }
2161 final_cmd_delay = get_best_delay(host, cmd_delay);
2162 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2163 final_cmd_delay.final_phase);
2164 final_delay = final_cmd_delay.final_phase;
2165
2166 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2167 return final_delay == 0xff ? -EIO : 0;
2168 }
2169
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2170 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2171 {
2172 struct msdc_host *host = mmc_priv(mmc);
2173 u32 rise_delay = 0, fall_delay = 0;
2174 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2175 u8 final_delay, final_maxlen;
2176 int i, ret;
2177
2178 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2179 host->latch_ck);
2180 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2181 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2182 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2183 msdc_set_data_delay(host, i);
2184 ret = mmc_send_tuning(mmc, opcode, NULL);
2185 if (!ret)
2186 rise_delay |= BIT(i);
2187 }
2188 final_rise_delay = get_best_delay(host, rise_delay);
2189 /* if rising edge has enough margin, then do not scan falling edge */
2190 if (final_rise_delay.maxlen >= 12 ||
2191 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2192 goto skip_fall;
2193
2194 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2195 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2196 for (i = 0; i < PAD_DELAY_MAX; i++) {
2197 msdc_set_data_delay(host, i);
2198 ret = mmc_send_tuning(mmc, opcode, NULL);
2199 if (!ret)
2200 fall_delay |= BIT(i);
2201 }
2202 final_fall_delay = get_best_delay(host, fall_delay);
2203
2204 skip_fall:
2205 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2206 if (final_maxlen == final_rise_delay.maxlen) {
2207 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2208 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2209 final_delay = final_rise_delay.final_phase;
2210 } else {
2211 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2212 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2213 final_delay = final_fall_delay.final_phase;
2214 }
2215 msdc_set_data_delay(host, final_delay);
2216
2217 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2218 return final_delay == 0xff ? -EIO : 0;
2219 }
2220
2221 /*
2222 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2223 * together, which can save the tuning time.
2224 */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2225 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2226 {
2227 struct msdc_host *host = mmc_priv(mmc);
2228 u32 rise_delay = 0, fall_delay = 0;
2229 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2230 u8 final_delay, final_maxlen;
2231 int i, ret;
2232
2233 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2234 host->latch_ck);
2235
2236 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2237 sdr_clr_bits(host->base + MSDC_IOCON,
2238 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2239 for (i = 0 ; i < PAD_DELAY_MAX; i++) {
2240 msdc_set_cmd_delay(host, i);
2241 msdc_set_data_delay(host, i);
2242 ret = mmc_send_tuning(mmc, opcode, NULL);
2243 if (!ret)
2244 rise_delay |= BIT(i);
2245 }
2246 final_rise_delay = get_best_delay(host, rise_delay);
2247 /* if rising edge has enough margin, then do not scan falling edge */
2248 if (final_rise_delay.maxlen >= 12 ||
2249 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2250 goto skip_fall;
2251
2252 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2253 sdr_set_bits(host->base + MSDC_IOCON,
2254 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2255 for (i = 0; i < PAD_DELAY_MAX; i++) {
2256 msdc_set_cmd_delay(host, i);
2257 msdc_set_data_delay(host, i);
2258 ret = mmc_send_tuning(mmc, opcode, NULL);
2259 if (!ret)
2260 fall_delay |= BIT(i);
2261 }
2262 final_fall_delay = get_best_delay(host, fall_delay);
2263
2264 skip_fall:
2265 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2266 if (final_maxlen == final_rise_delay.maxlen) {
2267 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2268 sdr_clr_bits(host->base + MSDC_IOCON,
2269 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2270 final_delay = final_rise_delay.final_phase;
2271 } else {
2272 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2273 sdr_set_bits(host->base + MSDC_IOCON,
2274 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2275 final_delay = final_fall_delay.final_phase;
2276 }
2277
2278 msdc_set_cmd_delay(host, final_delay);
2279 msdc_set_data_delay(host, final_delay);
2280
2281 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2282 return final_delay == 0xff ? -EIO : 0;
2283 }
2284
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2285 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2286 {
2287 struct msdc_host *host = mmc_priv(mmc);
2288 int ret;
2289 u32 tune_reg = host->dev_comp->pad_tune_reg;
2290
2291 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2292 ret = msdc_tune_together(mmc, opcode);
2293 if (host->hs400_mode) {
2294 sdr_clr_bits(host->base + MSDC_IOCON,
2295 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2296 msdc_set_data_delay(host, 0);
2297 }
2298 goto tune_done;
2299 }
2300 if (host->hs400_mode &&
2301 host->dev_comp->hs400_tune)
2302 ret = hs400_tune_response(mmc, opcode);
2303 else
2304 ret = msdc_tune_response(mmc, opcode);
2305 if (ret == -EIO) {
2306 dev_err(host->dev, "Tune response fail!\n");
2307 return ret;
2308 }
2309 if (host->hs400_mode == false) {
2310 ret = msdc_tune_data(mmc, opcode);
2311 if (ret == -EIO)
2312 dev_err(host->dev, "Tune data fail!\n");
2313 }
2314
2315 tune_done:
2316 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2317 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2318 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2319 if (host->top_base) {
2320 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2321 EMMC_TOP_CONTROL);
2322 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2323 EMMC_TOP_CMD);
2324 }
2325 return ret;
2326 }
2327
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2328 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2329 {
2330 struct msdc_host *host = mmc_priv(mmc);
2331
2332 host->hs400_mode = true;
2333
2334 if (host->top_base) {
2335 if (host->hs400_ds_dly3)
2336 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2337 PAD_DS_DLY3, host->hs400_ds_dly3);
2338 if (host->hs400_ds_delay)
2339 writel(host->hs400_ds_delay,
2340 host->top_base + EMMC50_PAD_DS_TUNE);
2341 } else {
2342 if (host->hs400_ds_dly3)
2343 sdr_set_field(host->base + PAD_DS_TUNE,
2344 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2345 if (host->hs400_ds_delay)
2346 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2347 }
2348 /* hs400 mode must set it to 0 */
2349 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2350 /* to improve read performance, set outstanding to 2 */
2351 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2352
2353 return 0;
2354 }
2355
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2356 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2357 {
2358 struct msdc_host *host = mmc_priv(mmc);
2359 struct msdc_delay_phase dly1_delay;
2360 u32 val, result_dly1 = 0;
2361 u8 *ext_csd;
2362 int i, ret;
2363
2364 if (host->top_base) {
2365 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2366 PAD_DS_DLY_SEL);
2367 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2368 PAD_DS_DLY2_SEL);
2369 } else {
2370 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2371 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL);
2372 }
2373
2374 host->hs400_tuning = true;
2375 for (i = 0; i < PAD_DELAY_MAX; i++) {
2376 if (host->top_base)
2377 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2378 PAD_DS_DLY1, i);
2379 else
2380 sdr_set_field(host->base + PAD_DS_TUNE,
2381 PAD_DS_TUNE_DLY1, i);
2382 ret = mmc_get_ext_csd(card, &ext_csd);
2383 if (!ret) {
2384 result_dly1 |= BIT(i);
2385 kfree(ext_csd);
2386 }
2387 }
2388 host->hs400_tuning = false;
2389
2390 dly1_delay = get_best_delay(host, result_dly1);
2391 if (dly1_delay.maxlen == 0) {
2392 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2393 goto fail;
2394 }
2395 if (host->top_base)
2396 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2397 PAD_DS_DLY1, dly1_delay.final_phase);
2398 else
2399 sdr_set_field(host->base + PAD_DS_TUNE,
2400 PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2401
2402 if (host->top_base)
2403 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2404 else
2405 val = readl(host->base + PAD_DS_TUNE);
2406
2407 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2408
2409 return 0;
2410
2411 fail:
2412 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2413 return -EIO;
2414 }
2415
msdc_hw_reset(struct mmc_host * mmc)2416 static void msdc_hw_reset(struct mmc_host *mmc)
2417 {
2418 struct msdc_host *host = mmc_priv(mmc);
2419
2420 sdr_set_bits(host->base + EMMC_IOCON, 1);
2421 udelay(10); /* 10us is enough */
2422 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2423 }
2424
msdc_ack_sdio_irq(struct mmc_host * mmc)2425 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2426 {
2427 unsigned long flags;
2428 struct msdc_host *host = mmc_priv(mmc);
2429
2430 spin_lock_irqsave(&host->lock, flags);
2431 __msdc_enable_sdio_irq(host, 1);
2432 spin_unlock_irqrestore(&host->lock, flags);
2433 }
2434
msdc_get_cd(struct mmc_host * mmc)2435 static int msdc_get_cd(struct mmc_host *mmc)
2436 {
2437 struct msdc_host *host = mmc_priv(mmc);
2438 int val;
2439
2440 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2441 return 1;
2442
2443 if (!host->internal_cd)
2444 return mmc_gpio_get_cd(mmc);
2445
2446 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2447 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2448 return !!val;
2449 else
2450 return !val;
2451 }
2452
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2453 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2454 struct mmc_ios *ios)
2455 {
2456 struct msdc_host *host = mmc_priv(mmc);
2457
2458 if (ios->enhanced_strobe) {
2459 msdc_prepare_hs400_tuning(mmc, ios);
2460 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2461 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2462 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2463
2464 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2465 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2466 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2467 } else {
2468 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2469 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2470 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2471
2472 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2473 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2474 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2475 }
2476 }
2477
msdc_cqe_cit_cal(struct msdc_host * host,u64 timer_ns)2478 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2479 {
2480 struct mmc_host *mmc = mmc_from_priv(host);
2481 struct cqhci_host *cq_host = mmc->cqe_private;
2482 u8 itcfmul;
2483 u64 hclk_freq, value;
2484
2485 /*
2486 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2487 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2488 * Send Status Command Idle Timer (CIT) value.
2489 */
2490 hclk_freq = (u64)clk_get_rate(host->h_clk);
2491 itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2492 switch (itcfmul) {
2493 case 0x0:
2494 do_div(hclk_freq, 1000);
2495 break;
2496 case 0x1:
2497 do_div(hclk_freq, 100);
2498 break;
2499 case 0x2:
2500 do_div(hclk_freq, 10);
2501 break;
2502 case 0x3:
2503 break;
2504 case 0x4:
2505 hclk_freq = hclk_freq * 10;
2506 break;
2507 default:
2508 host->cq_ssc1_time = 0x40;
2509 return;
2510 }
2511
2512 value = hclk_freq * timer_ns;
2513 do_div(value, 1000000000);
2514 host->cq_ssc1_time = value;
2515 }
2516
msdc_cqe_enable(struct mmc_host * mmc)2517 static void msdc_cqe_enable(struct mmc_host *mmc)
2518 {
2519 struct msdc_host *host = mmc_priv(mmc);
2520 struct cqhci_host *cq_host = mmc->cqe_private;
2521
2522 /* enable cmdq irq */
2523 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2524 /* enable busy check */
2525 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2526 /* default write data / busy timeout 20s */
2527 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2528 /* default read data timeout 1s */
2529 msdc_set_timeout(host, 1000000000ULL, 0);
2530
2531 /* Set the send status command idle timer */
2532 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2533 }
2534
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2535 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2536 {
2537 struct msdc_host *host = mmc_priv(mmc);
2538 unsigned int val = 0;
2539
2540 /* disable cmdq irq */
2541 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2542 /* disable busy check */
2543 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2544
2545 val = readl(host->base + MSDC_INT);
2546 writel(val, host->base + MSDC_INT);
2547
2548 if (recovery) {
2549 sdr_set_field(host->base + MSDC_DMA_CTRL,
2550 MSDC_DMA_CTRL_STOP, 1);
2551 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2552 !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2553 return;
2554 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2555 !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2556 return;
2557 msdc_reset_hw(host);
2558 }
2559 }
2560
msdc_cqe_pre_enable(struct mmc_host * mmc)2561 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2562 {
2563 struct cqhci_host *cq_host = mmc->cqe_private;
2564 u32 reg;
2565
2566 reg = cqhci_readl(cq_host, CQHCI_CFG);
2567 reg |= CQHCI_ENABLE;
2568 cqhci_writel(cq_host, reg, CQHCI_CFG);
2569 }
2570
msdc_cqe_post_disable(struct mmc_host * mmc)2571 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2572 {
2573 struct cqhci_host *cq_host = mmc->cqe_private;
2574 u32 reg;
2575
2576 reg = cqhci_readl(cq_host, CQHCI_CFG);
2577 reg &= ~CQHCI_ENABLE;
2578 cqhci_writel(cq_host, reg, CQHCI_CFG);
2579 }
2580
2581 static const struct mmc_host_ops mt_msdc_ops = {
2582 .post_req = msdc_post_req,
2583 .pre_req = msdc_pre_req,
2584 .request = msdc_ops_request,
2585 .set_ios = msdc_ops_set_ios,
2586 .get_ro = mmc_gpio_get_ro,
2587 .get_cd = msdc_get_cd,
2588 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2589 .enable_sdio_irq = msdc_enable_sdio_irq,
2590 .ack_sdio_irq = msdc_ack_sdio_irq,
2591 .start_signal_voltage_switch = msdc_ops_switch_volt,
2592 .card_busy = msdc_card_busy,
2593 .execute_tuning = msdc_execute_tuning,
2594 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2595 .execute_hs400_tuning = msdc_execute_hs400_tuning,
2596 .card_hw_reset = msdc_hw_reset,
2597 };
2598
2599 static const struct cqhci_host_ops msdc_cmdq_ops = {
2600 .enable = msdc_cqe_enable,
2601 .disable = msdc_cqe_disable,
2602 .pre_enable = msdc_cqe_pre_enable,
2603 .post_disable = msdc_cqe_post_disable,
2604 };
2605
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2606 static void msdc_of_property_parse(struct platform_device *pdev,
2607 struct msdc_host *host)
2608 {
2609 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2610 &host->latch_ck);
2611
2612 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2613 &host->hs400_ds_delay);
2614
2615 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2616 &host->hs400_ds_dly3);
2617
2618 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2619 &host->hs200_cmd_int_delay);
2620
2621 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2622 &host->hs400_cmd_int_delay);
2623
2624 if (of_property_read_bool(pdev->dev.of_node,
2625 "mediatek,hs400-cmd-resp-sel-rising"))
2626 host->hs400_cmd_resp_sel_rising = true;
2627 else
2628 host->hs400_cmd_resp_sel_rising = false;
2629
2630 if (of_property_read_bool(pdev->dev.of_node,
2631 "supports-cqe"))
2632 host->cqhci = true;
2633 else
2634 host->cqhci = false;
2635 }
2636
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2637 static int msdc_of_clock_parse(struct platform_device *pdev,
2638 struct msdc_host *host)
2639 {
2640 int ret;
2641
2642 host->src_clk = devm_clk_get(&pdev->dev, "source");
2643 if (IS_ERR(host->src_clk))
2644 return PTR_ERR(host->src_clk);
2645
2646 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2647 if (IS_ERR(host->h_clk))
2648 return PTR_ERR(host->h_clk);
2649
2650 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2651 if (IS_ERR(host->bus_clk))
2652 host->bus_clk = NULL;
2653
2654 /*source clock control gate is optional clock*/
2655 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2656 if (IS_ERR(host->src_clk_cg))
2657 return PTR_ERR(host->src_clk_cg);
2658
2659 /*
2660 * Fallback for legacy device-trees: src_clk and HCLK use the same
2661 * bit to control gating but they are parented to a different mux,
2662 * hence if our intention is to gate only the source, required
2663 * during a clk mode switch to avoid hw hangs, we need to gate
2664 * its parent (specified as a different clock only on new DTs).
2665 */
2666 if (!host->src_clk_cg) {
2667 host->src_clk_cg = clk_get_parent(host->src_clk);
2668 if (IS_ERR(host->src_clk_cg))
2669 return PTR_ERR(host->src_clk_cg);
2670 }
2671
2672 /* If present, always enable for this clock gate */
2673 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2674 if (IS_ERR(host->sys_clk_cg))
2675 host->sys_clk_cg = NULL;
2676
2677 host->bulk_clks[0].id = "pclk_cg";
2678 host->bulk_clks[1].id = "axi_cg";
2679 host->bulk_clks[2].id = "ahb_cg";
2680 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2681 host->bulk_clks);
2682 if (ret) {
2683 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2684 return ret;
2685 }
2686
2687 return 0;
2688 }
2689
msdc_drv_probe(struct platform_device * pdev)2690 static int msdc_drv_probe(struct platform_device *pdev)
2691 {
2692 struct mmc_host *mmc;
2693 struct msdc_host *host;
2694 struct resource *res;
2695 int ret;
2696
2697 if (!pdev->dev.of_node) {
2698 dev_err(&pdev->dev, "No DT found\n");
2699 return -EINVAL;
2700 }
2701
2702 /* Allocate MMC host for this device */
2703 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host));
2704 if (!mmc)
2705 return -ENOMEM;
2706
2707 host = mmc_priv(mmc);
2708 ret = mmc_of_parse(mmc);
2709 if (ret)
2710 return ret;
2711
2712 host->base = devm_platform_ioremap_resource(pdev, 0);
2713 if (IS_ERR(host->base))
2714 return PTR_ERR(host->base);
2715
2716 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2717 if (res) {
2718 host->top_base = devm_ioremap_resource(&pdev->dev, res);
2719 if (IS_ERR(host->top_base))
2720 host->top_base = NULL;
2721 }
2722
2723 ret = mmc_regulator_get_supply(mmc);
2724 if (ret)
2725 return ret;
2726
2727 ret = msdc_of_clock_parse(pdev, host);
2728 if (ret)
2729 return ret;
2730
2731 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2732 "hrst");
2733 if (IS_ERR(host->reset))
2734 return PTR_ERR(host->reset);
2735
2736 /* only eMMC has crypto property */
2737 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2738 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2739 if (IS_ERR(host->crypto_clk))
2740 return PTR_ERR(host->crypto_clk);
2741 else if (host->crypto_clk)
2742 mmc->caps2 |= MMC_CAP2_CRYPTO;
2743 }
2744
2745 host->irq = platform_get_irq(pdev, 0);
2746 if (host->irq < 0)
2747 return host->irq;
2748
2749 host->pinctrl = devm_pinctrl_get(&pdev->dev);
2750 if (IS_ERR(host->pinctrl))
2751 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl),
2752 "Cannot find pinctrl");
2753
2754 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2755 if (IS_ERR(host->pins_default)) {
2756 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2757 return PTR_ERR(host->pins_default);
2758 }
2759
2760 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2761 if (IS_ERR(host->pins_uhs)) {
2762 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2763 return PTR_ERR(host->pins_uhs);
2764 }
2765
2766 /* Support for SDIO eint irq ? */
2767 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2768 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2769 if (host->eint_irq > 0) {
2770 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2771 if (IS_ERR(host->pins_eint)) {
2772 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2773 host->pins_eint = NULL;
2774 } else {
2775 device_init_wakeup(&pdev->dev, true);
2776 }
2777 }
2778 }
2779
2780 msdc_of_property_parse(pdev, host);
2781
2782 host->dev = &pdev->dev;
2783 host->dev_comp = of_device_get_match_data(&pdev->dev);
2784 host->src_clk_freq = clk_get_rate(host->src_clk);
2785 /* Set host parameters to mmc */
2786 mmc->ops = &mt_msdc_ops;
2787 if (host->dev_comp->clk_div_bits == 8)
2788 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2789 else
2790 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2791
2792 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2793 !mmc_can_gpio_cd(mmc) &&
2794 host->dev_comp->use_internal_cd) {
2795 /*
2796 * Is removable but no GPIO declared, so
2797 * use internal functionality.
2798 */
2799 host->internal_cd = true;
2800 }
2801
2802 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2803 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2804
2805 mmc->caps |= MMC_CAP_CMD23;
2806 if (host->cqhci)
2807 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2808 /* MMC core transfer sizes tunable parameters */
2809 mmc->max_segs = MAX_BD_NUM;
2810 if (host->dev_comp->support_64g)
2811 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2812 else
2813 mmc->max_seg_size = BDMA_DESC_BUFLEN;
2814 mmc->max_blk_size = 2048;
2815 mmc->max_req_size = 512 * 1024;
2816 mmc->max_blk_count = mmc->max_req_size / 512;
2817 if (host->dev_comp->support_64g)
2818 host->dma_mask = DMA_BIT_MASK(36);
2819 else
2820 host->dma_mask = DMA_BIT_MASK(32);
2821 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2822
2823 host->timeout_clks = 3 * 1048576;
2824 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2825 2 * sizeof(struct mt_gpdma_desc),
2826 &host->dma.gpd_addr, GFP_KERNEL);
2827 host->dma.bd = dma_alloc_coherent(&pdev->dev,
2828 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2829 &host->dma.bd_addr, GFP_KERNEL);
2830 if (!host->dma.gpd || !host->dma.bd) {
2831 ret = -ENOMEM;
2832 goto release_mem;
2833 }
2834 msdc_init_gpd_bd(host, &host->dma);
2835 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2836 spin_lock_init(&host->lock);
2837
2838 platform_set_drvdata(pdev, mmc);
2839 ret = msdc_ungate_clock(host);
2840 if (ret) {
2841 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2842 goto release_clk;
2843 }
2844 msdc_init_hw(host);
2845
2846 if (mmc->caps2 & MMC_CAP2_CQE) {
2847 host->cq_host = devm_kzalloc(mmc->parent,
2848 sizeof(*host->cq_host),
2849 GFP_KERNEL);
2850 if (!host->cq_host) {
2851 ret = -ENOMEM;
2852 goto release;
2853 }
2854 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2855 host->cq_host->mmio = host->base + 0x800;
2856 host->cq_host->ops = &msdc_cmdq_ops;
2857 ret = cqhci_init(host->cq_host, mmc, true);
2858 if (ret)
2859 goto release;
2860 mmc->max_segs = 128;
2861 /* cqhci 16bit length */
2862 /* 0 size, means 65536 so we don't have to -1 here */
2863 mmc->max_seg_size = 64 * 1024;
2864 /* Reduce CIT to 0x40 that corresponds to 2.35us */
2865 msdc_cqe_cit_cal(host, 2350);
2866 }
2867
2868 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2869 IRQF_TRIGGER_NONE, pdev->name, host);
2870 if (ret)
2871 goto release;
2872
2873 pm_runtime_set_active(host->dev);
2874 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2875 pm_runtime_use_autosuspend(host->dev);
2876 pm_runtime_enable(host->dev);
2877 ret = mmc_add_host(mmc);
2878
2879 if (ret)
2880 goto end;
2881
2882 return 0;
2883 end:
2884 pm_runtime_disable(host->dev);
2885 release:
2886 msdc_deinit_hw(host);
2887 release_clk:
2888 msdc_gate_clock(host);
2889 platform_set_drvdata(pdev, NULL);
2890 release_mem:
2891 device_init_wakeup(&pdev->dev, false);
2892 if (host->dma.gpd)
2893 dma_free_coherent(&pdev->dev,
2894 2 * sizeof(struct mt_gpdma_desc),
2895 host->dma.gpd, host->dma.gpd_addr);
2896 if (host->dma.bd)
2897 dma_free_coherent(&pdev->dev,
2898 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2899 host->dma.bd, host->dma.bd_addr);
2900 return ret;
2901 }
2902
msdc_drv_remove(struct platform_device * pdev)2903 static void msdc_drv_remove(struct platform_device *pdev)
2904 {
2905 struct mmc_host *mmc;
2906 struct msdc_host *host;
2907
2908 mmc = platform_get_drvdata(pdev);
2909 host = mmc_priv(mmc);
2910
2911 pm_runtime_get_sync(host->dev);
2912
2913 platform_set_drvdata(pdev, NULL);
2914 mmc_remove_host(mmc);
2915 msdc_deinit_hw(host);
2916 msdc_gate_clock(host);
2917
2918 pm_runtime_disable(host->dev);
2919 pm_runtime_put_noidle(host->dev);
2920 dma_free_coherent(&pdev->dev,
2921 2 * sizeof(struct mt_gpdma_desc),
2922 host->dma.gpd, host->dma.gpd_addr);
2923 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2924 host->dma.bd, host->dma.bd_addr);
2925 device_init_wakeup(&pdev->dev, false);
2926 }
2927
msdc_save_reg(struct msdc_host * host)2928 static void msdc_save_reg(struct msdc_host *host)
2929 {
2930 u32 tune_reg = host->dev_comp->pad_tune_reg;
2931
2932 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2933 host->save_para.iocon = readl(host->base + MSDC_IOCON);
2934 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2935 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2936 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2937 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2938 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2939 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2940 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2941 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2942 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2943 if (host->top_base) {
2944 host->save_para.emmc_top_control =
2945 readl(host->top_base + EMMC_TOP_CONTROL);
2946 host->save_para.emmc_top_cmd =
2947 readl(host->top_base + EMMC_TOP_CMD);
2948 host->save_para.emmc50_pad_ds_tune =
2949 readl(host->top_base + EMMC50_PAD_DS_TUNE);
2950 } else {
2951 host->save_para.pad_tune = readl(host->base + tune_reg);
2952 }
2953 }
2954
msdc_restore_reg(struct msdc_host * host)2955 static void msdc_restore_reg(struct msdc_host *host)
2956 {
2957 struct mmc_host *mmc = mmc_from_priv(host);
2958 u32 tune_reg = host->dev_comp->pad_tune_reg;
2959
2960 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
2961 writel(host->save_para.iocon, host->base + MSDC_IOCON);
2962 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
2963 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
2964 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
2965 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
2966 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
2967 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
2968 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
2969 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
2970 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
2971 if (host->top_base) {
2972 writel(host->save_para.emmc_top_control,
2973 host->top_base + EMMC_TOP_CONTROL);
2974 writel(host->save_para.emmc_top_cmd,
2975 host->top_base + EMMC_TOP_CMD);
2976 writel(host->save_para.emmc50_pad_ds_tune,
2977 host->top_base + EMMC50_PAD_DS_TUNE);
2978 } else {
2979 writel(host->save_para.pad_tune, host->base + tune_reg);
2980 }
2981
2982 if (sdio_irq_claimed(mmc))
2983 __msdc_enable_sdio_irq(host, 1);
2984 }
2985
msdc_runtime_suspend(struct device * dev)2986 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
2987 {
2988 struct mmc_host *mmc = dev_get_drvdata(dev);
2989 struct msdc_host *host = mmc_priv(mmc);
2990
2991 msdc_save_reg(host);
2992
2993 if (sdio_irq_claimed(mmc)) {
2994 if (host->pins_eint) {
2995 disable_irq(host->irq);
2996 pinctrl_select_state(host->pinctrl, host->pins_eint);
2997 }
2998
2999 __msdc_enable_sdio_irq(host, 0);
3000 }
3001 msdc_gate_clock(host);
3002 return 0;
3003 }
3004
msdc_runtime_resume(struct device * dev)3005 static int __maybe_unused msdc_runtime_resume(struct device *dev)
3006 {
3007 struct mmc_host *mmc = dev_get_drvdata(dev);
3008 struct msdc_host *host = mmc_priv(mmc);
3009 int ret;
3010
3011 ret = msdc_ungate_clock(host);
3012 if (ret)
3013 return ret;
3014
3015 msdc_restore_reg(host);
3016
3017 if (sdio_irq_claimed(mmc) && host->pins_eint) {
3018 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3019 enable_irq(host->irq);
3020 }
3021 return 0;
3022 }
3023
msdc_suspend(struct device * dev)3024 static int __maybe_unused msdc_suspend(struct device *dev)
3025 {
3026 struct mmc_host *mmc = dev_get_drvdata(dev);
3027 struct msdc_host *host = mmc_priv(mmc);
3028 int ret;
3029 u32 val;
3030
3031 if (mmc->caps2 & MMC_CAP2_CQE) {
3032 ret = cqhci_suspend(mmc);
3033 if (ret)
3034 return ret;
3035 val = readl(host->base + MSDC_INT);
3036 writel(val, host->base + MSDC_INT);
3037 }
3038
3039 /*
3040 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3041 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3042 */
3043 if (sdio_irq_claimed(mmc) && host->pins_eint)
3044 pm_runtime_get_noresume(dev);
3045
3046 return pm_runtime_force_suspend(dev);
3047 }
3048
msdc_resume(struct device * dev)3049 static int __maybe_unused msdc_resume(struct device *dev)
3050 {
3051 struct mmc_host *mmc = dev_get_drvdata(dev);
3052 struct msdc_host *host = mmc_priv(mmc);
3053
3054 if (sdio_irq_claimed(mmc) && host->pins_eint)
3055 pm_runtime_put_noidle(dev);
3056
3057 return pm_runtime_force_resume(dev);
3058 }
3059
3060 static const struct dev_pm_ops msdc_dev_pm_ops = {
3061 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3062 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3063 };
3064
3065 static struct platform_driver mt_msdc_driver = {
3066 .probe = msdc_drv_probe,
3067 .remove_new = msdc_drv_remove,
3068 .driver = {
3069 .name = "mtk-msdc",
3070 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3071 .of_match_table = msdc_of_ids,
3072 .pm = &msdc_dev_pm_ops,
3073 },
3074 };
3075
3076 module_platform_driver(mt_msdc_driver);
3077 MODULE_LICENSE("GPL v2");
3078 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3079