xref: /openbmc/u-boot/drivers/mmc/jz_mmc.c (revision 82d54647)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Ingenic JZ MMC driver
4  *
5  * Copyright (c) 2013 Imagination Technologies
6  * Author: Paul Burton <paul.burton@imgtec.com>
7  */
8 
9 #include <common.h>
10 #include <malloc.h>
11 #include <mmc.h>
12 #include <asm/io.h>
13 #include <asm/unaligned.h>
14 #include <errno.h>
15 #include <mach/jz4780.h>
16 #include <wait_bit.h>
17 
18 /* Registers */
19 #define MSC_STRPCL			0x000
20 #define MSC_STAT			0x004
21 #define MSC_CLKRT			0x008
22 #define MSC_CMDAT			0x00c
23 #define MSC_RESTO			0x010
24 #define MSC_RDTO			0x014
25 #define MSC_BLKLEN			0x018
26 #define MSC_NOB				0x01c
27 #define MSC_SNOB			0x020
28 #define MSC_IMASK			0x024
29 #define MSC_IREG			0x028
30 #define MSC_CMD				0x02c
31 #define MSC_ARG				0x030
32 #define MSC_RES				0x034
33 #define MSC_RXFIFO			0x038
34 #define MSC_TXFIFO			0x03c
35 #define MSC_LPM				0x040
36 #define MSC_DMAC			0x044
37 #define MSC_DMANDA			0x048
38 #define MSC_DMADA			0x04c
39 #define MSC_DMALEN			0x050
40 #define MSC_DMACMD			0x054
41 #define MSC_CTRL2			0x058
42 #define MSC_RTCNT			0x05c
43 #define MSC_DBG				0x0fc
44 
45 /* MSC Clock and Control Register (MSC_STRPCL) */
46 #define MSC_STRPCL_EXIT_MULTIPLE	BIT(7)
47 #define MSC_STRPCL_EXIT_TRANSFER	BIT(6)
48 #define MSC_STRPCL_START_READWAIT	BIT(5)
49 #define MSC_STRPCL_STOP_READWAIT	BIT(4)
50 #define MSC_STRPCL_RESET		BIT(3)
51 #define MSC_STRPCL_START_OP		BIT(2)
52 #define MSC_STRPCL_CLOCK_CONTROL_STOP	BIT(0)
53 #define MSC_STRPCL_CLOCK_CONTROL_START	BIT(1)
54 
55 /* MSC Status Register (MSC_STAT) */
56 #define MSC_STAT_AUTO_CMD_DONE		BIT(31)
57 #define MSC_STAT_IS_RESETTING		BIT(15)
58 #define MSC_STAT_SDIO_INT_ACTIVE	BIT(14)
59 #define MSC_STAT_PRG_DONE		BIT(13)
60 #define MSC_STAT_DATA_TRAN_DONE		BIT(12)
61 #define MSC_STAT_END_CMD_RES		BIT(11)
62 #define MSC_STAT_DATA_FIFO_AFULL	BIT(10)
63 #define MSC_STAT_IS_READWAIT		BIT(9)
64 #define MSC_STAT_CLK_EN			BIT(8)
65 #define MSC_STAT_DATA_FIFO_FULL		BIT(7)
66 #define MSC_STAT_DATA_FIFO_EMPTY	BIT(6)
67 #define MSC_STAT_CRC_RES_ERR		BIT(5)
68 #define MSC_STAT_CRC_READ_ERROR		BIT(4)
69 #define MSC_STAT_CRC_WRITE_ERROR	BIT(2)
70 #define MSC_STAT_CRC_WRITE_ERROR_NOSTS	BIT(4)
71 #define MSC_STAT_TIME_OUT_RES		BIT(1)
72 #define MSC_STAT_TIME_OUT_READ		BIT(0)
73 
74 /* MSC Bus Clock Control Register (MSC_CLKRT) */
75 #define MSC_CLKRT_CLK_RATE_MASK		0x7
76 
77 /* MSC Command Sequence Control Register (MSC_CMDAT) */
78 #define MSC_CMDAT_IO_ABORT		BIT(11)
79 #define MSC_CMDAT_BUS_WIDTH_1BIT	(0x0 << 9)
80 #define MSC_CMDAT_BUS_WIDTH_4BIT	(0x2 << 9)
81 #define MSC_CMDAT_DMA_EN		BIT(8)
82 #define MSC_CMDAT_INIT			BIT(7)
83 #define MSC_CMDAT_BUSY			BIT(6)
84 #define MSC_CMDAT_STREAM_BLOCK		BIT(5)
85 #define MSC_CMDAT_WRITE			BIT(4)
86 #define MSC_CMDAT_DATA_EN		BIT(3)
87 #define MSC_CMDAT_RESPONSE_MASK		(0x7 << 0)
88 #define MSC_CMDAT_RESPONSE_NONE		(0x0 << 0) /* No response */
89 #define MSC_CMDAT_RESPONSE_R1		(0x1 << 0) /* Format R1 and R1b */
90 #define MSC_CMDAT_RESPONSE_R2		(0x2 << 0) /* Format R2 */
91 #define MSC_CMDAT_RESPONSE_R3		(0x3 << 0) /* Format R3 */
92 #define MSC_CMDAT_RESPONSE_R4		(0x4 << 0) /* Format R4 */
93 #define MSC_CMDAT_RESPONSE_R5		(0x5 << 0) /* Format R5 */
94 #define MSC_CMDAT_RESPONSE_R6		(0x6 << 0) /* Format R6 */
95 
96 /* MSC Interrupts Mask Register (MSC_IMASK) */
97 #define MSC_IMASK_TIME_OUT_RES		BIT(9)
98 #define MSC_IMASK_TIME_OUT_READ		BIT(8)
99 #define MSC_IMASK_SDIO			BIT(7)
100 #define MSC_IMASK_TXFIFO_WR_REQ		BIT(6)
101 #define MSC_IMASK_RXFIFO_RD_REQ		BIT(5)
102 #define MSC_IMASK_END_CMD_RES		BIT(2)
103 #define MSC_IMASK_PRG_DONE		BIT(1)
104 #define MSC_IMASK_DATA_TRAN_DONE	BIT(0)
105 
106 /* MSC Interrupts Status Register (MSC_IREG) */
107 #define MSC_IREG_TIME_OUT_RES		BIT(9)
108 #define MSC_IREG_TIME_OUT_READ		BIT(8)
109 #define MSC_IREG_SDIO			BIT(7)
110 #define MSC_IREG_TXFIFO_WR_REQ		BIT(6)
111 #define MSC_IREG_RXFIFO_RD_REQ		BIT(5)
112 #define MSC_IREG_END_CMD_RES		BIT(2)
113 #define MSC_IREG_PRG_DONE		BIT(1)
114 #define MSC_IREG_DATA_TRAN_DONE		BIT(0)
115 
116 struct jz_mmc_plat {
117 	struct mmc_config cfg;
118 	struct mmc mmc;
119 };
120 
121 struct jz_mmc_priv {
122 	void __iomem		*regs;
123 	u32			flags;
124 /* priv flags */
125 #define JZ_MMC_BUS_WIDTH_MASK	0x3
126 #define JZ_MMC_BUS_WIDTH_1	0x0
127 #define JZ_MMC_BUS_WIDTH_4	0x2
128 #define JZ_MMC_BUS_WIDTH_8	0x3
129 #define JZ_MMC_SENT_INIT	BIT(2)
130 };
131 
jz_mmc_clock_rate(void)132 static int jz_mmc_clock_rate(void)
133 {
134 	return 24000000;
135 }
136 
137 #if CONFIG_IS_ENABLED(MMC_WRITE)
jz_mmc_write_data(struct jz_mmc_priv * priv,struct mmc_data * data)138 static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
139 {
140 	int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
141 	const void *buf = data->src;
142 
143 	while (sz--) {
144 		u32 val = get_unaligned_le32(buf);
145 
146 		wait_for_bit_le32(priv->regs + MSC_IREG,
147 				  MSC_IREG_TXFIFO_WR_REQ,
148 				  true, 10000, false);
149 		writel(val, priv->regs + MSC_TXFIFO);
150 		buf += 4;
151 	}
152 }
153 #else
jz_mmc_write_data(struct jz_mmc_priv * priv,struct mmc_data * data)154 static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
155 {}
156 #endif
157 
jz_mmc_read_data(struct jz_mmc_priv * priv,struct mmc_data * data)158 static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
159 {
160 	int sz = data->blocks * data->blocksize;
161 	void *buf = data->dest;
162 	u32 stat, val;
163 
164 	do {
165 		stat = readl(priv->regs + MSC_STAT);
166 
167 		if (stat & MSC_STAT_TIME_OUT_READ)
168 			return -ETIMEDOUT;
169 		if (stat & MSC_STAT_CRC_READ_ERROR)
170 			return -EINVAL;
171 		if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
172 			udelay(10);
173 			continue;
174 		}
175 		do {
176 			val = readl(priv->regs + MSC_RXFIFO);
177 			if (sz == 1)
178 				*(u8 *)buf = (u8)val;
179 			else if (sz == 2)
180 				put_unaligned_le16(val, buf);
181 			else if (sz >= 4)
182 				put_unaligned_le32(val, buf);
183 			buf += 4;
184 			sz -= 4;
185 			stat = readl(priv->regs + MSC_STAT);
186 		} while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
187 	} while (!(stat & MSC_STAT_DATA_TRAN_DONE));
188 	return 0;
189 }
190 
jz_mmc_send_cmd(struct mmc * mmc,struct jz_mmc_priv * priv,struct mmc_cmd * cmd,struct mmc_data * data)191 static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
192 			   struct mmc_cmd *cmd, struct mmc_data *data)
193 {
194 	u32 stat, mask, cmdat = 0;
195 	int i, ret;
196 
197 	/* stop the clock */
198 	writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
199 	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
200 				MSC_STAT_CLK_EN, false, 10000, false);
201 	if (ret)
202 		return ret;
203 
204 	writel(0, priv->regs + MSC_DMAC);
205 
206 	/* setup command */
207 	writel(cmd->cmdidx, priv->regs + MSC_CMD);
208 	writel(cmd->cmdarg, priv->regs + MSC_ARG);
209 
210 	if (data) {
211 		/* setup data */
212 		cmdat |= MSC_CMDAT_DATA_EN;
213 		if (data->flags & MMC_DATA_WRITE)
214 			cmdat |= MSC_CMDAT_WRITE;
215 
216 		writel(data->blocks, priv->regs + MSC_NOB);
217 		writel(data->blocksize, priv->regs + MSC_BLKLEN);
218 	} else {
219 		writel(0, priv->regs + MSC_NOB);
220 		writel(0, priv->regs + MSC_BLKLEN);
221 	}
222 
223 	/* setup response */
224 	switch (cmd->resp_type) {
225 	case MMC_RSP_NONE:
226 		break;
227 	case MMC_RSP_R1:
228 	case MMC_RSP_R1b:
229 		cmdat |= MSC_CMDAT_RESPONSE_R1;
230 		break;
231 	case MMC_RSP_R2:
232 		cmdat |= MSC_CMDAT_RESPONSE_R2;
233 		break;
234 	case MMC_RSP_R3:
235 		cmdat |= MSC_CMDAT_RESPONSE_R3;
236 		break;
237 	default:
238 		break;
239 	}
240 
241 	if (cmd->resp_type & MMC_RSP_BUSY)
242 		cmdat |= MSC_CMDAT_BUSY;
243 
244 	/* set init for the first command only */
245 	if (!(priv->flags & JZ_MMC_SENT_INIT)) {
246 		cmdat |= MSC_CMDAT_INIT;
247 		priv->flags |= JZ_MMC_SENT_INIT;
248 	}
249 
250 	cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
251 
252 	/* write the data setup */
253 	writel(cmdat, priv->regs + MSC_CMDAT);
254 
255 	/* unmask interrupts */
256 	mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
257 	if (data) {
258 		mask &= ~MSC_IMASK_DATA_TRAN_DONE;
259 		if (data->flags & MMC_DATA_WRITE) {
260 			mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
261 		} else {
262 			mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
263 				  MSC_IMASK_TIME_OUT_READ);
264 		}
265 	}
266 	writel(mask, priv->regs + MSC_IMASK);
267 
268 	/* clear interrupts */
269 	writel(0xffffffff, priv->regs + MSC_IREG);
270 
271 	/* start the command (& the clock) */
272 	writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
273 	       priv->regs + MSC_STRPCL);
274 
275 	/* wait for completion */
276 	for (i = 0; i < 100; i++) {
277 		stat = readl(priv->regs + MSC_IREG);
278 		stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
279 		if (stat)
280 			break;
281 		mdelay(1);
282 	}
283 	writel(stat, priv->regs + MSC_IREG);
284 	if (stat & MSC_IREG_TIME_OUT_RES)
285 		return -ETIMEDOUT;
286 
287 	if (cmd->resp_type & MMC_RSP_PRESENT) {
288 		/* read the response */
289 		if (cmd->resp_type & MMC_RSP_136) {
290 			u16 a, b, c, i;
291 
292 			a = readw(priv->regs + MSC_RES);
293 			for (i = 0; i < 4; i++) {
294 				b = readw(priv->regs + MSC_RES);
295 				c = readw(priv->regs + MSC_RES);
296 				cmd->response[i] =
297 					(a << 24) | (b << 8) | (c >> 8);
298 				a = c;
299 			}
300 		} else {
301 			cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
302 			cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
303 			cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
304 		}
305 	}
306 	if (data) {
307 		if (data->flags & MMC_DATA_WRITE)
308 			jz_mmc_write_data(priv, data);
309 		else if (data->flags & MMC_DATA_READ) {
310 			ret = jz_mmc_read_data(priv, data);
311 			if (ret)
312 				return ret;
313 		}
314 	}
315 
316 	return 0;
317 }
318 
jz_mmc_set_ios(struct mmc * mmc,struct jz_mmc_priv * priv)319 static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
320 {
321 	u32 real_rate = jz_mmc_clock_rate();
322 	u8 clk_div = 0;
323 
324 	/* calculate clock divide */
325 	while ((real_rate > mmc->clock) && (clk_div < 7)) {
326 		real_rate >>= 1;
327 		clk_div++;
328 	}
329 	writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
330 
331 	/* set the bus width for the next command */
332 	priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
333 	if (mmc->bus_width == 8)
334 		priv->flags |= JZ_MMC_BUS_WIDTH_8;
335 	else if (mmc->bus_width == 4)
336 		priv->flags |= JZ_MMC_BUS_WIDTH_4;
337 	else
338 		priv->flags |= JZ_MMC_BUS_WIDTH_1;
339 
340 	return 0;
341 }
342 
jz_mmc_core_init(struct mmc * mmc)343 static int jz_mmc_core_init(struct mmc *mmc)
344 {
345 	struct jz_mmc_priv *priv = mmc->priv;
346 	int ret;
347 
348 	/* Reset */
349 	writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
350 	ret = wait_for_bit_le32(priv->regs + MSC_STAT,
351 				MSC_STAT_IS_RESETTING, false, 10000, false);
352 	if (ret)
353 		return ret;
354 
355 	/* Maximum timeouts */
356 	writel(0xffff, priv->regs + MSC_RESTO);
357 	writel(0xffffffff, priv->regs + MSC_RDTO);
358 
359 	/* Enable low power mode */
360 	writel(0x1, priv->regs + MSC_LPM);
361 
362 	return 0;
363 }
364 
365 #if !CONFIG_IS_ENABLED(DM_MMC)
366 
jz_mmc_legacy_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)367 static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
368 				  struct mmc_data *data)
369 {
370 	struct jz_mmc_priv *priv = mmc->priv;
371 
372 	return jz_mmc_send_cmd(mmc, priv, cmd, data);
373 }
374 
jz_mmc_legacy_set_ios(struct mmc * mmc)375 static int jz_mmc_legacy_set_ios(struct mmc *mmc)
376 {
377 	struct jz_mmc_priv *priv = mmc->priv;
378 
379 	return jz_mmc_set_ios(mmc, priv);
380 };
381 
382 static const struct mmc_ops jz_msc_ops = {
383 	.send_cmd	= jz_mmc_legacy_send_cmd,
384 	.set_ios	= jz_mmc_legacy_set_ios,
385 	.init		= jz_mmc_core_init,
386 };
387 
388 static struct jz_mmc_priv jz_mmc_priv_static;
389 static struct jz_mmc_plat jz_mmc_plat_static = {
390 	.cfg = {
391 		.name = "MSC",
392 		.ops = &jz_msc_ops,
393 
394 		.voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
395 			    MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
396 			    MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
397 		.host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
398 
399 		.f_min = 375000,
400 		.f_max = 48000000,
401 		.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
402 	},
403 };
404 
jz_mmc_init(void __iomem * base)405 int jz_mmc_init(void __iomem *base)
406 {
407 	struct mmc *mmc;
408 
409 	jz_mmc_priv_static.regs = base;
410 
411 	mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
412 
413 	return mmc ? 0 : -ENODEV;
414 }
415 
416 #else /* CONFIG_DM_MMC */
417 
418 #include <dm.h>
419 DECLARE_GLOBAL_DATA_PTR;
420 
jz_mmc_dm_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)421 static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
422 			      struct mmc_data *data)
423 {
424 	struct jz_mmc_priv *priv = dev_get_priv(dev);
425 	struct mmc *mmc = mmc_get_mmc_dev(dev);
426 
427 	return jz_mmc_send_cmd(mmc, priv, cmd, data);
428 }
429 
jz_mmc_dm_set_ios(struct udevice * dev)430 static int jz_mmc_dm_set_ios(struct udevice *dev)
431 {
432 	struct jz_mmc_priv *priv = dev_get_priv(dev);
433 	struct mmc *mmc = mmc_get_mmc_dev(dev);
434 
435 	return jz_mmc_set_ios(mmc, priv);
436 };
437 
438 static const struct dm_mmc_ops jz_msc_ops = {
439 	.send_cmd	= jz_mmc_dm_send_cmd,
440 	.set_ios	= jz_mmc_dm_set_ios,
441 };
442 
jz_mmc_ofdata_to_platdata(struct udevice * dev)443 static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
444 {
445 	struct jz_mmc_priv *priv = dev_get_priv(dev);
446 	struct jz_mmc_plat *plat = dev_get_platdata(dev);
447 	struct mmc_config *cfg;
448 	int ret;
449 
450 	priv->regs = map_physmem(devfdt_get_addr(dev), 0x100, MAP_NOCACHE);
451 	cfg = &plat->cfg;
452 
453 	cfg->name = "MSC";
454 	cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
455 
456 	ret = mmc_of_parse(dev, cfg);
457 	if (ret < 0) {
458 		dev_err(dev, "failed to parse host caps\n");
459 		return ret;
460 	}
461 
462 	cfg->f_min = 400000;
463 	cfg->f_max = 52000000;
464 
465 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
466 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
467 
468 	return 0;
469 }
470 
jz_mmc_bind(struct udevice * dev)471 static int jz_mmc_bind(struct udevice *dev)
472 {
473 	struct jz_mmc_plat *plat = dev_get_platdata(dev);
474 
475 	return mmc_bind(dev, &plat->mmc, &plat->cfg);
476 }
477 
jz_mmc_probe(struct udevice * dev)478 static int jz_mmc_probe(struct udevice *dev)
479 {
480 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
481 	struct jz_mmc_priv *priv = dev_get_priv(dev);
482 	struct jz_mmc_plat *plat = dev_get_platdata(dev);
483 
484 	plat->mmc.priv = priv;
485 	upriv->mmc = &plat->mmc;
486 	return jz_mmc_core_init(&plat->mmc);
487 }
488 
489 static const struct udevice_id jz_mmc_ids[] = {
490 	{ .compatible = "ingenic,jz4780-mmc" },
491 	{ }
492 };
493 
494 U_BOOT_DRIVER(jz_mmc_drv) = {
495 	.name			= "jz_mmc",
496 	.id			= UCLASS_MMC,
497 	.of_match		= jz_mmc_ids,
498 	.ofdata_to_platdata	= jz_mmc_ofdata_to_platdata,
499 	.bind			= jz_mmc_bind,
500 	.probe			= jz_mmc_probe,
501 	.priv_auto_alloc_size	= sizeof(struct jz_mmc_priv),
502 	.platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
503 	.ops			= &jz_msc_ops,
504 };
505 #endif /* CONFIG_DM_MMC */
506