xref: /openbmc/qemu/hw/scsi/mptsas.h (revision edf5ca5d)
1 #ifndef MPTSAS_H
2 #define MPTSAS_H
3 
4 #include "mpi.h"
5 #include "hw/pci/pci_device.h"
6 
7 #define MPTSAS_NUM_PORTS 8
8 #define MPTSAS_MAX_FRAMES 2048     /* Firmware limit at 65535 */
9 
10 #define MPTSAS_REQUEST_QUEUE_DEPTH 128
11 #define MPTSAS_REPLY_QUEUE_DEPTH   128
12 
13 #define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22
14 
15 typedef struct MPTSASRequest MPTSASRequest;
16 
17 #define TYPE_MPTSAS1068 "mptsas1068"
18 typedef struct MPTSASState MPTSASState;
19 DECLARE_INSTANCE_CHECKER(MPTSASState, MPT_SAS,
20                          TYPE_MPTSAS1068)
21 
22 enum {
23     DOORBELL_NONE,
24     DOORBELL_WRITE,
25     DOORBELL_READ
26 };
27 
28 struct MPTSASState {
29     PCIDevice dev;
30     MemoryRegion mmio_io;
31     MemoryRegion port_io;
32     MemoryRegion diag_io;
33     QEMUBH *request_bh;
34 
35     /* properties */
36     OnOffAuto msi;
37     uint64_t sas_addr;
38 
39     bool msi_in_use;
40 
41     /* Doorbell register */
42     uint32_t state;
43     uint8_t who_init;
44     uint8_t doorbell_state;
45 
46     /* Buffer for requests that are sent through the doorbell register.  */
47     uint32_t doorbell_msg[256];
48     int doorbell_idx;
49     int doorbell_cnt;
50 
51     uint16_t doorbell_reply[256];
52     int doorbell_reply_idx;
53     int doorbell_reply_size;
54 
55     /* Other registers */
56     uint8_t diagnostic_idx;
57     uint32_t diagnostic;
58     uint32_t intr_mask;
59     uint32_t intr_status;
60 
61     /* Request queues */
62     uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1];
63     uint16_t request_post_head;
64     uint16_t request_post_tail;
65 
66     uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1];
67     uint16_t reply_post_head;
68     uint16_t reply_post_tail;
69 
70     uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1];
71     uint16_t reply_free_head;
72     uint16_t reply_free_tail;
73 
74     /* IOC Facts */
75     hwaddr host_mfa_high_addr;
76     hwaddr sense_buffer_high_addr;
77     uint16_t max_devices;
78     uint16_t max_buses;
79     uint16_t reply_frame_size;
80 
81     SCSIBus bus;
82 };
83 
84 void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req);
85 void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply);
86 void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req);
87 void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply);
88 void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req);
89 void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply);
90 void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req);
91 void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply);
92 void mptsas_fix_config_endianness(MPIMsgConfig *req);
93 void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply);
94 void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req);
95 void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply);
96 void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req);
97 void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply);
98 void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req);
99 void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply);
100 
101 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply);
102 
103 void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req);
104 
105 #endif /* MPTSAS_H */
106