1 /*
2 * QEMU PowerPC e500-based platforms
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include "qemu/osdep.h"
18 #include "qemu/datadir.h"
19 #include "qemu/units.h"
20 #include "qemu/guest-random.h"
21 #include "exec/target_page.h"
22 #include "qapi/error.h"
23 #include "cpu-models.h"
24 #include "e500.h"
25 #include "e500-ccsr.h"
26 #include "net/net.h"
27 #include "qemu/config-file.h"
28 #include "hw/block/flash.h"
29 #include "hw/char/serial-mm.h"
30 #include "hw/pci/pci.h"
31 #include "system/block-backend-io.h"
32 #include "system/system.h"
33 #include "system/kvm.h"
34 #include "system/reset.h"
35 #include "system/runstate.h"
36 #include "kvm_ppc.h"
37 #include "system/device_tree.h"
38 #include "hw/ppc/openpic.h"
39 #include "hw/ppc/openpic_kvm.h"
40 #include "hw/ppc/ppc.h"
41 #include "hw/qdev-properties.h"
42 #include "hw/loader.h"
43 #include "elf.h"
44 #include "hw/sysbus.h"
45 #include "qemu/host-utils.h"
46 #include "qemu/option.h"
47 #include "hw/pci-host/ppce500.h"
48 #include "qemu/error-report.h"
49 #include "hw/platform-bus.h"
50 #include "hw/net/fsl_etsec/etsec.h"
51 #include "hw/i2c/i2c.h"
52 #include "hw/irq.h"
53 #include "hw/sd/sdhci.h"
54 #include "hw/misc/unimp.h"
55
56 #define EPAPR_MAGIC (0x45504150)
57 #define DTC_LOAD_PAD 0x1800000
58 #define DTC_PAD_MASK 0xFFFFF
59 #define DTB_MAX_SIZE (8 * MiB)
60 #define INITRD_LOAD_PAD 0x2000000
61 #define INITRD_PAD_MASK 0xFFFFFF
62
63 #define RAM_SIZES_ALIGN (64 * MiB)
64
65 /* TODO: parameterize */
66 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
67 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
68 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
69 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
70 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
71 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
72 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
73 #define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
74 #define MPC85XX_ESDHC_REGS_SIZE 0x1000ULL
75 #define MPC8544_UTIL_OFFSET 0xe0000ULL
76 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
77 #define MPC8544_I2C_REGS_OFFSET 0x3000ULL
78 #define MPC8XXX_GPIO_IRQ 47
79 #define MPC8544_I2C_IRQ 43
80 #define MPC85XX_ESDHC_IRQ 72
81 #define RTC_REGS_OFFSET 0x68
82
83 struct boot_info
84 {
85 uint32_t dt_base;
86 uint32_t dt_size;
87 uint32_t entry;
88 };
89
pci_map_create(void * fdt,uint32_t mpic,int first_slot,int nr_slots,int * len)90 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
91 int nr_slots, int *len)
92 {
93 int i = 0;
94 int slot;
95 int pci_irq;
96 int host_irq;
97 int last_slot = first_slot + nr_slots;
98 uint32_t *pci_map;
99
100 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
101 pci_map = g_malloc(*len);
102
103 for (slot = first_slot; slot < last_slot; slot++) {
104 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
105 pci_map[i++] = cpu_to_be32(slot << 11);
106 pci_map[i++] = cpu_to_be32(0x0);
107 pci_map[i++] = cpu_to_be32(0x0);
108 pci_map[i++] = cpu_to_be32(pci_irq + 1);
109 pci_map[i++] = cpu_to_be32(mpic);
110 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
111 pci_map[i++] = cpu_to_be32(host_irq + 1);
112 pci_map[i++] = cpu_to_be32(0x1);
113 }
114 }
115
116 assert((i * sizeof(uint32_t)) == *len);
117
118 return pci_map;
119 }
120
dt_serial_create(void * fdt,unsigned long long offset,const char * soc,uint32_t freq,const char * mpic,const char * alias,int idx,bool defcon)121 static void dt_serial_create(void *fdt, unsigned long long offset,
122 const char *soc, uint32_t freq, const char *mpic,
123 const char *alias, int idx, bool defcon)
124 {
125 char *ser;
126
127 ser = g_strdup_printf("%s/serial@%llx", soc, offset);
128 qemu_fdt_add_subnode(fdt, ser);
129 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
130 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
131 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
132 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
133 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", freq);
134 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
135 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
136 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
137
138 if (defcon) {
139 /*
140 * "linux,stdout-path" and "stdout" properties are deprecated by linux
141 * kernel. New platforms should only use the "stdout-path" property. Set
142 * the new property and continue using older property to remain
143 * compatible with the existing firmware.
144 */
145 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
146 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", ser);
147 }
148 g_free(ser);
149 }
150
create_dt_mpc8xxx_gpio(void * fdt,const char * soc,const char * mpic)151 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
152 {
153 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
154 int irq0 = MPC8XXX_GPIO_IRQ;
155 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
156 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
157 int gpio_ph;
158
159 qemu_fdt_add_subnode(fdt, node);
160 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
161 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
162 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
163 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
164 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
165 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
166 gpio_ph = qemu_fdt_alloc_phandle(fdt);
167 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
168 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
169
170 /* Power Off Pin */
171 qemu_fdt_add_subnode(fdt, poweroff);
172 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
173 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
174
175 g_free(node);
176 g_free(poweroff);
177 }
178
dt_rtc_create(void * fdt,const char * i2c,const char * alias)179 static void dt_rtc_create(void *fdt, const char *i2c, const char *alias)
180 {
181 int offset = RTC_REGS_OFFSET;
182
183 gchar *rtc = g_strdup_printf("%s/rtc@%"PRIx32, i2c, offset);
184 qemu_fdt_add_subnode(fdt, rtc);
185 qemu_fdt_setprop_string(fdt, rtc, "compatible", "pericom,pt7c4338");
186 qemu_fdt_setprop_cells(fdt, rtc, "reg", offset);
187 qemu_fdt_setprop_string(fdt, "/aliases", alias, rtc);
188
189 g_free(rtc);
190 }
191
dt_i2c_create(void * fdt,const char * soc,const char * mpic,const char * alias)192 static void dt_i2c_create(void *fdt, const char *soc, const char *mpic,
193 const char *alias)
194 {
195 hwaddr mmio0 = MPC8544_I2C_REGS_OFFSET;
196 int irq0 = MPC8544_I2C_IRQ;
197
198 gchar *i2c = g_strdup_printf("%s/i2c@%"PRIx64, soc, mmio0);
199 qemu_fdt_add_subnode(fdt, i2c);
200 qemu_fdt_setprop_string(fdt, i2c, "device_type", "i2c");
201 qemu_fdt_setprop_string(fdt, i2c, "compatible", "fsl-i2c");
202 qemu_fdt_setprop_cells(fdt, i2c, "reg", mmio0, 0x14);
203 qemu_fdt_setprop_cells(fdt, i2c, "cell-index", 0);
204 qemu_fdt_setprop_cells(fdt, i2c, "interrupts", irq0, 0x2);
205 qemu_fdt_setprop_phandle(fdt, i2c, "interrupt-parent", mpic);
206 qemu_fdt_setprop_cell(fdt, i2c, "#size-cells", 0);
207 qemu_fdt_setprop_cell(fdt, i2c, "#address-cells", 1);
208 qemu_fdt_setprop_string(fdt, "/aliases", alias, i2c);
209
210 g_free(i2c);
211 }
212
dt_sdhc_create(void * fdt,const char * parent,const char * mpic)213 static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
214 {
215 hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
216 hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
217 int irq = MPC85XX_ESDHC_IRQ;
218 g_autofree char *name = NULL;
219
220 name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
221 qemu_fdt_add_subnode(fdt, name);
222 qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
223 qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
224 qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
225 qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
226 qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
227 qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
228 }
229
230 typedef struct PlatformDevtreeData {
231 void *fdt;
232 const char *mpic;
233 int irq_start;
234 const char *node;
235 PlatformBusDevice *pbus;
236 } PlatformDevtreeData;
237
create_devtree_etsec(SysBusDevice * sbdev,PlatformDevtreeData * data)238 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
239 {
240 eTSEC *etsec = ETSEC_COMMON(sbdev);
241 PlatformBusDevice *pbus = data->pbus;
242 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
243 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
244 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
245 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
246 gchar *node = g_strdup_printf("%s/ethernet@%"PRIx64, data->node, mmio0);
247 gchar *group = g_strdup_printf("%s/queue-group", node);
248 void *fdt = data->fdt;
249
250 assert((int64_t)mmio0 >= 0);
251 assert(irq0 >= 0);
252 assert(irq1 >= 0);
253 assert(irq2 >= 0);
254
255 qemu_fdt_add_subnode(fdt, node);
256 qemu_fdt_setprop(fdt, node, "ranges", NULL, 0);
257 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
258 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
259 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
260 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
261 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
262 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
263 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
264
265 qemu_fdt_add_subnode(fdt, group);
266 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
267 qemu_fdt_setprop_cells(fdt, group, "interrupts",
268 data->irq_start + irq0, 0x2,
269 data->irq_start + irq1, 0x2,
270 data->irq_start + irq2, 0x2);
271
272 g_free(node);
273 g_free(group);
274
275 return 0;
276 }
277
sysbus_device_create_devtree(SysBusDevice * sbdev,void * opaque)278 static void sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
279 {
280 PlatformDevtreeData *data = opaque;
281 bool matched = false;
282
283 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
284 create_devtree_etsec(sbdev, data);
285 matched = true;
286 }
287
288 if (!matched) {
289 error_report("Device %s is not supported by this machine yet.",
290 qdev_fw_name(DEVICE(sbdev)));
291 exit(1);
292 }
293 }
294
create_devtree_flash(SysBusDevice * sbdev,PlatformDevtreeData * data)295 static void create_devtree_flash(SysBusDevice *sbdev,
296 PlatformDevtreeData *data)
297 {
298 g_autofree char *name = NULL;
299 uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
300 "num-blocks",
301 &error_fatal);
302 uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
303 "sector-length",
304 &error_fatal);
305 uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
306 "width",
307 &error_fatal);
308 hwaddr flashbase = 0;
309 hwaddr flashsize = num_blocks * sector_length;
310 void *fdt = data->fdt;
311
312 name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
313 qemu_fdt_add_subnode(fdt, name);
314 qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
315 qemu_fdt_setprop_sized_cells(fdt, name, "reg",
316 1, flashbase, 1, flashsize);
317 qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
318 }
319
platform_bus_create_devtree(PPCE500MachineState * pms,void * fdt,const char * mpic)320 static void platform_bus_create_devtree(PPCE500MachineState *pms,
321 void *fdt, const char *mpic)
322 {
323 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
324 gchar *node = g_strdup_printf("/platform@%"PRIx64, pmc->platform_bus_base);
325 const char platcomp[] = "qemu,platform\0simple-bus";
326 uint64_t addr = pmc->platform_bus_base;
327 uint64_t size = pmc->platform_bus_size;
328 int irq_start = pmc->platform_bus_first_irq;
329 SysBusDevice *sbdev;
330 bool ambiguous;
331
332 /* Create a /platform node that we can put all devices into */
333
334 qemu_fdt_add_subnode(fdt, node);
335 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
336
337 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
338 address and size */
339 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
340 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
341 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
342
343 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
344
345 /* Create dt nodes for dynamic devices */
346 PlatformDevtreeData data = {
347 .fdt = fdt,
348 .mpic = mpic,
349 .irq_start = irq_start,
350 .node = node,
351 .pbus = pms->pbus_dev,
352 };
353
354 /* Loop through all dynamic sysbus devices and create nodes for them */
355 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
356
357 sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
358 &ambiguous));
359 if (sbdev) {
360 assert(!ambiguous);
361 create_devtree_flash(sbdev, &data);
362 }
363
364 g_free(node);
365 }
366
ppce500_load_device_tree(PPCE500MachineState * pms,hwaddr addr,hwaddr initrd_base,hwaddr initrd_size,hwaddr kernel_base,hwaddr kernel_size,bool dry_run)367 static int ppce500_load_device_tree(PPCE500MachineState *pms,
368 hwaddr addr,
369 hwaddr initrd_base,
370 hwaddr initrd_size,
371 hwaddr kernel_base,
372 hwaddr kernel_size,
373 bool dry_run)
374 {
375 MachineState *machine = MACHINE(pms);
376 unsigned int smp_cpus = machine->smp.cpus;
377 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
378 CPUPPCState *env = cpu_env(first_cpu);
379 int ret = -1;
380 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
381 int fdt_size;
382 void *fdt;
383 uint8_t hypercall[16];
384 uint32_t clock_freq, tb_freq;
385 int i;
386 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
387 char *soc;
388 char *mpic;
389 uint32_t mpic_ph;
390 uint32_t msi_ph;
391 char *gutil;
392 char *pci;
393 char *msi;
394 uint32_t *pci_map = NULL;
395 int len;
396 uint32_t pci_ranges[14] =
397 {
398 0x2000000, 0x0, pmc->pci_mmio_bus_base,
399 pmc->pci_mmio_base >> 32, pmc->pci_mmio_base,
400 0x0, 0x20000000,
401
402 0x1000000, 0x0, 0x0,
403 pmc->pci_pio_base >> 32, pmc->pci_pio_base,
404 0x0, 0x10000,
405 };
406 const char *dtb_file = machine->dtb;
407 const char *toplevel_compat = machine->dt_compatible;
408 uint8_t rng_seed[32];
409
410 if (dtb_file) {
411 char *filename;
412 filename = qemu_find_file(QEMU_FILE_TYPE_DTB, dtb_file);
413 if (!filename) {
414 goto out;
415 }
416
417 fdt = load_device_tree(filename, &fdt_size);
418 g_free(filename);
419 if (!fdt) {
420 goto out;
421 }
422 goto done;
423 }
424
425 fdt = create_device_tree(&fdt_size);
426 if (fdt == NULL) {
427 goto out;
428 }
429
430 /* Manipulate device tree in memory. */
431 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
432 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
433
434 qemu_fdt_add_subnode(fdt, "/memory");
435 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
436 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
437 sizeof(mem_reg_property));
438
439 qemu_fdt_add_subnode(fdt, "/chosen");
440 if (initrd_size) {
441 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
442 initrd_base);
443 if (ret < 0) {
444 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
445 }
446
447 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
448 (initrd_base + initrd_size));
449 if (ret < 0) {
450 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
451 }
452
453 }
454
455 if (kernel_base != -1ULL) {
456 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
457 kernel_base >> 32, kernel_base,
458 kernel_size >> 32, kernel_size);
459 }
460
461 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
462 machine->kernel_cmdline);
463 if (ret < 0)
464 fprintf(stderr, "couldn't set /chosen/bootargs\n");
465
466 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
467 qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
468
469 if (kvm_enabled()) {
470 /* Read out host's frequencies */
471 clock_freq = kvmppc_get_clockfreq();
472 tb_freq = kvmppc_get_tbfreq();
473
474 /* indicate KVM hypercall interface */
475 qemu_fdt_add_subnode(fdt, "/hypervisor");
476 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
477 "linux,kvm");
478 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
479 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
480 hypercall, sizeof(hypercall));
481 /* if KVM supports the idle hcall, set property indicating this */
482 if (kvmppc_get_hasidle(env)) {
483 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
484 }
485 } else {
486 clock_freq = pmc->clock_freq;
487 tb_freq = pmc->tb_freq;
488 }
489
490 /* Create CPU nodes */
491 qemu_fdt_add_subnode(fdt, "/cpus");
492 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
493 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
494
495 /* We need to generate the cpu nodes in reverse order, so Linux can pick
496 the first node as boot node and be happy */
497 for (i = smp_cpus - 1; i >= 0; i--) {
498 CPUState *cpu;
499 char *cpu_name;
500 uint64_t cpu_release_addr = pmc->spin_base + (i * 0x20);
501
502 cpu = qemu_get_cpu(i);
503 if (cpu == NULL) {
504 continue;
505 }
506 env = cpu_env(cpu);
507
508 cpu_name = g_strdup_printf("/cpus/PowerPC,8544@%x", i);
509 qemu_fdt_add_subnode(fdt, cpu_name);
510 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
511 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
512 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
513 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", i);
514 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
515 env->dcache_line_size);
516 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
517 env->icache_line_size);
518 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
519 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
520 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
521 if (cpu->cpu_index) {
522 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
523 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
524 "spin-table");
525 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
526 cpu_release_addr);
527 } else {
528 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
529 }
530 g_free(cpu_name);
531 }
532
533 qemu_fdt_add_subnode(fdt, "/aliases");
534 /* XXX These should go into their respective devices' code */
535 soc = g_strdup_printf("/soc@%"PRIx64, pmc->ccsrbar_base);
536 qemu_fdt_add_subnode(fdt, soc);
537 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
538 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
539 sizeof(compatible_sb));
540 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
541 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
542 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
543 pmc->ccsrbar_base >> 32, pmc->ccsrbar_base,
544 MPC8544_CCSRBAR_SIZE);
545 /* XXX should contain a reasonable value */
546 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
547
548 mpic = g_strdup_printf("%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
549 qemu_fdt_add_subnode(fdt, mpic);
550 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
551 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
552 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
553 0x40000);
554 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
555 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
556 mpic_ph = qemu_fdt_alloc_phandle(fdt);
557 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
558 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
559 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
560
561 /*
562 * We have to generate ser1 first, because Linux takes the first
563 * device it finds in the dt as serial output device. And we generate
564 * devices in reverse order to the dt.
565 */
566 if (serial_hd(1)) {
567 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
568 soc, pmc->clock_freq, mpic, "serial1", 1, false);
569 }
570
571 if (serial_hd(0)) {
572 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
573 soc, pmc->clock_freq, mpic, "serial0", 0, true);
574 }
575
576 /* i2c */
577 dt_i2c_create(fdt, soc, mpic, "i2c");
578
579 dt_rtc_create(fdt, "i2c", "rtc");
580
581 /* sdhc */
582 if (pmc->has_esdhc) {
583 dt_sdhc_create(fdt, soc, mpic);
584 }
585
586 gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
587 MPC8544_UTIL_OFFSET);
588 qemu_fdt_add_subnode(fdt, gutil);
589 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
590 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
591 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
592 g_free(gutil);
593
594 msi = g_strdup_printf("/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
595 qemu_fdt_add_subnode(fdt, msi);
596 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
597 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
598 msi_ph = qemu_fdt_alloc_phandle(fdt);
599 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
600 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
601 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
602 0xe0, 0x0,
603 0xe1, 0x0,
604 0xe2, 0x0,
605 0xe3, 0x0,
606 0xe4, 0x0,
607 0xe5, 0x0,
608 0xe6, 0x0,
609 0xe7, 0x0);
610 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
611 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
612 g_free(msi);
613
614 pci = g_strdup_printf("/pci@%llx",
615 pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET);
616 qemu_fdt_add_subnode(fdt, pci);
617 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
618 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
619 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
620 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
621 0x0, 0x7);
622 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
623 pmc->pci_first_slot, pmc->pci_nr_slots,
624 &len);
625 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
626 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
627 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
628 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
629 for (i = 0; i < 14; i++) {
630 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
631 }
632 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
633 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
634 qemu_fdt_setprop_cells(fdt, pci, "reg",
635 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET) >> 32,
636 (pmc->ccsrbar_base + MPC8544_PCI_REGS_OFFSET),
637 0, 0x1000);
638 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
639 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
640 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
641 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
642 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
643 g_free(pci);
644
645 if (pmc->has_mpc8xxx_gpio) {
646 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
647 }
648 g_free(soc);
649
650 platform_bus_create_devtree(pms, fdt, mpic);
651
652 g_free(mpic);
653
654 pmc->fixup_devtree(fdt);
655
656 if (toplevel_compat) {
657 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
658 strlen(toplevel_compat) + 1);
659 }
660
661 done:
662 if (!dry_run) {
663 cpu_physical_memory_write(addr, fdt, fdt_size);
664
665 /* Set machine->fdt for 'dumpdtb' QMP/HMP command */
666 g_free(machine->fdt);
667 machine->fdt = fdt;
668 } else {
669 g_free(fdt);
670 }
671 ret = fdt_size;
672
673 out:
674 g_free(pci_map);
675
676 return ret;
677 }
678
679 typedef struct DeviceTreeParams {
680 PPCE500MachineState *machine;
681 hwaddr addr;
682 hwaddr initrd_base;
683 hwaddr initrd_size;
684 hwaddr kernel_base;
685 hwaddr kernel_size;
686 Notifier notifier;
687 } DeviceTreeParams;
688
ppce500_reset_device_tree(void * opaque)689 static void ppce500_reset_device_tree(void *opaque)
690 {
691 DeviceTreeParams *p = opaque;
692 ppce500_load_device_tree(p->machine, p->addr, p->initrd_base,
693 p->initrd_size, p->kernel_base, p->kernel_size,
694 false);
695 }
696
ppce500_init_notify(Notifier * notifier,void * data)697 static void ppce500_init_notify(Notifier *notifier, void *data)
698 {
699 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
700 ppce500_reset_device_tree(p);
701 }
702
ppce500_prep_device_tree(PPCE500MachineState * machine,hwaddr addr,hwaddr initrd_base,hwaddr initrd_size,hwaddr kernel_base,hwaddr kernel_size)703 static int ppce500_prep_device_tree(PPCE500MachineState *machine,
704 hwaddr addr,
705 hwaddr initrd_base,
706 hwaddr initrd_size,
707 hwaddr kernel_base,
708 hwaddr kernel_size)
709 {
710 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
711 p->machine = machine;
712 p->addr = addr;
713 p->initrd_base = initrd_base;
714 p->initrd_size = initrd_size;
715 p->kernel_base = kernel_base;
716 p->kernel_size = kernel_size;
717
718 qemu_register_reset_nosnapshotload(ppce500_reset_device_tree, p);
719 p->notifier.notify = ppce500_init_notify;
720 qemu_add_machine_init_done_notifier(&p->notifier);
721
722 /* Issue the device tree loader once, so that we get the size of the blob */
723 return ppce500_load_device_tree(machine, addr, initrd_base, initrd_size,
724 kernel_base, kernel_size, true);
725 }
726
booke206_page_size_to_tlb(uint64_t size)727 static hwaddr booke206_page_size_to_tlb(uint64_t size)
728 {
729 return 63 - clz64(size / KiB);
730 }
731
booke206_set_tlb(ppcmas_tlb_t * tlb,target_ulong va,hwaddr pa,hwaddr len)732 void booke206_set_tlb(ppcmas_tlb_t *tlb, target_ulong va, hwaddr pa,
733 hwaddr len)
734 {
735 tlb->mas1 = booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT;
736 tlb->mas1 |= MAS1_VALID;
737 tlb->mas2 = va & TARGET_PAGE_MASK;
738 tlb->mas7_3 = pa & TARGET_PAGE_MASK;
739 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
740 }
741
booke206_initial_map_tsize(CPUPPCState * env)742 static int booke206_initial_map_tsize(CPUPPCState *env)
743 {
744 struct boot_info *bi = env->load_info;
745 hwaddr dt_end;
746 int ps;
747
748 /* Our initial TLB entry needs to cover everything from 0 to
749 the device tree top */
750 dt_end = bi->dt_base + bi->dt_size;
751 ps = booke206_page_size_to_tlb(dt_end) + 1;
752 if (ps & 1) {
753 /* e500v2 can only do even TLB size bits */
754 ps++;
755 }
756 return ps;
757 }
758
mmubooke_initial_mapsize(CPUPPCState * env)759 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
760 {
761 int tsize;
762
763 tsize = booke206_initial_map_tsize(env);
764 return (1ULL << 10 << tsize);
765 }
766
ppce500_cpu_reset_sec(void * opaque)767 static void ppce500_cpu_reset_sec(void *opaque)
768 {
769 PowerPCCPU *cpu = opaque;
770 CPUState *cs = CPU(cpu);
771
772 cpu_reset(cs);
773
774 cs->exception_index = EXCP_HLT;
775 }
776
ppce500_cpu_reset(void * opaque)777 static void ppce500_cpu_reset(void *opaque)
778 {
779 PowerPCCPU *cpu = opaque;
780 CPUState *cs = CPU(cpu);
781 CPUPPCState *env = &cpu->env;
782 struct boot_info *bi = env->load_info;
783 uint64_t map_size = mmubooke_initial_mapsize(env);
784 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
785
786 cpu_reset(cs);
787
788 /* Set initial guest state. */
789 cs->halted = 0;
790 env->gpr[1] = (16 * MiB) - 8;
791 env->gpr[3] = bi->dt_base;
792 env->gpr[4] = 0;
793 env->gpr[5] = 0;
794 env->gpr[6] = EPAPR_MAGIC;
795 env->gpr[7] = map_size;
796 env->gpr[8] = 0;
797 env->gpr[9] = 0;
798 env->nip = bi->entry;
799 /* create initial mapping */
800 booke206_set_tlb(tlb, 0, 0, map_size);
801 #ifdef CONFIG_KVM
802 env->tlb_dirty = true;
803 #endif
804 }
805
ppce500_init_mpic_qemu(PPCE500MachineState * pms,IrqLines * irqs)806 static DeviceState *ppce500_init_mpic_qemu(PPCE500MachineState *pms,
807 IrqLines *irqs)
808 {
809 DeviceState *dev;
810 SysBusDevice *s;
811 int i, j, k;
812 MachineState *machine = MACHINE(pms);
813 unsigned int smp_cpus = machine->smp.cpus;
814 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
815
816 dev = qdev_new(TYPE_OPENPIC);
817 object_property_add_child(OBJECT(machine), "pic", OBJECT(dev));
818 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
819 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
820
821 s = SYS_BUS_DEVICE(dev);
822 sysbus_realize_and_unref(s, &error_fatal);
823
824 k = 0;
825 for (i = 0; i < smp_cpus; i++) {
826 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
827 sysbus_connect_irq(s, k++, irqs[i].irq[j]);
828 }
829 }
830
831 return dev;
832 }
833
ppce500_init_mpic_kvm(const PPCE500MachineClass * pmc,Error ** errp)834 static DeviceState *ppce500_init_mpic_kvm(const PPCE500MachineClass *pmc,
835 Error **errp)
836 {
837 #ifdef CONFIG_KVM
838 DeviceState *dev;
839 CPUState *cs;
840
841 dev = qdev_new(TYPE_KVM_OPENPIC);
842 qdev_prop_set_uint32(dev, "model", pmc->mpic_version);
843
844 if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
845 object_unparent(OBJECT(dev));
846 return NULL;
847 }
848
849 CPU_FOREACH(cs) {
850 if (kvm_openpic_connect_vcpu(dev, cs)) {
851 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
852 __func__);
853 abort();
854 }
855 }
856
857 return dev;
858 #else
859 g_assert_not_reached();
860 #endif
861 }
862
ppce500_init_mpic(PPCE500MachineState * pms,MemoryRegion * ccsr,IrqLines * irqs)863 static DeviceState *ppce500_init_mpic(PPCE500MachineState *pms,
864 MemoryRegion *ccsr,
865 IrqLines *irqs)
866 {
867 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(pms);
868 DeviceState *dev = NULL;
869 SysBusDevice *s;
870
871 if (kvm_enabled()) {
872 Error *err = NULL;
873
874 if (kvm_kernel_irqchip_allowed()) {
875 dev = ppce500_init_mpic_kvm(pmc, &err);
876 }
877 if (kvm_kernel_irqchip_required() && !dev) {
878 error_reportf_err(err,
879 "kernel_irqchip requested but unavailable: ");
880 exit(1);
881 }
882 }
883
884 if (!dev) {
885 dev = ppce500_init_mpic_qemu(pms, irqs);
886 }
887
888 s = SYS_BUS_DEVICE(dev);
889 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
890 s->mmio[0].memory);
891
892 return dev;
893 }
894
ppce500_power_off(void * opaque,int line,int on)895 static void ppce500_power_off(void *opaque, int line, int on)
896 {
897 if (on) {
898 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
899 }
900 }
901
ppce500_init(MachineState * machine)902 void ppce500_init(MachineState *machine)
903 {
904 MemoryRegion *address_space_mem = get_system_memory();
905 PPCE500MachineState *pms = PPCE500_MACHINE(machine);
906 const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine);
907 MachineClass *mc = MACHINE_CLASS(pmc);
908 PCIBus *pci_bus;
909 CPUPPCState *env = NULL;
910 uint64_t loadaddr;
911 hwaddr kernel_base = -1LL;
912 int kernel_size = 0;
913 hwaddr dt_base = 0;
914 hwaddr initrd_base = 0;
915 int initrd_size = 0;
916 hwaddr cur_base = 0;
917 char *filename;
918 const char *payload_name;
919 bool kernel_as_payload;
920 hwaddr bios_entry = 0;
921 target_long payload_size;
922 struct boot_info *boot_info = NULL;
923 int dt_size;
924 int i;
925 unsigned int smp_cpus = machine->smp.cpus;
926 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
927 * 4 respectively */
928 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
929 IrqLines *irqs;
930 DeviceState *dev, *mpicdev;
931 DriveInfo *dinfo;
932 CPUPPCState *firstenv = NULL;
933 MemoryRegion *ccsr_addr_space;
934 SysBusDevice *s;
935 I2CBus *i2c;
936
937 irqs = g_new0(IrqLines, smp_cpus);
938 for (i = 0; i < smp_cpus; i++) {
939 PowerPCCPU *cpu;
940 CPUState *cs;
941
942 cpu = POWERPC_CPU(object_new(machine->cpu_type));
943 env = &cpu->env;
944 cs = CPU(cpu);
945
946 if (!(POWERPC_CPU_GET_CLASS(cpu)->svr & POWERPC_SVR_E500)) {
947 error_report("This machine needs a CPU from the e500 family");
948 exit(1);
949 }
950
951 /*
952 * Secondary CPU starts in halted state for now. Needs to change
953 * when implementing non-kernel boot.
954 */
955 object_property_set_bool(OBJECT(cs), "start-powered-off", i != 0,
956 &error_abort);
957 qdev_realize_and_unref(DEVICE(cs), NULL, &error_fatal);
958
959 if (!firstenv) {
960 firstenv = env;
961 }
962
963 irqs[i].irq[OPENPIC_OUTPUT_INT] =
964 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_INT);
965 irqs[i].irq[OPENPIC_OUTPUT_CINT] =
966 qdev_get_gpio_in(DEVICE(cpu), PPCE500_INPUT_CINT);
967 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
968 env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
969
970 ppc_booke_timers_init(cpu, pmc->tb_freq, PPC_TIMER_E500);
971
972 /* Register reset handler */
973 if (!i) {
974 /* Primary CPU */
975 boot_info = g_new0(struct boot_info, 1);
976 qemu_register_reset(ppce500_cpu_reset, cpu);
977 env->load_info = boot_info;
978 } else {
979 /* Secondary CPUs */
980 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
981 }
982 }
983
984 env = firstenv;
985
986 if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) {
987 error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN);
988 exit(EXIT_FAILURE);
989 }
990
991 /* Register Memory */
992 memory_region_add_subregion(address_space_mem, 0, machine->ram);
993
994 dev = qdev_new("e500-ccsr");
995 s = SYS_BUS_DEVICE(dev);
996 object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
997 sysbus_realize_and_unref(s, &error_fatal);
998 ccsr_addr_space = sysbus_mmio_get_region(s, 0);
999 memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
1000 ccsr_addr_space);
1001
1002 mpicdev = ppce500_init_mpic(pms, ccsr_addr_space, irqs);
1003 g_free(irqs);
1004
1005 /* Serial */
1006 if (serial_hd(0)) {
1007 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
1008 0, qdev_get_gpio_in(mpicdev, 42), 399193,
1009 serial_hd(0), DEVICE_BIG_ENDIAN);
1010 }
1011
1012 if (serial_hd(1)) {
1013 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
1014 0, qdev_get_gpio_in(mpicdev, 42), 399193,
1015 serial_hd(1), DEVICE_BIG_ENDIAN);
1016 }
1017
1018 /* I2C */
1019 dev = qdev_new("mpc-i2c");
1020 s = SYS_BUS_DEVICE(dev);
1021 sysbus_realize_and_unref(s, &error_fatal);
1022 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8544_I2C_IRQ));
1023 memory_region_add_subregion(ccsr_addr_space, MPC8544_I2C_REGS_OFFSET,
1024 sysbus_mmio_get_region(s, 0));
1025 i2c = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
1026 i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
1027
1028 /* eSDHC */
1029 if (pmc->has_esdhc) {
1030 dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
1031 qdev_prop_set_string(dev, "name", "esdhc");
1032 qdev_prop_set_uint64(dev, "size", MPC85XX_ESDHC_REGS_SIZE);
1033 s = SYS_BUS_DEVICE(dev);
1034 sysbus_realize_and_unref(s, &error_fatal);
1035 memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
1036 sysbus_mmio_get_region(s, 0));
1037
1038 /*
1039 * Compatible with:
1040 * - SD Host Controller Specification Version 2.0 Part A2
1041 * (See MPC8569E Reference Manual)
1042 */
1043 dev = qdev_new(TYPE_SYSBUS_SDHCI);
1044 qdev_prop_set_uint8(dev, "sd-spec-version", 2);
1045 qdev_prop_set_uint8(dev, "endianness", DEVICE_BIG_ENDIAN);
1046 qdev_prop_set_uint8(dev, "vendor", SDHCI_VENDOR_FSL);
1047 s = SYS_BUS_DEVICE(dev);
1048 sysbus_realize_and_unref(s, &error_fatal);
1049 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
1050 memory_region_add_subregion(ccsr_addr_space, MPC85XX_ESDHC_REGS_OFFSET,
1051 sysbus_mmio_get_region(s, 0));
1052 }
1053
1054 /* General Utility device */
1055 dev = qdev_new("mpc8544-guts");
1056 s = SYS_BUS_DEVICE(dev);
1057 sysbus_realize_and_unref(s, &error_fatal);
1058 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
1059 sysbus_mmio_get_region(s, 0));
1060
1061 /* PCI */
1062 dev = qdev_new("e500-pcihost");
1063 object_property_add_child(OBJECT(machine), "pci-host", OBJECT(dev));
1064 qdev_prop_set_uint32(dev, "first_slot", pmc->pci_first_slot);
1065 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
1066 s = SYS_BUS_DEVICE(dev);
1067 sysbus_realize_and_unref(s, &error_fatal);
1068 for (i = 0; i < PCI_NUM_PINS; i++) {
1069 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, pci_irq_nrs[i]));
1070 }
1071
1072 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
1073 sysbus_mmio_get_region(s, 0));
1074
1075 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
1076 if (!pci_bus)
1077 printf("couldn't create PCI controller!\n");
1078
1079 if (pci_bus) {
1080 /* Register network interfaces. */
1081 pci_init_nic_devices(pci_bus, mc->default_nic);
1082 }
1083
1084 /* Register spinning region */
1085 sysbus_create_simple("e500-spin", pmc->spin_base, NULL);
1086
1087 if (pmc->has_mpc8xxx_gpio) {
1088 qemu_irq poweroff_irq;
1089
1090 dev = qdev_new("mpc8xxx_gpio");
1091 s = SYS_BUS_DEVICE(dev);
1092 sysbus_realize_and_unref(s, &error_fatal);
1093 sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC8XXX_GPIO_IRQ));
1094 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
1095 sysbus_mmio_get_region(s, 0));
1096
1097 /* Power Off GPIO at Pin 0 */
1098 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
1099 qdev_connect_gpio_out(dev, 0, poweroff_irq);
1100 }
1101
1102 /* Platform Bus Device */
1103 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1104 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1105 qdev_prop_set_uint32(dev, "num_irqs", pmc->platform_bus_num_irqs);
1106 qdev_prop_set_uint32(dev, "mmio_size", pmc->platform_bus_size);
1107 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1108 pms->pbus_dev = PLATFORM_BUS_DEVICE(dev);
1109
1110 s = SYS_BUS_DEVICE(pms->pbus_dev);
1111 for (i = 0; i < pmc->platform_bus_num_irqs; i++) {
1112 int irqn = pmc->platform_bus_first_irq + i;
1113 sysbus_connect_irq(s, i, qdev_get_gpio_in(mpicdev, irqn));
1114 }
1115
1116 memory_region_add_subregion(address_space_mem,
1117 pmc->platform_bus_base,
1118 &pms->pbus_dev->mmio);
1119
1120 dinfo = drive_get(IF_PFLASH, 0, 0);
1121 if (dinfo) {
1122 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
1123 BlockDriverState *bs = blk_bs(blk);
1124 uint64_t mmio_size = memory_region_size(&pms->pbus_dev->mmio);
1125 uint64_t size = bdrv_getlength(bs);
1126 uint32_t sector_len = 64 * KiB;
1127
1128 if (!is_power_of_2(size)) {
1129 error_report("Size of pflash file must be a power of two.");
1130 exit(1);
1131 }
1132
1133 if (size > mmio_size) {
1134 error_report("Size of pflash file must not be bigger than %" PRIu64
1135 " bytes.", mmio_size);
1136 exit(1);
1137 }
1138
1139 if (!QEMU_IS_ALIGNED(size, sector_len)) {
1140 error_report("Size of pflash file must be a multiple of %" PRIu32
1141 ".", sector_len);
1142 exit(1);
1143 }
1144
1145 dev = qdev_new(TYPE_PFLASH_CFI01);
1146 qdev_prop_set_drive(dev, "drive", blk);
1147 qdev_prop_set_uint32(dev, "num-blocks", size / sector_len);
1148 qdev_prop_set_uint64(dev, "sector-length", sector_len);
1149 qdev_prop_set_uint8(dev, "width", 2);
1150 qdev_prop_set_bit(dev, "big-endian", true);
1151 qdev_prop_set_uint16(dev, "id0", 0x89);
1152 qdev_prop_set_uint16(dev, "id1", 0x18);
1153 qdev_prop_set_uint16(dev, "id2", 0x0000);
1154 qdev_prop_set_uint16(dev, "id3", 0x0);
1155 qdev_prop_set_string(dev, "name", "e500.flash");
1156 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1157
1158 memory_region_add_subregion(&pms->pbus_dev->mmio, 0,
1159 pflash_cfi01_get_memory(PFLASH_CFI01(dev)));
1160 }
1161
1162 /*
1163 * Smart firmware defaults ahead!
1164 *
1165 * We follow the following table to select which payload we execute.
1166 *
1167 * -kernel | -bios | payload
1168 * ---------+-------+---------
1169 * N | Y | u-boot
1170 * N | N | u-boot
1171 * Y | Y | u-boot
1172 * Y | N | kernel
1173 *
1174 * This ensures backwards compatibility with how we used to expose
1175 * -kernel to users but allows them to run through u-boot as well.
1176 */
1177 kernel_as_payload = false;
1178 if (machine->firmware == NULL) {
1179 if (machine->kernel_filename) {
1180 payload_name = machine->kernel_filename;
1181 kernel_as_payload = true;
1182 } else {
1183 payload_name = "u-boot.e500";
1184 }
1185 } else {
1186 payload_name = machine->firmware;
1187 }
1188
1189 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, payload_name);
1190 if (!filename) {
1191 error_report("could not find firmware/kernel file '%s'", payload_name);
1192 exit(1);
1193 }
1194
1195 payload_size = load_elf(filename, NULL, NULL, NULL,
1196 &bios_entry, &loadaddr, NULL, NULL,
1197 ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
1198 if (payload_size < 0) {
1199 /*
1200 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1201 * ePAPR compliant kernel
1202 */
1203 loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
1204 payload_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1205 NULL, NULL);
1206 if (payload_size < 0) {
1207 error_report("could not load firmware '%s'", filename);
1208 exit(1);
1209 }
1210 }
1211
1212 g_free(filename);
1213
1214 if (kernel_as_payload) {
1215 kernel_base = loadaddr;
1216 kernel_size = payload_size;
1217 }
1218
1219 cur_base = loadaddr + payload_size;
1220 if (cur_base < 32 * MiB) {
1221 /* u-boot occupies memory up to 32MB, so load blobs above */
1222 cur_base = 32 * MiB;
1223 }
1224
1225 /* Load bare kernel only if no bios/u-boot has been provided */
1226 if (machine->kernel_filename && !kernel_as_payload) {
1227 kernel_base = cur_base;
1228 kernel_size = load_image_targphys(machine->kernel_filename,
1229 cur_base,
1230 machine->ram_size - cur_base);
1231 if (kernel_size < 0) {
1232 error_report("could not load kernel '%s'",
1233 machine->kernel_filename);
1234 exit(1);
1235 }
1236
1237 cur_base += kernel_size;
1238 }
1239
1240 /* Load initrd. */
1241 if (machine->initrd_filename) {
1242 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
1243 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
1244 machine->ram_size - initrd_base);
1245
1246 if (initrd_size < 0) {
1247 error_report("could not load initial ram disk '%s'",
1248 machine->initrd_filename);
1249 exit(1);
1250 }
1251
1252 cur_base = initrd_base + initrd_size;
1253 }
1254
1255 /*
1256 * Reserve space for dtb behind the kernel image because Linux has a bug
1257 * where it can only handle the dtb if it's within the first 64MB of where
1258 * <kernel> starts. dtb cannot not reach initrd_base because INITRD_LOAD_PAD
1259 * ensures enough space between kernel and initrd.
1260 */
1261 dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1262 if (dt_base + DTB_MAX_SIZE > machine->ram_size) {
1263 error_report("not enough memory for device tree");
1264 exit(1);
1265 }
1266
1267 dt_size = ppce500_prep_device_tree(pms, dt_base,
1268 initrd_base, initrd_size,
1269 kernel_base, kernel_size);
1270 if (dt_size < 0) {
1271 error_report("couldn't load device tree");
1272 exit(1);
1273 }
1274 assert(dt_size < DTB_MAX_SIZE);
1275
1276 boot_info->entry = bios_entry;
1277 boot_info->dt_base = dt_base;
1278 boot_info->dt_size = dt_size;
1279 }
1280
e500_ccsr_initfn(Object * obj)1281 static void e500_ccsr_initfn(Object *obj)
1282 {
1283 PPCE500CCSRState *ccsr = CCSR(obj);
1284 memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
1285 MPC8544_CCSRBAR_SIZE);
1286 sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space);
1287 }
1288
1289 static const TypeInfo e500_ccsr_info = {
1290 .name = TYPE_CCSR,
1291 .parent = TYPE_SYS_BUS_DEVICE,
1292 .instance_size = sizeof(PPCE500CCSRState),
1293 .instance_init = e500_ccsr_initfn,
1294 };
1295
1296 static const TypeInfo ppce500_info = {
1297 .name = TYPE_PPCE500_MACHINE,
1298 .parent = TYPE_MACHINE,
1299 .abstract = true,
1300 .instance_size = sizeof(PPCE500MachineState),
1301 .class_size = sizeof(PPCE500MachineClass),
1302 };
1303
e500_register_types(void)1304 static void e500_register_types(void)
1305 {
1306 type_register_static(&e500_ccsr_info);
1307 type_register_static(&ppce500_info);
1308 }
1309
1310 type_init(e500_register_types)
1311