1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 *
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 *
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
16 *
17 *
18 * TODO: orientation events
19 */
20
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
35
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_FF_MT_CHAN_SHIFT 3
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66 #define MMA8452_TRANSIENT_SRC 0x1e
67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70 #define MMA8452_TRANSIENT_THS 0x1f
71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72 #define MMA8452_TRANSIENT_COUNT 0x20
73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
74 #define MMA8452_CTRL_REG1 0x2a
75 #define MMA8452_CTRL_ACTIVE BIT(0)
76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77 #define MMA8452_CTRL_DR_SHIFT 3
78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
79 #define MMA8452_CTRL_REG2 0x2b
80 #define MMA8452_CTRL_REG2_RST BIT(6)
81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83 #define MMA8452_CTRL_REG4 0x2d
84 #define MMA8452_CTRL_REG5 0x2e
85 #define MMA8452_OFF_X 0x2f
86 #define MMA8452_OFF_Y 0x30
87 #define MMA8452_OFF_Z 0x31
88
89 #define MMA8452_MAX_REG 0x31
90
91 #define MMA8452_INT_DRDY BIT(0)
92 #define MMA8452_INT_FF_MT BIT(2)
93 #define MMA8452_INT_TRANS BIT(5)
94
95 #define MMA8451_DEVICE_ID 0x1a
96 #define MMA8452_DEVICE_ID 0x2a
97 #define MMA8453_DEVICE_ID 0x3a
98 #define MMA8652_DEVICE_ID 0x4a
99 #define MMA8653_DEVICE_ID 0x5a
100 #define FXLS8471_DEVICE_ID 0x6a
101
102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
103
104 struct mma8452_data {
105 struct i2c_client *client;
106 struct mutex lock;
107 struct iio_mount_matrix orientation;
108 u8 ctrl_reg1;
109 u8 data_cfg;
110 const struct mma_chip_info *chip_info;
111 int sleep_val;
112 struct regulator *vdd_reg;
113 struct regulator *vddio_reg;
114
115 /* Ensure correct alignment of time stamp when present */
116 struct {
117 __be16 channels[3];
118 s64 ts __aligned(8);
119 } buffer;
120 };
121
122 /**
123 * struct mma8452_event_regs - chip specific data related to events
124 * @ev_cfg: event config register address
125 * @ev_cfg_ele: latch bit in event config register
126 * @ev_cfg_chan_shift: number of the bit to enable events in X
127 * direction; in event config register
128 * @ev_src: event source register address
129 * @ev_ths: event threshold register address
130 * @ev_ths_mask: mask for the threshold value
131 * @ev_count: event count (period) register address
132 *
133 * Since not all chips supported by the driver support comparing high pass
134 * filtered data for events (interrupts), different interrupt sources are
135 * used for different chips and the relevant registers are included here.
136 */
137 struct mma8452_event_regs {
138 u8 ev_cfg;
139 u8 ev_cfg_ele;
140 u8 ev_cfg_chan_shift;
141 u8 ev_src;
142 u8 ev_ths;
143 u8 ev_ths_mask;
144 u8 ev_count;
145 };
146
147 static const struct mma8452_event_regs ff_mt_ev_regs = {
148 .ev_cfg = MMA8452_FF_MT_CFG,
149 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
150 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
151 .ev_src = MMA8452_FF_MT_SRC,
152 .ev_ths = MMA8452_FF_MT_THS,
153 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
154 .ev_count = MMA8452_FF_MT_COUNT
155 };
156
157 static const struct mma8452_event_regs trans_ev_regs = {
158 .ev_cfg = MMA8452_TRANSIENT_CFG,
159 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
160 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
161 .ev_src = MMA8452_TRANSIENT_SRC,
162 .ev_ths = MMA8452_TRANSIENT_THS,
163 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
164 .ev_count = MMA8452_TRANSIENT_COUNT,
165 };
166
167 /**
168 * struct mma_chip_info - chip specific data
169 * @name: part number of device reported via 'name' attr
170 * @chip_id: WHO_AM_I register's value
171 * @channels: struct iio_chan_spec matching the device's
172 * capabilities
173 * @num_channels: number of channels
174 * @mma_scales: scale factors for converting register values
175 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
176 * per mode: m/s^2 and micro m/s^2
177 * @all_events: all events supported by this chip
178 * @enabled_events: event flags enabled and handled by this driver
179 */
180 struct mma_chip_info {
181 const char *name;
182 u8 chip_id;
183 const struct iio_chan_spec *channels;
184 int num_channels;
185 const int mma_scales[3][2];
186 int all_events;
187 int enabled_events;
188 };
189
190 enum {
191 idx_x,
192 idx_y,
193 idx_z,
194 idx_ts,
195 };
196
mma8452_drdy(struct mma8452_data * data)197 static int mma8452_drdy(struct mma8452_data *data)
198 {
199 int tries = 150;
200
201 while (tries-- > 0) {
202 int ret = i2c_smbus_read_byte_data(data->client,
203 MMA8452_STATUS);
204 if (ret < 0)
205 return ret;
206 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
207 return 0;
208
209 if (data->sleep_val <= 20)
210 usleep_range(data->sleep_val * 250,
211 data->sleep_val * 500);
212 else
213 msleep(20);
214 }
215
216 dev_err(&data->client->dev, "data not ready\n");
217
218 return -EIO;
219 }
220
mma8452_set_runtime_pm_state(struct i2c_client * client,bool on)221 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
222 {
223 #ifdef CONFIG_PM
224 int ret;
225
226 if (on) {
227 ret = pm_runtime_resume_and_get(&client->dev);
228 } else {
229 pm_runtime_mark_last_busy(&client->dev);
230 ret = pm_runtime_put_autosuspend(&client->dev);
231 }
232
233 if (ret < 0) {
234 dev_err(&client->dev,
235 "failed to change power state to %d\n", on);
236
237 return ret;
238 }
239 #endif
240
241 return 0;
242 }
243
mma8452_read(struct mma8452_data * data,__be16 buf[3])244 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
245 {
246 int ret = mma8452_drdy(data);
247
248 if (ret < 0)
249 return ret;
250
251 ret = mma8452_set_runtime_pm_state(data->client, true);
252 if (ret)
253 return ret;
254
255 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
256 3 * sizeof(__be16), (u8 *)buf);
257
258 ret = mma8452_set_runtime_pm_state(data->client, false);
259
260 return ret;
261 }
262
mma8452_show_int_plus_micros(char * buf,const int (* vals)[2],int n)263 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
264 int n)
265 {
266 size_t len = 0;
267
268 while (n-- > 0)
269 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
270 vals[n][0], vals[n][1]);
271
272 /* replace trailing space by newline */
273 buf[len - 1] = '\n';
274
275 return len;
276 }
277
mma8452_get_int_plus_micros_index(const int (* vals)[2],int n,int val,int val2)278 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
279 int val, int val2)
280 {
281 while (n-- > 0)
282 if (val == vals[n][0] && val2 == vals[n][1])
283 return n;
284
285 return -EINVAL;
286 }
287
mma8452_get_odr_index(struct mma8452_data * data)288 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
289 {
290 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
291 MMA8452_CTRL_DR_SHIFT;
292 }
293
294 static const int mma8452_samp_freq[8][2] = {
295 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
296 {6, 250000}, {1, 560000}
297 };
298
299 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
300 static const unsigned int mma8452_time_step_us[4][8] = {
301 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
302 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
303 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
304 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
305 };
306
307 /* Datasheet table "High-Pass Filter Cutoff Options" */
308 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
309 { /* normal */
310 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
311 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
312 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
313 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
318 },
319 { /* low noise low power */
320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
322 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
323 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
324 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
327 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
328 },
329 { /* high resolution */
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
338 },
339 { /* low power */
340 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
341 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
342 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
343 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
344 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
347 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
348 }
349 };
350
351 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
352 static const u16 mma8452_os_ratio[4][8] = {
353 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
354 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
355 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
356 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
357 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
358 };
359
mma8452_get_power_mode(struct mma8452_data * data)360 static int mma8452_get_power_mode(struct mma8452_data *data)
361 {
362 int reg;
363
364 reg = i2c_smbus_read_byte_data(data->client,
365 MMA8452_CTRL_REG2);
366 if (reg < 0)
367 return reg;
368
369 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
370 MMA8452_CTRL_REG2_MODS_SHIFT);
371 }
372
mma8452_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)373 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
374 struct device_attribute *attr,
375 char *buf)
376 {
377 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
378 ARRAY_SIZE(mma8452_samp_freq));
379 }
380
mma8452_show_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)381 static ssize_t mma8452_show_scale_avail(struct device *dev,
382 struct device_attribute *attr,
383 char *buf)
384 {
385 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
386 struct mma8452_data *data = iio_priv(indio_dev);
387
388 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
389 ARRAY_SIZE(data->chip_info->mma_scales));
390 }
391
mma8452_show_hp_cutoff_avail(struct device * dev,struct device_attribute * attr,char * buf)392 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
393 struct device_attribute *attr,
394 char *buf)
395 {
396 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
397 struct mma8452_data *data = iio_priv(indio_dev);
398 int i, j;
399
400 i = mma8452_get_odr_index(data);
401 j = mma8452_get_power_mode(data);
402 if (j < 0)
403 return j;
404
405 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
406 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
407 }
408
mma8452_show_os_ratio_avail(struct device * dev,struct device_attribute * attr,char * buf)409 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
410 struct device_attribute *attr,
411 char *buf)
412 {
413 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
414 struct mma8452_data *data = iio_priv(indio_dev);
415 int i = mma8452_get_odr_index(data);
416 int j;
417 u16 val = 0;
418 size_t len = 0;
419
420 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
421 if (val == mma8452_os_ratio[j][i])
422 continue;
423
424 val = mma8452_os_ratio[j][i];
425
426 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
427 }
428 buf[len - 1] = '\n';
429
430 return len;
431 }
432
433 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
434 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
435 mma8452_show_scale_avail, NULL, 0);
436 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
437 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
438 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
439 mma8452_show_os_ratio_avail, NULL, 0);
440
mma8452_get_samp_freq_index(struct mma8452_data * data,int val,int val2)441 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
442 int val, int val2)
443 {
444 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
445 ARRAY_SIZE(mma8452_samp_freq),
446 val, val2);
447 }
448
mma8452_get_scale_index(struct mma8452_data * data,int val,int val2)449 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
450 {
451 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
452 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
453 }
454
mma8452_get_hp_filter_index(struct mma8452_data * data,int val,int val2)455 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
456 int val, int val2)
457 {
458 int i, j;
459
460 i = mma8452_get_odr_index(data);
461 j = mma8452_get_power_mode(data);
462 if (j < 0)
463 return j;
464
465 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
466 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
467 }
468
mma8452_read_hp_filter(struct mma8452_data * data,int * hz,int * uHz)469 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
470 {
471 int j, i, ret;
472
473 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
474 if (ret < 0)
475 return ret;
476
477 i = mma8452_get_odr_index(data);
478 j = mma8452_get_power_mode(data);
479 if (j < 0)
480 return j;
481
482 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
483 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
484 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
485
486 return 0;
487 }
488
mma8452_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)489 static int mma8452_read_raw(struct iio_dev *indio_dev,
490 struct iio_chan_spec const *chan,
491 int *val, int *val2, long mask)
492 {
493 struct mma8452_data *data = iio_priv(indio_dev);
494 __be16 buffer[3];
495 int i, ret;
496
497 switch (mask) {
498 case IIO_CHAN_INFO_RAW:
499 ret = iio_device_claim_direct_mode(indio_dev);
500 if (ret)
501 return ret;
502
503 mutex_lock(&data->lock);
504 ret = mma8452_read(data, buffer);
505 mutex_unlock(&data->lock);
506 iio_device_release_direct_mode(indio_dev);
507 if (ret < 0)
508 return ret;
509
510 *val = sign_extend32(be16_to_cpu(
511 buffer[chan->scan_index]) >> chan->scan_type.shift,
512 chan->scan_type.realbits - 1);
513
514 return IIO_VAL_INT;
515 case IIO_CHAN_INFO_SCALE:
516 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
517 *val = data->chip_info->mma_scales[i][0];
518 *val2 = data->chip_info->mma_scales[i][1];
519
520 return IIO_VAL_INT_PLUS_MICRO;
521 case IIO_CHAN_INFO_SAMP_FREQ:
522 i = mma8452_get_odr_index(data);
523 *val = mma8452_samp_freq[i][0];
524 *val2 = mma8452_samp_freq[i][1];
525
526 return IIO_VAL_INT_PLUS_MICRO;
527 case IIO_CHAN_INFO_CALIBBIAS:
528 ret = i2c_smbus_read_byte_data(data->client,
529 MMA8452_OFF_X +
530 chan->scan_index);
531 if (ret < 0)
532 return ret;
533
534 *val = sign_extend32(ret, 7);
535
536 return IIO_VAL_INT;
537 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
538 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
539 ret = mma8452_read_hp_filter(data, val, val2);
540 if (ret < 0)
541 return ret;
542 } else {
543 *val = 0;
544 *val2 = 0;
545 }
546
547 return IIO_VAL_INT_PLUS_MICRO;
548 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
549 ret = mma8452_get_power_mode(data);
550 if (ret < 0)
551 return ret;
552
553 i = mma8452_get_odr_index(data);
554
555 *val = mma8452_os_ratio[ret][i];
556 return IIO_VAL_INT;
557 }
558
559 return -EINVAL;
560 }
561
mma8452_calculate_sleep(struct mma8452_data * data)562 static int mma8452_calculate_sleep(struct mma8452_data *data)
563 {
564 int ret, i = mma8452_get_odr_index(data);
565
566 if (mma8452_samp_freq[i][0] > 0)
567 ret = 1000 / mma8452_samp_freq[i][0];
568 else
569 ret = 1000;
570
571 return ret == 0 ? 1 : ret;
572 }
573
mma8452_standby(struct mma8452_data * data)574 static int mma8452_standby(struct mma8452_data *data)
575 {
576 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
577 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
578 }
579
mma8452_active(struct mma8452_data * data)580 static int mma8452_active(struct mma8452_data *data)
581 {
582 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
583 data->ctrl_reg1);
584 }
585
586 /* returns >0 if active, 0 if in standby and <0 on error */
mma8452_is_active(struct mma8452_data * data)587 static int mma8452_is_active(struct mma8452_data *data)
588 {
589 int reg;
590
591 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
592 if (reg < 0)
593 return reg;
594
595 return reg & MMA8452_CTRL_ACTIVE;
596 }
597
mma8452_change_config(struct mma8452_data * data,u8 reg,u8 val)598 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
599 {
600 int ret;
601 int is_active;
602
603 mutex_lock(&data->lock);
604
605 is_active = mma8452_is_active(data);
606 if (is_active < 0) {
607 ret = is_active;
608 goto fail;
609 }
610
611 /* config can only be changed when in standby */
612 if (is_active > 0) {
613 ret = mma8452_standby(data);
614 if (ret < 0)
615 goto fail;
616 }
617
618 ret = i2c_smbus_write_byte_data(data->client, reg, val);
619 if (ret < 0)
620 goto fail;
621
622 if (is_active > 0) {
623 ret = mma8452_active(data);
624 if (ret < 0)
625 goto fail;
626 }
627
628 ret = 0;
629 fail:
630 mutex_unlock(&data->lock);
631
632 return ret;
633 }
634
mma8452_set_power_mode(struct mma8452_data * data,u8 mode)635 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
636 {
637 int reg;
638
639 reg = i2c_smbus_read_byte_data(data->client,
640 MMA8452_CTRL_REG2);
641 if (reg < 0)
642 return reg;
643
644 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
645 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
646
647 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
648 }
649
650 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
mma8452_freefall_mode_enabled(struct mma8452_data * data)651 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
652 {
653 int val;
654
655 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
656 if (val < 0)
657 return val;
658
659 return !(val & MMA8452_FF_MT_CFG_OAE);
660 }
661
mma8452_set_freefall_mode(struct mma8452_data * data,bool state)662 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
663 {
664 int val;
665
666 if ((state && mma8452_freefall_mode_enabled(data)) ||
667 (!state && !(mma8452_freefall_mode_enabled(data))))
668 return 0;
669
670 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
671 if (val < 0)
672 return val;
673
674 if (state) {
675 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
676 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
677 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
678 val &= ~MMA8452_FF_MT_CFG_OAE;
679 } else {
680 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
681 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
682 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
683 val |= MMA8452_FF_MT_CFG_OAE;
684 }
685
686 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
687 }
688
mma8452_set_hp_filter_frequency(struct mma8452_data * data,int val,int val2)689 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
690 int val, int val2)
691 {
692 int i, reg;
693
694 i = mma8452_get_hp_filter_index(data, val, val2);
695 if (i < 0)
696 return i;
697
698 reg = i2c_smbus_read_byte_data(data->client,
699 MMA8452_HP_FILTER_CUTOFF);
700 if (reg < 0)
701 return reg;
702
703 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
704 reg |= i;
705
706 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
707 }
708
mma8452_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)709 static int mma8452_write_raw(struct iio_dev *indio_dev,
710 struct iio_chan_spec const *chan,
711 int val, int val2, long mask)
712 {
713 struct mma8452_data *data = iio_priv(indio_dev);
714 int i, j, ret;
715
716 ret = iio_device_claim_direct_mode(indio_dev);
717 if (ret)
718 return ret;
719
720 switch (mask) {
721 case IIO_CHAN_INFO_SAMP_FREQ:
722 i = mma8452_get_samp_freq_index(data, val, val2);
723 if (i < 0) {
724 ret = i;
725 break;
726 }
727 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
728 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
729
730 data->sleep_val = mma8452_calculate_sleep(data);
731
732 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
733 data->ctrl_reg1);
734 break;
735 case IIO_CHAN_INFO_SCALE:
736 i = mma8452_get_scale_index(data, val, val2);
737 if (i < 0) {
738 ret = i;
739 break;
740 }
741
742 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
743 data->data_cfg |= i;
744
745 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
746 data->data_cfg);
747 break;
748 case IIO_CHAN_INFO_CALIBBIAS:
749 if (val < -128 || val > 127) {
750 ret = -EINVAL;
751 break;
752 }
753
754 ret = mma8452_change_config(data,
755 MMA8452_OFF_X + chan->scan_index,
756 val);
757 break;
758
759 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
760 if (val == 0 && val2 == 0) {
761 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
762 } else {
763 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
764 ret = mma8452_set_hp_filter_frequency(data, val, val2);
765 if (ret < 0)
766 break;
767 }
768
769 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
770 data->data_cfg);
771 break;
772
773 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
774 j = mma8452_get_odr_index(data);
775
776 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
777 if (mma8452_os_ratio[i][j] == val) {
778 ret = mma8452_set_power_mode(data, i);
779 break;
780 }
781 }
782 if (i == ARRAY_SIZE(mma8452_os_ratio)) {
783 ret = -EINVAL;
784 break;
785 }
786 break;
787 default:
788 ret = -EINVAL;
789 break;
790 }
791
792 iio_device_release_direct_mode(indio_dev);
793 return ret;
794 }
795
mma8452_get_event_regs(struct mma8452_data * data,const struct iio_chan_spec * chan,enum iio_event_direction dir,const struct mma8452_event_regs ** ev_reg)796 static int mma8452_get_event_regs(struct mma8452_data *data,
797 const struct iio_chan_spec *chan, enum iio_event_direction dir,
798 const struct mma8452_event_regs **ev_reg)
799 {
800 if (!chan)
801 return -EINVAL;
802
803 switch (chan->type) {
804 case IIO_ACCEL:
805 switch (dir) {
806 case IIO_EV_DIR_RISING:
807 if ((data->chip_info->all_events
808 & MMA8452_INT_TRANS) &&
809 (data->chip_info->enabled_events
810 & MMA8452_INT_TRANS))
811 *ev_reg = &trans_ev_regs;
812 else
813 *ev_reg = &ff_mt_ev_regs;
814 return 0;
815 case IIO_EV_DIR_FALLING:
816 *ev_reg = &ff_mt_ev_regs;
817 return 0;
818 default:
819 return -EINVAL;
820 }
821 default:
822 return -EINVAL;
823 }
824 }
825
mma8452_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)826 static int mma8452_read_event_value(struct iio_dev *indio_dev,
827 const struct iio_chan_spec *chan,
828 enum iio_event_type type,
829 enum iio_event_direction dir,
830 enum iio_event_info info,
831 int *val, int *val2)
832 {
833 struct mma8452_data *data = iio_priv(indio_dev);
834 int ret, us, power_mode;
835 const struct mma8452_event_regs *ev_regs;
836
837 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
838 if (ret)
839 return ret;
840
841 switch (info) {
842 case IIO_EV_INFO_VALUE:
843 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
844 if (ret < 0)
845 return ret;
846
847 *val = ret & ev_regs->ev_ths_mask;
848
849 return IIO_VAL_INT;
850
851 case IIO_EV_INFO_PERIOD:
852 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
853 if (ret < 0)
854 return ret;
855
856 power_mode = mma8452_get_power_mode(data);
857 if (power_mode < 0)
858 return power_mode;
859
860 us = ret * mma8452_time_step_us[power_mode][
861 mma8452_get_odr_index(data)];
862 *val = us / USEC_PER_SEC;
863 *val2 = us % USEC_PER_SEC;
864
865 return IIO_VAL_INT_PLUS_MICRO;
866
867 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
868 ret = i2c_smbus_read_byte_data(data->client,
869 MMA8452_TRANSIENT_CFG);
870 if (ret < 0)
871 return ret;
872
873 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
874 *val = 0;
875 *val2 = 0;
876 } else {
877 ret = mma8452_read_hp_filter(data, val, val2);
878 if (ret < 0)
879 return ret;
880 }
881
882 return IIO_VAL_INT_PLUS_MICRO;
883
884 default:
885 return -EINVAL;
886 }
887 }
888
mma8452_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)889 static int mma8452_write_event_value(struct iio_dev *indio_dev,
890 const struct iio_chan_spec *chan,
891 enum iio_event_type type,
892 enum iio_event_direction dir,
893 enum iio_event_info info,
894 int val, int val2)
895 {
896 struct mma8452_data *data = iio_priv(indio_dev);
897 int ret, reg, steps;
898 const struct mma8452_event_regs *ev_regs;
899
900 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
901 if (ret)
902 return ret;
903
904 switch (info) {
905 case IIO_EV_INFO_VALUE:
906 if (val < 0 || val > ev_regs->ev_ths_mask)
907 return -EINVAL;
908
909 return mma8452_change_config(data, ev_regs->ev_ths, val);
910
911 case IIO_EV_INFO_PERIOD:
912 ret = mma8452_get_power_mode(data);
913 if (ret < 0)
914 return ret;
915
916 steps = (val * USEC_PER_SEC + val2) /
917 mma8452_time_step_us[ret][
918 mma8452_get_odr_index(data)];
919
920 if (steps < 0 || steps > 0xff)
921 return -EINVAL;
922
923 return mma8452_change_config(data, ev_regs->ev_count, steps);
924
925 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
926 reg = i2c_smbus_read_byte_data(data->client,
927 MMA8452_TRANSIENT_CFG);
928 if (reg < 0)
929 return reg;
930
931 if (val == 0 && val2 == 0) {
932 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
933 } else {
934 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
935 ret = mma8452_set_hp_filter_frequency(data, val, val2);
936 if (ret < 0)
937 return ret;
938 }
939
940 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
941
942 default:
943 return -EINVAL;
944 }
945 }
946
mma8452_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)947 static int mma8452_read_event_config(struct iio_dev *indio_dev,
948 const struct iio_chan_spec *chan,
949 enum iio_event_type type,
950 enum iio_event_direction dir)
951 {
952 struct mma8452_data *data = iio_priv(indio_dev);
953 int ret;
954 const struct mma8452_event_regs *ev_regs;
955
956 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
957 if (ret)
958 return ret;
959
960 switch (dir) {
961 case IIO_EV_DIR_FALLING:
962 return mma8452_freefall_mode_enabled(data);
963 case IIO_EV_DIR_RISING:
964 ret = i2c_smbus_read_byte_data(data->client,
965 ev_regs->ev_cfg);
966 if (ret < 0)
967 return ret;
968
969 return !!(ret & BIT(chan->scan_index +
970 ev_regs->ev_cfg_chan_shift));
971 default:
972 return -EINVAL;
973 }
974 }
975
mma8452_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)976 static int mma8452_write_event_config(struct iio_dev *indio_dev,
977 const struct iio_chan_spec *chan,
978 enum iio_event_type type,
979 enum iio_event_direction dir,
980 int state)
981 {
982 struct mma8452_data *data = iio_priv(indio_dev);
983 int val, ret;
984 const struct mma8452_event_regs *ev_regs;
985
986 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
987 if (ret)
988 return ret;
989
990 ret = mma8452_set_runtime_pm_state(data->client, state);
991 if (ret)
992 return ret;
993
994 switch (dir) {
995 case IIO_EV_DIR_FALLING:
996 return mma8452_set_freefall_mode(data, state);
997 case IIO_EV_DIR_RISING:
998 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
999 if (val < 0)
1000 return val;
1001
1002 if (state) {
1003 if (mma8452_freefall_mode_enabled(data)) {
1004 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
1005 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1006 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1007 val |= MMA8452_FF_MT_CFG_OAE;
1008 }
1009 val |= BIT(chan->scan_index +
1010 ev_regs->ev_cfg_chan_shift);
1011 } else {
1012 if (mma8452_freefall_mode_enabled(data))
1013 return 0;
1014
1015 val &= ~BIT(chan->scan_index +
1016 ev_regs->ev_cfg_chan_shift);
1017 }
1018
1019 val |= ev_regs->ev_cfg_ele;
1020
1021 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1022 default:
1023 return -EINVAL;
1024 }
1025 }
1026
mma8452_transient_interrupt(struct iio_dev * indio_dev)1027 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1028 {
1029 struct mma8452_data *data = iio_priv(indio_dev);
1030 s64 ts = iio_get_time_ns(indio_dev);
1031 int src;
1032
1033 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1034 if (src < 0)
1035 return;
1036
1037 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1038 iio_push_event(indio_dev,
1039 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1040 IIO_EV_TYPE_MAG,
1041 IIO_EV_DIR_RISING),
1042 ts);
1043
1044 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1045 iio_push_event(indio_dev,
1046 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1047 IIO_EV_TYPE_MAG,
1048 IIO_EV_DIR_RISING),
1049 ts);
1050
1051 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1052 iio_push_event(indio_dev,
1053 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1054 IIO_EV_TYPE_MAG,
1055 IIO_EV_DIR_RISING),
1056 ts);
1057 }
1058
mma8452_interrupt(int irq,void * p)1059 static irqreturn_t mma8452_interrupt(int irq, void *p)
1060 {
1061 struct iio_dev *indio_dev = p;
1062 struct mma8452_data *data = iio_priv(indio_dev);
1063 irqreturn_t ret = IRQ_NONE;
1064 int src;
1065
1066 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1067 if (src < 0)
1068 return IRQ_NONE;
1069
1070 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1071 return IRQ_NONE;
1072
1073 if (src & MMA8452_INT_DRDY) {
1074 iio_trigger_poll_nested(indio_dev->trig);
1075 ret = IRQ_HANDLED;
1076 }
1077
1078 if (src & MMA8452_INT_FF_MT) {
1079 if (mma8452_freefall_mode_enabled(data)) {
1080 s64 ts = iio_get_time_ns(indio_dev);
1081
1082 iio_push_event(indio_dev,
1083 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1084 IIO_MOD_X_AND_Y_AND_Z,
1085 IIO_EV_TYPE_MAG,
1086 IIO_EV_DIR_FALLING),
1087 ts);
1088 }
1089 ret = IRQ_HANDLED;
1090 }
1091
1092 if (src & MMA8452_INT_TRANS) {
1093 mma8452_transient_interrupt(indio_dev);
1094 ret = IRQ_HANDLED;
1095 }
1096
1097 return ret;
1098 }
1099
mma8452_trigger_handler(int irq,void * p)1100 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1101 {
1102 struct iio_poll_func *pf = p;
1103 struct iio_dev *indio_dev = pf->indio_dev;
1104 struct mma8452_data *data = iio_priv(indio_dev);
1105 int ret;
1106
1107 ret = mma8452_read(data, data->buffer.channels);
1108 if (ret < 0)
1109 goto done;
1110
1111 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1112 iio_get_time_ns(indio_dev));
1113
1114 done:
1115 iio_trigger_notify_done(indio_dev->trig);
1116
1117 return IRQ_HANDLED;
1118 }
1119
mma8452_reg_access_dbg(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1120 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1121 unsigned int reg, unsigned int writeval,
1122 unsigned int *readval)
1123 {
1124 int ret;
1125 struct mma8452_data *data = iio_priv(indio_dev);
1126
1127 if (reg > MMA8452_MAX_REG)
1128 return -EINVAL;
1129
1130 if (!readval)
1131 return mma8452_change_config(data, reg, writeval);
1132
1133 ret = i2c_smbus_read_byte_data(data->client, reg);
1134 if (ret < 0)
1135 return ret;
1136
1137 *readval = ret;
1138
1139 return 0;
1140 }
1141
1142 static const struct iio_event_spec mma8452_freefall_event[] = {
1143 {
1144 .type = IIO_EV_TYPE_MAG,
1145 .dir = IIO_EV_DIR_FALLING,
1146 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1147 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1148 BIT(IIO_EV_INFO_PERIOD) |
1149 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1150 },
1151 };
1152
1153 static const struct iio_event_spec mma8652_freefall_event[] = {
1154 {
1155 .type = IIO_EV_TYPE_MAG,
1156 .dir = IIO_EV_DIR_FALLING,
1157 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1158 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1159 BIT(IIO_EV_INFO_PERIOD)
1160 },
1161 };
1162
1163 static const struct iio_event_spec mma8452_transient_event[] = {
1164 {
1165 .type = IIO_EV_TYPE_MAG,
1166 .dir = IIO_EV_DIR_RISING,
1167 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1168 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1169 BIT(IIO_EV_INFO_PERIOD) |
1170 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1171 },
1172 };
1173
1174 static const struct iio_event_spec mma8452_motion_event[] = {
1175 {
1176 .type = IIO_EV_TYPE_MAG,
1177 .dir = IIO_EV_DIR_RISING,
1178 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1179 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1180 BIT(IIO_EV_INFO_PERIOD)
1181 },
1182 };
1183
1184 /*
1185 * Threshold is configured in fixed 8G/127 steps regardless of
1186 * currently selected scale for measurement.
1187 */
1188 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1189
1190 static struct attribute *mma8452_event_attributes[] = {
1191 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1192 NULL,
1193 };
1194
1195 static const struct attribute_group mma8452_event_attribute_group = {
1196 .attrs = mma8452_event_attributes,
1197 };
1198
1199 static const struct iio_mount_matrix *
mma8452_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1200 mma8452_get_mount_matrix(const struct iio_dev *indio_dev,
1201 const struct iio_chan_spec *chan)
1202 {
1203 struct mma8452_data *data = iio_priv(indio_dev);
1204
1205 return &data->orientation;
1206 }
1207
1208 static const struct iio_chan_spec_ext_info mma8452_ext_info[] = {
1209 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mma8452_get_mount_matrix),
1210 { }
1211 };
1212
1213 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1214 .type = IIO_ACCEL, \
1215 .modified = 1, \
1216 .channel2 = modifier, \
1217 .scan_index = -1, \
1218 .event_spec = mma8452_freefall_event, \
1219 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1220 }
1221
1222 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1223 .type = IIO_ACCEL, \
1224 .modified = 1, \
1225 .channel2 = modifier, \
1226 .scan_index = -1, \
1227 .event_spec = mma8652_freefall_event, \
1228 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1229 }
1230
1231 #define MMA8452_CHANNEL(axis, idx, bits) { \
1232 .type = IIO_ACCEL, \
1233 .modified = 1, \
1234 .channel2 = IIO_MOD_##axis, \
1235 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1236 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1237 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1238 BIT(IIO_CHAN_INFO_SCALE) | \
1239 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1240 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1241 .scan_index = idx, \
1242 .scan_type = { \
1243 .sign = 's', \
1244 .realbits = (bits), \
1245 .storagebits = 16, \
1246 .shift = 16 - (bits), \
1247 .endianness = IIO_BE, \
1248 }, \
1249 .event_spec = mma8452_transient_event, \
1250 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1251 .ext_info = mma8452_ext_info, \
1252 }
1253
1254 #define MMA8652_CHANNEL(axis, idx, bits) { \
1255 .type = IIO_ACCEL, \
1256 .modified = 1, \
1257 .channel2 = IIO_MOD_##axis, \
1258 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1259 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1260 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1261 BIT(IIO_CHAN_INFO_SCALE) | \
1262 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1263 .scan_index = idx, \
1264 .scan_type = { \
1265 .sign = 's', \
1266 .realbits = (bits), \
1267 .storagebits = 16, \
1268 .shift = 16 - (bits), \
1269 .endianness = IIO_BE, \
1270 }, \
1271 .event_spec = mma8452_motion_event, \
1272 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1273 .ext_info = mma8452_ext_info, \
1274 }
1275
1276 static const struct iio_chan_spec mma8451_channels[] = {
1277 MMA8452_CHANNEL(X, idx_x, 14),
1278 MMA8452_CHANNEL(Y, idx_y, 14),
1279 MMA8452_CHANNEL(Z, idx_z, 14),
1280 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1281 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1282 };
1283
1284 static const struct iio_chan_spec mma8452_channels[] = {
1285 MMA8452_CHANNEL(X, idx_x, 12),
1286 MMA8452_CHANNEL(Y, idx_y, 12),
1287 MMA8452_CHANNEL(Z, idx_z, 12),
1288 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1289 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1290 };
1291
1292 static const struct iio_chan_spec mma8453_channels[] = {
1293 MMA8452_CHANNEL(X, idx_x, 10),
1294 MMA8452_CHANNEL(Y, idx_y, 10),
1295 MMA8452_CHANNEL(Z, idx_z, 10),
1296 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1297 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1298 };
1299
1300 static const struct iio_chan_spec mma8652_channels[] = {
1301 MMA8652_CHANNEL(X, idx_x, 12),
1302 MMA8652_CHANNEL(Y, idx_y, 12),
1303 MMA8652_CHANNEL(Z, idx_z, 12),
1304 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1305 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1306 };
1307
1308 static const struct iio_chan_spec mma8653_channels[] = {
1309 MMA8652_CHANNEL(X, idx_x, 10),
1310 MMA8652_CHANNEL(Y, idx_y, 10),
1311 MMA8652_CHANNEL(Z, idx_z, 10),
1312 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1313 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1314 };
1315
1316 enum {
1317 mma8451,
1318 mma8452,
1319 mma8453,
1320 mma8652,
1321 mma8653,
1322 fxls8471,
1323 };
1324
1325 static const struct mma_chip_info mma_chip_info_table[] = {
1326 [mma8451] = {
1327 .name = "mma8451",
1328 .chip_id = MMA8451_DEVICE_ID,
1329 .channels = mma8451_channels,
1330 .num_channels = ARRAY_SIZE(mma8451_channels),
1331 /*
1332 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1333 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1334 * bit.
1335 * The userspace interface uses m/s^2 and we declare micro units
1336 * So scale factor for 12 bit here is given by:
1337 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1338 */
1339 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1340 /*
1341 * Although we enable the interrupt sources once and for
1342 * all here the event detection itself is not enabled until
1343 * userspace asks for it by mma8452_write_event_config()
1344 */
1345 .all_events = MMA8452_INT_DRDY |
1346 MMA8452_INT_TRANS |
1347 MMA8452_INT_FF_MT,
1348 .enabled_events = MMA8452_INT_TRANS |
1349 MMA8452_INT_FF_MT,
1350 },
1351 [mma8452] = {
1352 .name = "mma8452",
1353 .chip_id = MMA8452_DEVICE_ID,
1354 .channels = mma8452_channels,
1355 .num_channels = ARRAY_SIZE(mma8452_channels),
1356 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1357 /*
1358 * Although we enable the interrupt sources once and for
1359 * all here the event detection itself is not enabled until
1360 * userspace asks for it by mma8452_write_event_config()
1361 */
1362 .all_events = MMA8452_INT_DRDY |
1363 MMA8452_INT_TRANS |
1364 MMA8452_INT_FF_MT,
1365 .enabled_events = MMA8452_INT_TRANS |
1366 MMA8452_INT_FF_MT,
1367 },
1368 [mma8453] = {
1369 .name = "mma8453",
1370 .chip_id = MMA8453_DEVICE_ID,
1371 .channels = mma8453_channels,
1372 .num_channels = ARRAY_SIZE(mma8453_channels),
1373 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1374 /*
1375 * Although we enable the interrupt sources once and for
1376 * all here the event detection itself is not enabled until
1377 * userspace asks for it by mma8452_write_event_config()
1378 */
1379 .all_events = MMA8452_INT_DRDY |
1380 MMA8452_INT_TRANS |
1381 MMA8452_INT_FF_MT,
1382 .enabled_events = MMA8452_INT_TRANS |
1383 MMA8452_INT_FF_MT,
1384 },
1385 [mma8652] = {
1386 .name = "mma8652",
1387 .chip_id = MMA8652_DEVICE_ID,
1388 .channels = mma8652_channels,
1389 .num_channels = ARRAY_SIZE(mma8652_channels),
1390 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1391 .all_events = MMA8452_INT_DRDY |
1392 MMA8452_INT_FF_MT,
1393 .enabled_events = MMA8452_INT_FF_MT,
1394 },
1395 [mma8653] = {
1396 .name = "mma8653",
1397 .chip_id = MMA8653_DEVICE_ID,
1398 .channels = mma8653_channels,
1399 .num_channels = ARRAY_SIZE(mma8653_channels),
1400 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1401 /*
1402 * Although we enable the interrupt sources once and for
1403 * all here the event detection itself is not enabled until
1404 * userspace asks for it by mma8452_write_event_config()
1405 */
1406 .all_events = MMA8452_INT_DRDY |
1407 MMA8452_INT_FF_MT,
1408 .enabled_events = MMA8452_INT_FF_MT,
1409 },
1410 [fxls8471] = {
1411 .name = "fxls8471",
1412 .chip_id = FXLS8471_DEVICE_ID,
1413 .channels = mma8451_channels,
1414 .num_channels = ARRAY_SIZE(mma8451_channels),
1415 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1416 /*
1417 * Although we enable the interrupt sources once and for
1418 * all here the event detection itself is not enabled until
1419 * userspace asks for it by mma8452_write_event_config()
1420 */
1421 .all_events = MMA8452_INT_DRDY |
1422 MMA8452_INT_TRANS |
1423 MMA8452_INT_FF_MT,
1424 .enabled_events = MMA8452_INT_TRANS |
1425 MMA8452_INT_FF_MT,
1426 },
1427 };
1428
1429 static struct attribute *mma8452_attributes[] = {
1430 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1431 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1432 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1433 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1434 NULL
1435 };
1436
1437 static const struct attribute_group mma8452_group = {
1438 .attrs = mma8452_attributes,
1439 };
1440
1441 static const struct iio_info mma8452_info = {
1442 .attrs = &mma8452_group,
1443 .read_raw = &mma8452_read_raw,
1444 .write_raw = &mma8452_write_raw,
1445 .event_attrs = &mma8452_event_attribute_group,
1446 .read_event_value = &mma8452_read_event_value,
1447 .write_event_value = &mma8452_write_event_value,
1448 .read_event_config = &mma8452_read_event_config,
1449 .write_event_config = &mma8452_write_event_config,
1450 .debugfs_reg_access = &mma8452_reg_access_dbg,
1451 };
1452
1453 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1454
mma8452_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)1455 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1456 bool state)
1457 {
1458 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1459 struct mma8452_data *data = iio_priv(indio_dev);
1460 int reg, ret;
1461
1462 ret = mma8452_set_runtime_pm_state(data->client, state);
1463 if (ret)
1464 return ret;
1465
1466 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1467 if (reg < 0)
1468 return reg;
1469
1470 if (state)
1471 reg |= MMA8452_INT_DRDY;
1472 else
1473 reg &= ~MMA8452_INT_DRDY;
1474
1475 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1476 }
1477
1478 static const struct iio_trigger_ops mma8452_trigger_ops = {
1479 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1480 .validate_device = iio_trigger_validate_own_device,
1481 };
1482
mma8452_trigger_setup(struct iio_dev * indio_dev)1483 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1484 {
1485 struct mma8452_data *data = iio_priv(indio_dev);
1486 struct iio_trigger *trig;
1487 int ret;
1488
1489 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1490 indio_dev->name,
1491 iio_device_id(indio_dev));
1492 if (!trig)
1493 return -ENOMEM;
1494
1495 trig->ops = &mma8452_trigger_ops;
1496 iio_trigger_set_drvdata(trig, indio_dev);
1497
1498 ret = iio_trigger_register(trig);
1499 if (ret)
1500 return ret;
1501
1502 indio_dev->trig = iio_trigger_get(trig);
1503
1504 return 0;
1505 }
1506
mma8452_trigger_cleanup(struct iio_dev * indio_dev)1507 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1508 {
1509 if (indio_dev->trig)
1510 iio_trigger_unregister(indio_dev->trig);
1511 }
1512
mma8452_reset(struct i2c_client * client)1513 static int mma8452_reset(struct i2c_client *client)
1514 {
1515 int i;
1516 int ret;
1517
1518 /*
1519 * Find on fxls8471, after config reset bit, it reset immediately,
1520 * and will not give ACK, so here do not check the return value.
1521 * The following code will read the reset register, and check whether
1522 * this reset works.
1523 */
1524 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1525 MMA8452_CTRL_REG2_RST);
1526
1527 for (i = 0; i < 10; i++) {
1528 usleep_range(100, 200);
1529 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1530 if (ret == -EIO)
1531 continue; /* I2C comm reset */
1532 if (ret < 0)
1533 return ret;
1534 if (!(ret & MMA8452_CTRL_REG2_RST))
1535 return 0;
1536 }
1537
1538 return -ETIMEDOUT;
1539 }
1540
1541 static const struct of_device_id mma8452_dt_ids[] = {
1542 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1543 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1544 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1545 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1546 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1547 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1548 { }
1549 };
1550 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1551
mma8452_probe(struct i2c_client * client)1552 static int mma8452_probe(struct i2c_client *client)
1553 {
1554 const struct i2c_device_id *id = i2c_client_get_device_id(client);
1555 struct mma8452_data *data;
1556 struct iio_dev *indio_dev;
1557 int ret;
1558
1559 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1560 if (!indio_dev)
1561 return -ENOMEM;
1562
1563 data = iio_priv(indio_dev);
1564 data->client = client;
1565 mutex_init(&data->lock);
1566
1567 data->chip_info = device_get_match_data(&client->dev);
1568 if (!data->chip_info) {
1569 if (id) {
1570 data->chip_info = &mma_chip_info_table[id->driver_data];
1571 } else {
1572 dev_err(&client->dev, "unknown device model\n");
1573 return -ENODEV;
1574 }
1575 }
1576
1577 ret = iio_read_mount_matrix(&client->dev, &data->orientation);
1578 if (ret)
1579 return ret;
1580
1581 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1582 if (IS_ERR(data->vdd_reg))
1583 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1584 "failed to get VDD regulator!\n");
1585
1586 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1587 if (IS_ERR(data->vddio_reg))
1588 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1589 "failed to get VDDIO regulator!\n");
1590
1591 ret = regulator_enable(data->vdd_reg);
1592 if (ret) {
1593 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1594 return ret;
1595 }
1596
1597 ret = regulator_enable(data->vddio_reg);
1598 if (ret) {
1599 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1600 goto disable_regulator_vdd;
1601 }
1602
1603 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1604 if (ret < 0)
1605 goto disable_regulators;
1606
1607 switch (ret) {
1608 case MMA8451_DEVICE_ID:
1609 case MMA8452_DEVICE_ID:
1610 case MMA8453_DEVICE_ID:
1611 case MMA8652_DEVICE_ID:
1612 case MMA8653_DEVICE_ID:
1613 case FXLS8471_DEVICE_ID:
1614 if (ret == data->chip_info->chip_id)
1615 break;
1616 fallthrough;
1617 default:
1618 ret = -ENODEV;
1619 goto disable_regulators;
1620 }
1621
1622 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1623 data->chip_info->name, data->chip_info->chip_id);
1624
1625 i2c_set_clientdata(client, indio_dev);
1626 indio_dev->info = &mma8452_info;
1627 indio_dev->name = data->chip_info->name;
1628 indio_dev->modes = INDIO_DIRECT_MODE;
1629 indio_dev->channels = data->chip_info->channels;
1630 indio_dev->num_channels = data->chip_info->num_channels;
1631 indio_dev->available_scan_masks = mma8452_scan_masks;
1632
1633 ret = mma8452_reset(client);
1634 if (ret < 0)
1635 goto disable_regulators;
1636
1637 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1638 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1639 data->data_cfg);
1640 if (ret < 0)
1641 goto disable_regulators;
1642
1643 /*
1644 * By default set transient threshold to max to avoid events if
1645 * enabling without configuring threshold.
1646 */
1647 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1648 MMA8452_TRANSIENT_THS_MASK);
1649 if (ret < 0)
1650 goto disable_regulators;
1651
1652 if (client->irq) {
1653 int irq2;
1654
1655 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1656
1657 if (irq2 == client->irq) {
1658 dev_dbg(&client->dev, "using interrupt line INT2\n");
1659 } else {
1660 ret = i2c_smbus_write_byte_data(client,
1661 MMA8452_CTRL_REG5,
1662 data->chip_info->all_events);
1663 if (ret < 0)
1664 goto disable_regulators;
1665
1666 dev_dbg(&client->dev, "using interrupt line INT1\n");
1667 }
1668
1669 ret = i2c_smbus_write_byte_data(client,
1670 MMA8452_CTRL_REG4,
1671 data->chip_info->enabled_events);
1672 if (ret < 0)
1673 goto disable_regulators;
1674
1675 ret = mma8452_trigger_setup(indio_dev);
1676 if (ret < 0)
1677 goto disable_regulators;
1678 }
1679
1680 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1681 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1682
1683 data->sleep_val = mma8452_calculate_sleep(data);
1684
1685 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1686 data->ctrl_reg1);
1687 if (ret < 0)
1688 goto trigger_cleanup;
1689
1690 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1691 mma8452_trigger_handler, NULL);
1692 if (ret < 0)
1693 goto trigger_cleanup;
1694
1695 if (client->irq) {
1696 ret = devm_request_threaded_irq(&client->dev,
1697 client->irq,
1698 NULL, mma8452_interrupt,
1699 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1700 client->name, indio_dev);
1701 if (ret)
1702 goto buffer_cleanup;
1703 }
1704
1705 ret = pm_runtime_set_active(&client->dev);
1706 if (ret < 0)
1707 goto buffer_cleanup;
1708
1709 pm_runtime_enable(&client->dev);
1710 pm_runtime_set_autosuspend_delay(&client->dev,
1711 MMA8452_AUTO_SUSPEND_DELAY_MS);
1712 pm_runtime_use_autosuspend(&client->dev);
1713
1714 ret = iio_device_register(indio_dev);
1715 if (ret < 0)
1716 goto buffer_cleanup;
1717
1718 ret = mma8452_set_freefall_mode(data, false);
1719 if (ret < 0)
1720 goto unregister_device;
1721
1722 return 0;
1723
1724 unregister_device:
1725 iio_device_unregister(indio_dev);
1726
1727 buffer_cleanup:
1728 iio_triggered_buffer_cleanup(indio_dev);
1729
1730 trigger_cleanup:
1731 mma8452_trigger_cleanup(indio_dev);
1732
1733 disable_regulators:
1734 regulator_disable(data->vddio_reg);
1735
1736 disable_regulator_vdd:
1737 regulator_disable(data->vdd_reg);
1738
1739 return ret;
1740 }
1741
mma8452_remove(struct i2c_client * client)1742 static void mma8452_remove(struct i2c_client *client)
1743 {
1744 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1745 struct mma8452_data *data = iio_priv(indio_dev);
1746
1747 iio_device_unregister(indio_dev);
1748
1749 pm_runtime_disable(&client->dev);
1750 pm_runtime_set_suspended(&client->dev);
1751
1752 iio_triggered_buffer_cleanup(indio_dev);
1753 mma8452_trigger_cleanup(indio_dev);
1754 mma8452_standby(iio_priv(indio_dev));
1755
1756 regulator_disable(data->vddio_reg);
1757 regulator_disable(data->vdd_reg);
1758 }
1759
1760 #ifdef CONFIG_PM
mma8452_runtime_suspend(struct device * dev)1761 static int mma8452_runtime_suspend(struct device *dev)
1762 {
1763 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1764 struct mma8452_data *data = iio_priv(indio_dev);
1765 int ret;
1766
1767 mutex_lock(&data->lock);
1768 ret = mma8452_standby(data);
1769 mutex_unlock(&data->lock);
1770 if (ret < 0) {
1771 dev_err(&data->client->dev, "powering off device failed\n");
1772 return -EAGAIN;
1773 }
1774
1775 ret = regulator_disable(data->vddio_reg);
1776 if (ret) {
1777 dev_err(dev, "failed to disable VDDIO regulator\n");
1778 return ret;
1779 }
1780
1781 ret = regulator_disable(data->vdd_reg);
1782 if (ret) {
1783 dev_err(dev, "failed to disable VDD regulator\n");
1784 return ret;
1785 }
1786
1787 return 0;
1788 }
1789
mma8452_runtime_resume(struct device * dev)1790 static int mma8452_runtime_resume(struct device *dev)
1791 {
1792 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1793 struct mma8452_data *data = iio_priv(indio_dev);
1794 int ret, sleep_val;
1795
1796 ret = regulator_enable(data->vdd_reg);
1797 if (ret) {
1798 dev_err(dev, "failed to enable VDD regulator\n");
1799 return ret;
1800 }
1801
1802 ret = regulator_enable(data->vddio_reg);
1803 if (ret) {
1804 dev_err(dev, "failed to enable VDDIO regulator\n");
1805 regulator_disable(data->vdd_reg);
1806 return ret;
1807 }
1808
1809 ret = mma8452_active(data);
1810 if (ret < 0)
1811 goto runtime_resume_failed;
1812
1813 ret = mma8452_get_odr_index(data);
1814 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1815 if (sleep_val < 20)
1816 usleep_range(sleep_val * 1000, 20000);
1817 else
1818 msleep_interruptible(sleep_val);
1819
1820 return 0;
1821
1822 runtime_resume_failed:
1823 regulator_disable(data->vddio_reg);
1824 regulator_disable(data->vdd_reg);
1825
1826 return ret;
1827 }
1828 #endif
1829
1830 static const struct dev_pm_ops mma8452_pm_ops = {
1831 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1832 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1833 mma8452_runtime_resume, NULL)
1834 };
1835
1836 static const struct i2c_device_id mma8452_id[] = {
1837 { "mma8451", mma8451 },
1838 { "mma8452", mma8452 },
1839 { "mma8453", mma8453 },
1840 { "mma8652", mma8652 },
1841 { "mma8653", mma8653 },
1842 { "fxls8471", fxls8471 },
1843 { }
1844 };
1845 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1846
1847 static struct i2c_driver mma8452_driver = {
1848 .driver = {
1849 .name = "mma8452",
1850 .of_match_table = mma8452_dt_ids,
1851 .pm = &mma8452_pm_ops,
1852 },
1853 .probe = mma8452_probe,
1854 .remove = mma8452_remove,
1855 .id_table = mma8452_id,
1856 };
1857 module_i2c_driver(mma8452_driver);
1858
1859 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1860 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1861 MODULE_LICENSE("GPL");
1862