1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2020, Mellanox Technologies inc. All rights reserved. */
3
4 #include <devlink.h>
5
6 #include "fw_reset.h"
7 #include "diag/fw_tracer.h"
8 #include "lib/tout.h"
9
10 enum {
11 MLX5_FW_RESET_FLAGS_RESET_REQUESTED,
12 MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
13 MLX5_FW_RESET_FLAGS_PENDING_COMP,
14 MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS,
15 MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED
16 };
17
18 struct mlx5_fw_reset {
19 struct mlx5_core_dev *dev;
20 struct mlx5_nb nb;
21 struct workqueue_struct *wq;
22 struct work_struct fw_live_patch_work;
23 struct work_struct reset_request_work;
24 struct work_struct reset_unload_work;
25 struct work_struct reset_reload_work;
26 struct work_struct reset_now_work;
27 struct work_struct reset_abort_work;
28 unsigned long reset_flags;
29 struct timer_list timer;
30 struct completion done;
31 int ret;
32 };
33
34 enum {
35 MLX5_FW_RST_STATE_IDLE = 0,
36 MLX5_FW_RST_STATE_TOGGLE_REQ = 4,
37 };
38
39 enum {
40 MLX5_RST_STATE_BIT_NUM = 12,
41 MLX5_RST_ACK_BIT_NUM = 22,
42 };
43
mlx5_get_fw_rst_state(struct mlx5_core_dev * dev)44 static u8 mlx5_get_fw_rst_state(struct mlx5_core_dev *dev)
45 {
46 return (ioread32be(&dev->iseg->initializing) >> MLX5_RST_STATE_BIT_NUM) & 0xF;
47 }
48
mlx5_set_fw_rst_ack(struct mlx5_core_dev * dev)49 static void mlx5_set_fw_rst_ack(struct mlx5_core_dev *dev)
50 {
51 iowrite32be(BIT(MLX5_RST_ACK_BIT_NUM), &dev->iseg->initializing);
52 }
53
mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)54 static int mlx5_fw_reset_enable_remote_dev_reset_set(struct devlink *devlink, u32 id,
55 struct devlink_param_gset_ctx *ctx)
56 {
57 struct mlx5_core_dev *dev = devlink_priv(devlink);
58 struct mlx5_fw_reset *fw_reset;
59
60 fw_reset = dev->priv.fw_reset;
61
62 if (ctx->val.vbool)
63 clear_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
64 else
65 set_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags);
66 return 0;
67 }
68
mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink * devlink,u32 id,struct devlink_param_gset_ctx * ctx)69 static int mlx5_fw_reset_enable_remote_dev_reset_get(struct devlink *devlink, u32 id,
70 struct devlink_param_gset_ctx *ctx)
71 {
72 struct mlx5_core_dev *dev = devlink_priv(devlink);
73 struct mlx5_fw_reset *fw_reset;
74
75 fw_reset = dev->priv.fw_reset;
76
77 ctx->val.vbool = !test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST,
78 &fw_reset->reset_flags);
79 return 0;
80 }
81
mlx5_reg_mfrl_set(struct mlx5_core_dev * dev,u8 reset_level,u8 reset_type_sel,u8 sync_resp,bool sync_start)82 static int mlx5_reg_mfrl_set(struct mlx5_core_dev *dev, u8 reset_level,
83 u8 reset_type_sel, u8 sync_resp, bool sync_start)
84 {
85 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
86 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
87
88 MLX5_SET(mfrl_reg, in, reset_level, reset_level);
89 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
90 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_resp, sync_resp);
91 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, sync_start);
92
93 return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 1);
94 }
95
mlx5_reg_mfrl_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type,u8 * reset_state)96 static int mlx5_reg_mfrl_query(struct mlx5_core_dev *dev, u8 *reset_level,
97 u8 *reset_type, u8 *reset_state)
98 {
99 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
100 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
101 int err;
102
103 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out), MLX5_REG_MFRL, 0, 0);
104 if (err)
105 return err;
106
107 if (reset_level)
108 *reset_level = MLX5_GET(mfrl_reg, out, reset_level);
109 if (reset_type)
110 *reset_type = MLX5_GET(mfrl_reg, out, reset_type);
111 if (reset_state)
112 *reset_state = MLX5_GET(mfrl_reg, out, reset_state);
113
114 return 0;
115 }
116
mlx5_fw_reset_query(struct mlx5_core_dev * dev,u8 * reset_level,u8 * reset_type)117 int mlx5_fw_reset_query(struct mlx5_core_dev *dev, u8 *reset_level, u8 *reset_type)
118 {
119 return mlx5_reg_mfrl_query(dev, reset_level, reset_type, NULL);
120 }
121
mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev * dev,struct netlink_ext_ack * extack)122 static int mlx5_fw_reset_get_reset_state_err(struct mlx5_core_dev *dev,
123 struct netlink_ext_ack *extack)
124 {
125 u8 reset_state;
126
127 if (mlx5_reg_mfrl_query(dev, NULL, NULL, &reset_state))
128 goto out;
129
130 if (!reset_state)
131 return 0;
132
133 switch (reset_state) {
134 case MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION:
135 case MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS:
136 NL_SET_ERR_MSG_MOD(extack, "Sync reset still in progress");
137 return -EBUSY;
138 case MLX5_MFRL_REG_RESET_STATE_NEG_TIMEOUT:
139 NL_SET_ERR_MSG_MOD(extack, "Sync reset negotiation timeout");
140 return -ETIMEDOUT;
141 case MLX5_MFRL_REG_RESET_STATE_NACK:
142 NL_SET_ERR_MSG_MOD(extack, "One of the hosts disabled reset");
143 return -EPERM;
144 case MLX5_MFRL_REG_RESET_STATE_UNLOAD_TIMEOUT:
145 NL_SET_ERR_MSG_MOD(extack, "Sync reset unload timeout");
146 return -ETIMEDOUT;
147 }
148
149 out:
150 NL_SET_ERR_MSG_MOD(extack, "Sync reset failed");
151 return -EIO;
152 }
153
mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev * dev,u8 reset_type_sel,struct netlink_ext_ack * extack)154 int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *dev, u8 reset_type_sel,
155 struct netlink_ext_ack *extack)
156 {
157 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
158 u32 out[MLX5_ST_SZ_DW(mfrl_reg)] = {};
159 u32 in[MLX5_ST_SZ_DW(mfrl_reg)] = {};
160 int err, rst_res;
161
162 set_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
163
164 MLX5_SET(mfrl_reg, in, reset_level, MLX5_MFRL_REG_RESET_LEVEL3);
165 MLX5_SET(mfrl_reg, in, rst_type_sel, reset_type_sel);
166 MLX5_SET(mfrl_reg, in, pci_sync_for_fw_update_start, 1);
167 err = mlx5_access_reg(dev, in, sizeof(in), out, sizeof(out),
168 MLX5_REG_MFRL, 0, 1, false);
169 if (!err)
170 return 0;
171
172 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
173 if (err == -EREMOTEIO && MLX5_CAP_MCAM_FEATURE(dev, reset_state)) {
174 rst_res = mlx5_fw_reset_get_reset_state_err(dev, extack);
175 return rst_res ? rst_res : err;
176 }
177
178 NL_SET_ERR_MSG_MOD(extack, "Sync reset command failed");
179 return mlx5_cmd_check(dev, err, in, out);
180 }
181
mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev * dev,struct netlink_ext_ack * extack)182 int mlx5_fw_reset_verify_fw_complete(struct mlx5_core_dev *dev,
183 struct netlink_ext_ack *extack)
184 {
185 u8 rst_state;
186 int err;
187
188 err = mlx5_fw_reset_get_reset_state_err(dev, extack);
189 if (err)
190 return err;
191
192 rst_state = mlx5_get_fw_rst_state(dev);
193 if (!rst_state)
194 return 0;
195
196 mlx5_core_err(dev, "Sync reset did not complete, state=%d\n", rst_state);
197 NL_SET_ERR_MSG_MOD(extack, "Sync reset did not complete successfully");
198 return rst_state;
199 }
200
mlx5_fw_reset_set_live_patch(struct mlx5_core_dev * dev)201 int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev)
202 {
203 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false);
204 }
205
mlx5_fw_reset_complete_reload(struct mlx5_core_dev * dev,bool unloaded)206 static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool unloaded)
207 {
208 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
209 struct devlink *devlink = priv_to_devlink(dev);
210
211 /* if this is the driver that initiated the fw reset, devlink completed the reload */
212 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) {
213 complete(&fw_reset->done);
214 } else {
215 if (!unloaded)
216 mlx5_unload_one(dev, false);
217 if (mlx5_health_wait_pci_up(dev))
218 mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not working\n");
219 else
220 mlx5_load_one(dev, true);
221 devl_lock(devlink);
222 devlink_remote_reload_actions_performed(devlink, 0,
223 BIT(DEVLINK_RELOAD_ACTION_DRIVER_REINIT) |
224 BIT(DEVLINK_RELOAD_ACTION_FW_ACTIVATE));
225 devl_unlock(devlink);
226 }
227 }
228
mlx5_stop_sync_reset_poll(struct mlx5_core_dev * dev)229 static void mlx5_stop_sync_reset_poll(struct mlx5_core_dev *dev)
230 {
231 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
232
233 del_timer_sync(&fw_reset->timer);
234 }
235
mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev * dev,bool poll_health)236 static int mlx5_sync_reset_clear_reset_requested(struct mlx5_core_dev *dev, bool poll_health)
237 {
238 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
239
240 if (!test_and_clear_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
241 mlx5_core_warn(dev, "Reset request was already cleared\n");
242 return -EALREADY;
243 }
244
245 mlx5_stop_sync_reset_poll(dev);
246 if (poll_health)
247 mlx5_start_health_poll(dev);
248 return 0;
249 }
250
mlx5_sync_reset_reload_work(struct work_struct * work)251 static void mlx5_sync_reset_reload_work(struct work_struct *work)
252 {
253 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
254 reset_reload_work);
255 struct mlx5_core_dev *dev = fw_reset->dev;
256
257 mlx5_sync_reset_clear_reset_requested(dev, false);
258 mlx5_enter_error_state(dev, true);
259 mlx5_fw_reset_complete_reload(dev, false);
260 }
261
262 #define MLX5_RESET_POLL_INTERVAL (HZ / 10)
poll_sync_reset(struct timer_list * t)263 static void poll_sync_reset(struct timer_list *t)
264 {
265 struct mlx5_fw_reset *fw_reset = from_timer(fw_reset, t, timer);
266 struct mlx5_core_dev *dev = fw_reset->dev;
267 u32 fatal_error;
268
269 if (!test_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags))
270 return;
271
272 fatal_error = mlx5_health_check_fatal_sensors(dev);
273
274 if (fatal_error) {
275 mlx5_core_warn(dev, "Got Device Reset\n");
276 if (!test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
277 queue_work(fw_reset->wq, &fw_reset->reset_reload_work);
278 else
279 mlx5_core_err(dev, "Device is being removed, Drop new reset work\n");
280 return;
281 }
282
283 mod_timer(&fw_reset->timer, round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL));
284 }
285
mlx5_start_sync_reset_poll(struct mlx5_core_dev * dev)286 static void mlx5_start_sync_reset_poll(struct mlx5_core_dev *dev)
287 {
288 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
289
290 timer_setup(&fw_reset->timer, poll_sync_reset, 0);
291 fw_reset->timer.expires = round_jiffies(jiffies + MLX5_RESET_POLL_INTERVAL);
292 add_timer(&fw_reset->timer);
293 }
294
mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev * dev)295 static int mlx5_fw_reset_set_reset_sync_ack(struct mlx5_core_dev *dev)
296 {
297 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 1, false);
298 }
299
mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev * dev)300 static int mlx5_fw_reset_set_reset_sync_nack(struct mlx5_core_dev *dev)
301 {
302 return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL3, 0, 2, false);
303 }
304
mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev * dev)305 static int mlx5_sync_reset_set_reset_requested(struct mlx5_core_dev *dev)
306 {
307 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
308
309 if (test_and_set_bit(MLX5_FW_RESET_FLAGS_RESET_REQUESTED, &fw_reset->reset_flags)) {
310 mlx5_core_warn(dev, "Reset request was already set\n");
311 return -EALREADY;
312 }
313 mlx5_stop_health_poll(dev, true);
314 mlx5_start_sync_reset_poll(dev);
315 return 0;
316 }
317
mlx5_fw_live_patch_event(struct work_struct * work)318 static void mlx5_fw_live_patch_event(struct work_struct *work)
319 {
320 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
321 fw_live_patch_work);
322 struct mlx5_core_dev *dev = fw_reset->dev;
323
324 mlx5_core_info(dev, "Live patch updated firmware version: %d.%d.%d\n", fw_rev_maj(dev),
325 fw_rev_min(dev), fw_rev_sub(dev));
326
327 if (mlx5_fw_tracer_reload(dev->tracer))
328 mlx5_core_err(dev, "Failed to reload FW tracer\n");
329 }
330
331 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
mlx5_check_hotplug_interrupt(struct mlx5_core_dev * dev)332 static int mlx5_check_hotplug_interrupt(struct mlx5_core_dev *dev)
333 {
334 struct pci_dev *bridge = dev->pdev->bus->self;
335 u16 reg16;
336 int err;
337
338 if (!bridge)
339 return -EOPNOTSUPP;
340
341 err = pcie_capability_read_word(bridge, PCI_EXP_SLTCTL, ®16);
342 if (err)
343 return err;
344
345 if ((reg16 & PCI_EXP_SLTCTL_HPIE) && (reg16 & PCI_EXP_SLTCTL_DLLSCE)) {
346 mlx5_core_warn(dev, "FW reset is not supported as HotPlug is enabled\n");
347 return -EOPNOTSUPP;
348 }
349
350 return 0;
351 }
352 #endif
353
mlx5_check_dev_ids(struct mlx5_core_dev * dev,u16 dev_id)354 static int mlx5_check_dev_ids(struct mlx5_core_dev *dev, u16 dev_id)
355 {
356 struct pci_bus *bridge_bus = dev->pdev->bus;
357 struct pci_dev *sdev;
358 u16 sdev_id;
359 int err;
360
361 /* Check that all functions under the pci bridge are PFs of
362 * this device otherwise fail this function.
363 */
364 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
365 err = pci_read_config_word(sdev, PCI_DEVICE_ID, &sdev_id);
366 if (err)
367 return pcibios_err_to_errno(err);
368 if (sdev_id != dev_id) {
369 mlx5_core_warn(dev, "unrecognized dev_id (0x%x)\n", sdev_id);
370 return -EPERM;
371 }
372 }
373 return 0;
374 }
375
mlx5_is_reset_now_capable(struct mlx5_core_dev * dev)376 static bool mlx5_is_reset_now_capable(struct mlx5_core_dev *dev)
377 {
378 u16 dev_id;
379 int err;
380
381 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
382 mlx5_core_warn(dev, "fast teardown is not supported by firmware\n");
383 return false;
384 }
385
386 #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE)
387 err = mlx5_check_hotplug_interrupt(dev);
388 if (err)
389 return false;
390 #endif
391
392 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
393 if (err)
394 return false;
395 return (!mlx5_check_dev_ids(dev, dev_id));
396 }
397
mlx5_sync_reset_request_event(struct work_struct * work)398 static void mlx5_sync_reset_request_event(struct work_struct *work)
399 {
400 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
401 reset_request_work);
402 struct mlx5_core_dev *dev = fw_reset->dev;
403 int err;
404
405 if (test_bit(MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, &fw_reset->reset_flags) ||
406 !mlx5_is_reset_now_capable(dev)) {
407 err = mlx5_fw_reset_set_reset_sync_nack(dev);
408 mlx5_core_warn(dev, "PCI Sync FW Update Reset Nack %s",
409 err ? "Failed" : "Sent");
410 return;
411 }
412 if (mlx5_sync_reset_set_reset_requested(dev))
413 return;
414
415 err = mlx5_fw_reset_set_reset_sync_ack(dev);
416 if (err)
417 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack Failed. Error code: %d\n", err);
418 else
419 mlx5_core_warn(dev, "PCI Sync FW Update Reset Ack. Device reset is expected.\n");
420 }
421
mlx5_pci_link_toggle(struct mlx5_core_dev * dev)422 static int mlx5_pci_link_toggle(struct mlx5_core_dev *dev)
423 {
424 struct pci_bus *bridge_bus = dev->pdev->bus;
425 struct pci_dev *bridge = bridge_bus->self;
426 unsigned long timeout;
427 struct pci_dev *sdev;
428 u16 reg16, dev_id;
429 int cap, err;
430
431 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, &dev_id);
432 if (err)
433 return pcibios_err_to_errno(err);
434 err = mlx5_check_dev_ids(dev, dev_id);
435 if (err)
436 return err;
437 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
438 if (!cap)
439 return -EOPNOTSUPP;
440
441 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
442 pci_save_state(sdev);
443 pci_cfg_access_lock(sdev);
444 }
445 /* PCI link toggle */
446 err = pcie_capability_set_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
447 if (err)
448 return pcibios_err_to_errno(err);
449 msleep(500);
450 err = pcie_capability_clear_word(bridge, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_LD);
451 if (err)
452 return pcibios_err_to_errno(err);
453
454 /* Check link */
455 if (!bridge->link_active_reporting) {
456 mlx5_core_warn(dev, "No PCI link reporting capability\n");
457 msleep(1000);
458 goto restore;
459 }
460
461 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, PCI_TOGGLE));
462 do {
463 err = pci_read_config_word(bridge, cap + PCI_EXP_LNKSTA, ®16);
464 if (err)
465 return pcibios_err_to_errno(err);
466 if (reg16 & PCI_EXP_LNKSTA_DLLLA)
467 break;
468 msleep(20);
469 } while (!time_after(jiffies, timeout));
470
471 if (reg16 & PCI_EXP_LNKSTA_DLLLA) {
472 mlx5_core_info(dev, "PCI Link up\n");
473 } else {
474 mlx5_core_err(dev, "PCI link not ready (0x%04x) after %llu ms\n",
475 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
476 err = -ETIMEDOUT;
477 goto restore;
478 }
479
480 do {
481 err = pci_read_config_word(dev->pdev, PCI_DEVICE_ID, ®16);
482 if (err)
483 return pcibios_err_to_errno(err);
484 if (reg16 == dev_id)
485 break;
486 msleep(20);
487 } while (!time_after(jiffies, timeout));
488
489 if (reg16 == dev_id) {
490 mlx5_core_info(dev, "Firmware responds to PCI config cycles again\n");
491 } else {
492 mlx5_core_err(dev, "Firmware is not responsive (0x%04x) after %llu ms\n",
493 reg16, mlx5_tout_ms(dev, PCI_TOGGLE));
494 err = -ETIMEDOUT;
495 }
496
497 restore:
498 list_for_each_entry(sdev, &bridge_bus->devices, bus_list) {
499 pci_cfg_access_unlock(sdev);
500 pci_restore_state(sdev);
501 }
502
503 return err;
504 }
505
mlx5_sync_reset_now_event(struct work_struct * work)506 static void mlx5_sync_reset_now_event(struct work_struct *work)
507 {
508 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
509 reset_now_work);
510 struct mlx5_core_dev *dev = fw_reset->dev;
511 int err;
512
513 if (mlx5_sync_reset_clear_reset_requested(dev, false))
514 return;
515
516 mlx5_core_warn(dev, "Sync Reset now. Device is going to reset.\n");
517
518 err = mlx5_cmd_fast_teardown_hca(dev);
519 if (err) {
520 mlx5_core_warn(dev, "Fast teardown failed, no reset done, err %d\n", err);
521 goto done;
522 }
523
524 err = mlx5_pci_link_toggle(dev);
525 if (err) {
526 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, no reset done, err %d\n", err);
527 set_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags);
528 }
529
530 mlx5_enter_error_state(dev, true);
531 done:
532 fw_reset->ret = err;
533 mlx5_fw_reset_complete_reload(dev, false);
534 }
535
mlx5_sync_reset_unload_event(struct work_struct * work)536 static void mlx5_sync_reset_unload_event(struct work_struct *work)
537 {
538 struct mlx5_fw_reset *fw_reset;
539 struct mlx5_core_dev *dev;
540 unsigned long timeout;
541 bool reset_action;
542 u8 rst_state;
543 int err;
544
545 fw_reset = container_of(work, struct mlx5_fw_reset, reset_unload_work);
546 dev = fw_reset->dev;
547
548 if (mlx5_sync_reset_clear_reset_requested(dev, false))
549 return;
550
551 mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n");
552
553 err = mlx5_cmd_fast_teardown_hca(dev);
554 if (err)
555 mlx5_core_warn(dev, "Fast teardown failed, unloading, err %d\n", err);
556 else
557 mlx5_enter_error_state(dev, true);
558
559 if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags))
560 mlx5_unload_one_devl_locked(dev, false);
561 else
562 mlx5_unload_one(dev, false);
563
564 mlx5_set_fw_rst_ack(dev);
565 mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n");
566
567 reset_action = false;
568 timeout = jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD));
569 do {
570 rst_state = mlx5_get_fw_rst_state(dev);
571 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ ||
572 rst_state == MLX5_FW_RST_STATE_IDLE) {
573 reset_action = true;
574 break;
575 }
576 msleep(20);
577 } while (!time_after(jiffies, timeout));
578
579 if (!reset_action) {
580 mlx5_core_err(dev, "Got timeout waiting for sync reset action, state = %u\n",
581 rst_state);
582 fw_reset->ret = -ETIMEDOUT;
583 goto done;
584 }
585
586 mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state = %u\n", rst_state);
587 if (rst_state == MLX5_FW_RST_STATE_TOGGLE_REQ) {
588 err = mlx5_pci_link_toggle(dev);
589 if (err) {
590 mlx5_core_warn(dev, "mlx5_pci_link_toggle failed, err %d\n", err);
591 fw_reset->ret = err;
592 }
593 }
594
595 done:
596 mlx5_fw_reset_complete_reload(dev, true);
597 }
598
mlx5_sync_reset_abort_event(struct work_struct * work)599 static void mlx5_sync_reset_abort_event(struct work_struct *work)
600 {
601 struct mlx5_fw_reset *fw_reset = container_of(work, struct mlx5_fw_reset,
602 reset_abort_work);
603 struct mlx5_core_dev *dev = fw_reset->dev;
604
605 if (mlx5_sync_reset_clear_reset_requested(dev, true))
606 return;
607 mlx5_core_warn(dev, "PCI Sync FW Update Reset Aborted.\n");
608 }
609
mlx5_sync_reset_events_handle(struct mlx5_fw_reset * fw_reset,struct mlx5_eqe * eqe)610 static void mlx5_sync_reset_events_handle(struct mlx5_fw_reset *fw_reset, struct mlx5_eqe *eqe)
611 {
612 struct mlx5_eqe_sync_fw_update *sync_fw_update_eqe;
613 u8 sync_event_rst_type;
614
615 sync_fw_update_eqe = &eqe->data.sync_fw_update;
616 sync_event_rst_type = sync_fw_update_eqe->sync_rst_state & SYNC_RST_STATE_MASK;
617 switch (sync_event_rst_type) {
618 case MLX5_SYNC_RST_STATE_RESET_REQUEST:
619 queue_work(fw_reset->wq, &fw_reset->reset_request_work);
620 break;
621 case MLX5_SYNC_RST_STATE_RESET_UNLOAD:
622 queue_work(fw_reset->wq, &fw_reset->reset_unload_work);
623 break;
624 case MLX5_SYNC_RST_STATE_RESET_NOW:
625 queue_work(fw_reset->wq, &fw_reset->reset_now_work);
626 break;
627 case MLX5_SYNC_RST_STATE_RESET_ABORT:
628 queue_work(fw_reset->wq, &fw_reset->reset_abort_work);
629 break;
630 }
631 }
632
fw_reset_event_notifier(struct notifier_block * nb,unsigned long action,void * data)633 static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long action, void *data)
634 {
635 struct mlx5_fw_reset *fw_reset = mlx5_nb_cof(nb, struct mlx5_fw_reset, nb);
636 struct mlx5_eqe *eqe = data;
637
638 if (test_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags))
639 return NOTIFY_DONE;
640
641 switch (eqe->sub_type) {
642 case MLX5_GENERAL_SUBTYPE_FW_LIVE_PATCH_EVENT:
643 queue_work(fw_reset->wq, &fw_reset->fw_live_patch_work);
644 break;
645 case MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT:
646 mlx5_sync_reset_events_handle(fw_reset, eqe);
647 break;
648 default:
649 return NOTIFY_DONE;
650 }
651
652 return NOTIFY_OK;
653 }
654
mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev * dev)655 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
656 {
657 unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
658 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
659 unsigned long timeout;
660 int err;
661
662 if (MLX5_CAP_GEN(dev, pci_sync_for_fw_update_with_driver_unload))
663 pci_sync_update_timeout += mlx5_tout_ms(dev, RESET_UNLOAD);
664 timeout = msecs_to_jiffies(pci_sync_update_timeout);
665 if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
666 mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
667 pci_sync_update_timeout / 1000);
668 err = -ETIMEDOUT;
669 goto out;
670 }
671 err = fw_reset->ret;
672 if (test_and_clear_bit(MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, &fw_reset->reset_flags)) {
673 mlx5_unload_one_devl_locked(dev, false);
674 mlx5_load_one_devl_locked(dev, true);
675 }
676 out:
677 clear_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags);
678 return err;
679 }
680
mlx5_fw_reset_events_start(struct mlx5_core_dev * dev)681 void mlx5_fw_reset_events_start(struct mlx5_core_dev *dev)
682 {
683 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
684
685 if (!fw_reset)
686 return;
687
688 MLX5_NB_INIT(&fw_reset->nb, fw_reset_event_notifier, GENERAL_EVENT);
689 mlx5_eq_notifier_register(dev, &fw_reset->nb);
690 }
691
mlx5_fw_reset_events_stop(struct mlx5_core_dev * dev)692 void mlx5_fw_reset_events_stop(struct mlx5_core_dev *dev)
693 {
694 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
695
696 if (!fw_reset)
697 return;
698
699 mlx5_eq_notifier_unregister(dev, &fw_reset->nb);
700 }
701
mlx5_drain_fw_reset(struct mlx5_core_dev * dev)702 void mlx5_drain_fw_reset(struct mlx5_core_dev *dev)
703 {
704 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
705
706 if (!fw_reset)
707 return;
708
709 set_bit(MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, &fw_reset->reset_flags);
710 cancel_work_sync(&fw_reset->fw_live_patch_work);
711 cancel_work_sync(&fw_reset->reset_request_work);
712 cancel_work_sync(&fw_reset->reset_unload_work);
713 cancel_work_sync(&fw_reset->reset_reload_work);
714 cancel_work_sync(&fw_reset->reset_now_work);
715 cancel_work_sync(&fw_reset->reset_abort_work);
716 }
717
718 static const struct devlink_param mlx5_fw_reset_devlink_params[] = {
719 DEVLINK_PARAM_GENERIC(ENABLE_REMOTE_DEV_RESET, BIT(DEVLINK_PARAM_CMODE_RUNTIME),
720 mlx5_fw_reset_enable_remote_dev_reset_get,
721 mlx5_fw_reset_enable_remote_dev_reset_set, NULL),
722 };
723
mlx5_fw_reset_init(struct mlx5_core_dev * dev)724 int mlx5_fw_reset_init(struct mlx5_core_dev *dev)
725 {
726 struct mlx5_fw_reset *fw_reset;
727 int err;
728
729 if (!MLX5_CAP_MCAM_REG(dev, mfrl))
730 return 0;
731
732 fw_reset = kzalloc(sizeof(*fw_reset), GFP_KERNEL);
733 if (!fw_reset)
734 return -ENOMEM;
735 fw_reset->wq = create_singlethread_workqueue("mlx5_fw_reset_events");
736 if (!fw_reset->wq) {
737 kfree(fw_reset);
738 return -ENOMEM;
739 }
740
741 fw_reset->dev = dev;
742 dev->priv.fw_reset = fw_reset;
743
744 err = devl_params_register(priv_to_devlink(dev),
745 mlx5_fw_reset_devlink_params,
746 ARRAY_SIZE(mlx5_fw_reset_devlink_params));
747 if (err) {
748 destroy_workqueue(fw_reset->wq);
749 kfree(fw_reset);
750 return err;
751 }
752
753 INIT_WORK(&fw_reset->fw_live_patch_work, mlx5_fw_live_patch_event);
754 INIT_WORK(&fw_reset->reset_request_work, mlx5_sync_reset_request_event);
755 INIT_WORK(&fw_reset->reset_unload_work, mlx5_sync_reset_unload_event);
756 INIT_WORK(&fw_reset->reset_reload_work, mlx5_sync_reset_reload_work);
757 INIT_WORK(&fw_reset->reset_now_work, mlx5_sync_reset_now_event);
758 INIT_WORK(&fw_reset->reset_abort_work, mlx5_sync_reset_abort_event);
759
760 init_completion(&fw_reset->done);
761 return 0;
762 }
763
mlx5_fw_reset_cleanup(struct mlx5_core_dev * dev)764 void mlx5_fw_reset_cleanup(struct mlx5_core_dev *dev)
765 {
766 struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
767
768 if (!fw_reset)
769 return;
770
771 devl_params_unregister(priv_to_devlink(dev),
772 mlx5_fw_reset_devlink_params,
773 ARRAY_SIZE(mlx5_fw_reset_devlink_params));
774 destroy_workqueue(fw_reset->wq);
775 kfree(dev->priv.fw_reset);
776 }
777