1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2021 MediaTek Inc.
4 */
5
6 #include <drm/drm_fourcc.h>
7 #include <drm/drm_framebuffer.h>
8 #include <linux/clk.h>
9 #include <linux/component.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/platform_device.h>
13 #include <linux/reset.h>
14 #include <linux/soc/mediatek/mtk-cmdq.h>
15 #include <linux/soc/mediatek/mtk-mmsys.h>
16
17 #include "mtk_drm_crtc.h"
18 #include "mtk_drm_ddp_comp.h"
19 #include "mtk_drm_drv.h"
20 #include "mtk_ethdr.h"
21
22 #define MIX_INTEN 0x4
23 #define MIX_FME_CPL_INTEN BIT(1)
24 #define MIX_INTSTA 0x8
25 #define MIX_EN 0xc
26 #define MIX_RST 0x14
27 #define MIX_ROI_SIZE 0x18
28 #define MIX_DATAPATH_CON 0x1c
29 #define OUTPUT_NO_RND BIT(3)
30 #define SOURCE_RGB_SEL BIT(7)
31 #define BACKGROUND_RELAY (4 << 9)
32 #define MIX_ROI_BGCLR 0x20
33 #define BGCLR_BLACK 0xff000000
34 #define MIX_SRC_CON 0x24
35 #define MIX_SRC_L0_EN BIT(0)
36 #define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
37 #define NON_PREMULTI_SOURCE (2 << 12)
38 #define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
39 #define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
40 #define MIX_FUNC_DCM0 0x120
41 #define MIX_FUNC_DCM1 0x124
42 #define MIX_FUNC_DCM_ENABLE 0xffffffff
43
44 #define HDR_VDO_FE_0804_HDR_DM_FE 0x804
45 #define HDR_VDO_FE_0804_BYPASS_ALL 0xfd
46 #define HDR_GFX_FE_0204_GFX_HDR_FE 0x204
47 #define HDR_GFX_FE_0204_BYPASS_ALL 0xfd
48 #define HDR_VDO_BE_0204_VDO_DM_BE 0x204
49 #define HDR_VDO_BE_0204_BYPASS_ALL 0x7e
50
51 #define MIXER_INX_MODE_BYPASS 0
52 #define MIXER_INX_MODE_EVEN_EXTEND 1
53 #define MIXER_ALPHA_AEN BIT(8)
54 #define MIXER_ALPHA 0xff
55 #define ETHDR_CLK_NUM 13
56
57 enum mtk_ethdr_comp_id {
58 ETHDR_MIXER,
59 ETHDR_VDO_FE0,
60 ETHDR_VDO_FE1,
61 ETHDR_GFX_FE0,
62 ETHDR_GFX_FE1,
63 ETHDR_VDO_BE,
64 ETHDR_ADL_DS,
65 ETHDR_ID_MAX
66 };
67
68 struct mtk_ethdr_comp {
69 struct device *dev;
70 void __iomem *regs;
71 struct cmdq_client_reg cmdq_base;
72 };
73
74 struct mtk_ethdr {
75 struct mtk_ethdr_comp ethdr_comp[ETHDR_ID_MAX];
76 struct clk_bulk_data ethdr_clk[ETHDR_CLK_NUM];
77 struct device *mmsys_dev;
78 void (*vblank_cb)(void *data);
79 void *vblank_cb_data;
80 int irq;
81 struct reset_control *reset_ctl;
82 };
83
84 static const char * const ethdr_clk_str[] = {
85 "ethdr_top",
86 "mixer",
87 "vdo_fe0",
88 "vdo_fe1",
89 "gfx_fe0",
90 "gfx_fe1",
91 "vdo_be",
92 "adl_ds",
93 "vdo_fe0_async",
94 "vdo_fe1_async",
95 "gfx_fe0_async",
96 "gfx_fe1_async",
97 "vdo_be_async",
98 };
99
mtk_ethdr_register_vblank_cb(struct device * dev,void (* vblank_cb)(void *),void * vblank_cb_data)100 void mtk_ethdr_register_vblank_cb(struct device *dev,
101 void (*vblank_cb)(void *),
102 void *vblank_cb_data)
103 {
104 struct mtk_ethdr *priv = dev_get_drvdata(dev);
105
106 priv->vblank_cb = vblank_cb;
107 priv->vblank_cb_data = vblank_cb_data;
108 }
109
mtk_ethdr_unregister_vblank_cb(struct device * dev)110 void mtk_ethdr_unregister_vblank_cb(struct device *dev)
111 {
112 struct mtk_ethdr *priv = dev_get_drvdata(dev);
113
114 priv->vblank_cb = NULL;
115 priv->vblank_cb_data = NULL;
116 }
117
mtk_ethdr_enable_vblank(struct device * dev)118 void mtk_ethdr_enable_vblank(struct device *dev)
119 {
120 struct mtk_ethdr *priv = dev_get_drvdata(dev);
121
122 writel(MIX_FME_CPL_INTEN, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
123 }
124
mtk_ethdr_disable_vblank(struct device * dev)125 void mtk_ethdr_disable_vblank(struct device *dev)
126 {
127 struct mtk_ethdr *priv = dev_get_drvdata(dev);
128
129 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTEN);
130 }
131
mtk_ethdr_irq_handler(int irq,void * dev_id)132 static irqreturn_t mtk_ethdr_irq_handler(int irq, void *dev_id)
133 {
134 struct mtk_ethdr *priv = dev_id;
135
136 writel(0x0, priv->ethdr_comp[ETHDR_MIXER].regs + MIX_INTSTA);
137
138 if (!priv->vblank_cb)
139 return IRQ_NONE;
140
141 priv->vblank_cb(priv->vblank_cb_data);
142
143 return IRQ_HANDLED;
144 }
145
mtk_ethdr_layer_config(struct device * dev,unsigned int idx,struct mtk_plane_state * state,struct cmdq_pkt * cmdq_pkt)146 void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
147 struct mtk_plane_state *state,
148 struct cmdq_pkt *cmdq_pkt)
149 {
150 struct mtk_ethdr *priv = dev_get_drvdata(dev);
151 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
152 struct mtk_plane_pending_state *pending = &state->pending;
153 unsigned int offset = (pending->x & 1) << 31 | pending->y << 16 | pending->x;
154 unsigned int align_width = ALIGN_DOWN(pending->width, 2);
155 unsigned int alpha_con = 0;
156 bool replace_src_a = false;
157
158 dev_dbg(dev, "%s+ idx:%d", __func__, idx);
159
160 if (idx >= 4)
161 return;
162
163 if (!pending->enable || !pending->width || !pending->height) {
164 /*
165 * instead of disabling layer with MIX_SRC_CON directly
166 * set the size to 0 to avoid screen shift due to mixer
167 * mode switch (hardware behavior)
168 */
169 mtk_ddp_write(cmdq_pkt, 0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(idx));
170 return;
171 }
172
173 if (state->base.fb && state->base.fb->format->has_alpha)
174 alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
175
176 if (state->base.fb && !state->base.fb->format->has_alpha) {
177 /*
178 * Mixer doesn't support CONST_BLD mode,
179 * use a trick to make the output equivalent
180 */
181 replace_src_a = true;
182 }
183
184 mtk_mmsys_mixer_in_config(priv->mmsys_dev, idx + 1, replace_src_a,
185 MIXER_ALPHA,
186 pending->x & 1 ? MIXER_INX_MODE_EVEN_EXTEND :
187 MIXER_INX_MODE_BYPASS, align_width / 2 - 1, cmdq_pkt);
188
189 mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
190 mixer->regs, MIX_L_SRC_SIZE(idx));
191 mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
192 mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
193 0x1ff);
194 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
195 BIT(idx));
196 }
197
mtk_ethdr_config(struct device * dev,unsigned int w,unsigned int h,unsigned int vrefresh,unsigned int bpc,struct cmdq_pkt * cmdq_pkt)198 void mtk_ethdr_config(struct device *dev, unsigned int w,
199 unsigned int h, unsigned int vrefresh,
200 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
201 {
202 struct mtk_ethdr *priv = dev_get_drvdata(dev);
203 struct mtk_ethdr_comp *vdo_fe0 = &priv->ethdr_comp[ETHDR_VDO_FE0];
204 struct mtk_ethdr_comp *vdo_fe1 = &priv->ethdr_comp[ETHDR_VDO_FE1];
205 struct mtk_ethdr_comp *gfx_fe0 = &priv->ethdr_comp[ETHDR_GFX_FE0];
206 struct mtk_ethdr_comp *gfx_fe1 = &priv->ethdr_comp[ETHDR_GFX_FE1];
207 struct mtk_ethdr_comp *vdo_be = &priv->ethdr_comp[ETHDR_VDO_BE];
208 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
209
210 dev_dbg(dev, "%s-w:%d, h:%d\n", __func__, w, h);
211
212 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe0->cmdq_base,
213 vdo_fe0->regs, HDR_VDO_FE_0804_HDR_DM_FE);
214
215 mtk_ddp_write(cmdq_pkt, HDR_VDO_FE_0804_BYPASS_ALL, &vdo_fe1->cmdq_base,
216 vdo_fe1->regs, HDR_VDO_FE_0804_HDR_DM_FE);
217
218 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe0->cmdq_base,
219 gfx_fe0->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
220
221 mtk_ddp_write(cmdq_pkt, HDR_GFX_FE_0204_BYPASS_ALL, &gfx_fe1->cmdq_base,
222 gfx_fe1->regs, HDR_GFX_FE_0204_GFX_HDR_FE);
223
224 mtk_ddp_write(cmdq_pkt, HDR_VDO_BE_0204_BYPASS_ALL, &vdo_be->cmdq_base,
225 vdo_be->regs, HDR_VDO_BE_0204_VDO_DM_BE);
226
227 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM0);
228 mtk_ddp_write(cmdq_pkt, MIX_FUNC_DCM_ENABLE, &mixer->cmdq_base, mixer->regs, MIX_FUNC_DCM1);
229 mtk_ddp_write(cmdq_pkt, h << 16 | w, &mixer->cmdq_base, mixer->regs, MIX_ROI_SIZE);
230 mtk_ddp_write(cmdq_pkt, BGCLR_BLACK, &mixer->cmdq_base, mixer->regs, MIX_ROI_BGCLR);
231 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
232 MIX_L_SRC_CON(0));
233 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
234 MIX_L_SRC_CON(1));
235 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
236 MIX_L_SRC_CON(2));
237 mtk_ddp_write(cmdq_pkt, NON_PREMULTI_SOURCE, &mixer->cmdq_base, mixer->regs,
238 MIX_L_SRC_CON(3));
239 mtk_ddp_write(cmdq_pkt, 0x0, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_SIZE(0));
240 mtk_ddp_write(cmdq_pkt, OUTPUT_NO_RND | SOURCE_RGB_SEL | BACKGROUND_RELAY,
241 &mixer->cmdq_base, mixer->regs, MIX_DATAPATH_CON);
242 mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs,
243 MIX_SRC_CON, MIX_SRC_L0_EN);
244
245 mtk_mmsys_hdr_config(priv->mmsys_dev, w / 2, h, cmdq_pkt);
246 mtk_mmsys_mixer_in_channel_swap(priv->mmsys_dev, 4, 0, cmdq_pkt);
247 }
248
mtk_ethdr_start(struct device * dev)249 void mtk_ethdr_start(struct device *dev)
250 {
251 struct mtk_ethdr *priv = dev_get_drvdata(dev);
252 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
253
254 writel(1, mixer->regs + MIX_EN);
255 }
256
mtk_ethdr_stop(struct device * dev)257 void mtk_ethdr_stop(struct device *dev)
258 {
259 struct mtk_ethdr *priv = dev_get_drvdata(dev);
260 struct mtk_ethdr_comp *mixer = &priv->ethdr_comp[ETHDR_MIXER];
261
262 writel(0, mixer->regs + MIX_EN);
263 writel(1, mixer->regs + MIX_RST);
264 reset_control_reset(priv->reset_ctl);
265 writel(0, mixer->regs + MIX_RST);
266 }
267
mtk_ethdr_clk_enable(struct device * dev)268 int mtk_ethdr_clk_enable(struct device *dev)
269 {
270 int ret;
271 struct mtk_ethdr *priv = dev_get_drvdata(dev);
272
273 ret = clk_bulk_prepare_enable(ETHDR_CLK_NUM, priv->ethdr_clk);
274 if (ret)
275 dev_err(dev,
276 "ethdr_clk prepare enable failed\n");
277 return ret;
278 }
279
mtk_ethdr_clk_disable(struct device * dev)280 void mtk_ethdr_clk_disable(struct device *dev)
281 {
282 struct mtk_ethdr *priv = dev_get_drvdata(dev);
283
284 clk_bulk_disable_unprepare(ETHDR_CLK_NUM, priv->ethdr_clk);
285 }
286
mtk_ethdr_bind(struct device * dev,struct device * master,void * data)287 static int mtk_ethdr_bind(struct device *dev, struct device *master,
288 void *data)
289 {
290 struct mtk_ethdr *priv = dev_get_drvdata(dev);
291
292 priv->mmsys_dev = data;
293 return 0;
294 }
295
mtk_ethdr_unbind(struct device * dev,struct device * master,void * data)296 static void mtk_ethdr_unbind(struct device *dev, struct device *master, void *data)
297 {
298 }
299
300 static const struct component_ops mtk_ethdr_component_ops = {
301 .bind = mtk_ethdr_bind,
302 .unbind = mtk_ethdr_unbind,
303 };
304
mtk_ethdr_probe(struct platform_device * pdev)305 static int mtk_ethdr_probe(struct platform_device *pdev)
306 {
307 struct device *dev = &pdev->dev;
308 struct mtk_ethdr *priv;
309 int ret;
310 int i;
311
312 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
313 if (!priv)
314 return -ENOMEM;
315
316 for (i = 0; i < ETHDR_ID_MAX; i++) {
317 priv->ethdr_comp[i].dev = dev;
318 priv->ethdr_comp[i].regs = of_iomap(dev->of_node, i);
319 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
320 ret = cmdq_dev_get_client_reg(dev,
321 &priv->ethdr_comp[i].cmdq_base, i);
322 if (ret)
323 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
324 #endif
325 dev_dbg(dev, "[DRM]regs:0x%p, node:%d\n", priv->ethdr_comp[i].regs, i);
326 }
327
328 for (i = 0; i < ETHDR_CLK_NUM; i++)
329 priv->ethdr_clk[i].id = ethdr_clk_str[i];
330 ret = devm_clk_bulk_get_optional(dev, ETHDR_CLK_NUM, priv->ethdr_clk);
331 if (ret)
332 return ret;
333
334 priv->irq = platform_get_irq(pdev, 0);
335 if (priv->irq < 0)
336 priv->irq = 0;
337
338 if (priv->irq) {
339 ret = devm_request_irq(dev, priv->irq, mtk_ethdr_irq_handler,
340 IRQF_TRIGGER_NONE, dev_name(dev), priv);
341 if (ret < 0) {
342 dev_err(dev, "Failed to request irq %d: %d\n", priv->irq, ret);
343 return ret;
344 }
345 }
346
347 priv->reset_ctl = devm_reset_control_array_get_optional_exclusive(dev);
348 if (IS_ERR(priv->reset_ctl)) {
349 dev_err_probe(dev, PTR_ERR(priv->reset_ctl), "cannot get ethdr reset control\n");
350 return PTR_ERR(priv->reset_ctl);
351 }
352
353 platform_set_drvdata(pdev, priv);
354
355 ret = component_add(dev, &mtk_ethdr_component_ops);
356 if (ret)
357 dev_notice(dev, "Failed to add component: %d\n", ret);
358
359 return ret;
360 }
361
mtk_ethdr_remove(struct platform_device * pdev)362 static int mtk_ethdr_remove(struct platform_device *pdev)
363 {
364 component_del(&pdev->dev, &mtk_ethdr_component_ops);
365 return 0;
366 }
367
368 static const struct of_device_id mtk_ethdr_driver_dt_match[] = {
369 { .compatible = "mediatek,mt8195-disp-ethdr"},
370 {},
371 };
372
373 MODULE_DEVICE_TABLE(of, mtk_ethdr_driver_dt_match);
374
375 struct platform_driver mtk_ethdr_driver = {
376 .probe = mtk_ethdr_probe,
377 .remove = mtk_ethdr_remove,
378 .driver = {
379 .name = "mediatek-disp-ethdr",
380 .owner = THIS_MODULE,
381 .of_match_table = mtk_ethdr_driver_dt_match,
382 },
383 };
384