1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ASIX AX8817X based USB 2.0 Ethernet Devices
4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
7 * Copyright (c) 2002-2003 TiVo Inc.
8 */
9
10 #include "asix.h"
11
12 #define PHY_MODE_MARVELL 0x0000
13 #define MII_MARVELL_LED_CTRL 0x0018
14 #define MII_MARVELL_STATUS 0x001b
15 #define MII_MARVELL_CTRL 0x0014
16
17 #define MARVELL_LED_MANUAL 0x0019
18
19 #define MARVELL_STATUS_HWCFG 0x0004
20
21 #define MARVELL_CTRL_TXDELAY 0x0002
22 #define MARVELL_CTRL_RXDELAY 0x0080
23
24 #define PHY_MODE_RTL8211CL 0x000C
25
26 #define AX88772A_PHY14H 0x14
27 #define AX88772A_PHY14H_DEFAULT 0x442C
28
29 #define AX88772A_PHY15H 0x15
30 #define AX88772A_PHY15H_DEFAULT 0x03C8
31
32 #define AX88772A_PHY16H 0x16
33 #define AX88772A_PHY16H_DEFAULT 0x4044
34
35 struct ax88172_int_data {
36 __le16 res1;
37 u8 link;
38 __le16 res2;
39 u8 status;
40 __le16 res3;
41 } __packed;
42
asix_status(struct usbnet * dev,struct urb * urb)43 static void asix_status(struct usbnet *dev, struct urb *urb)
44 {
45 struct ax88172_int_data *event;
46 int link;
47
48 if (urb->actual_length < 8)
49 return;
50
51 event = urb->transfer_buffer;
52 link = event->link & 0x01;
53 if (netif_carrier_ok(dev->net) != link) {
54 usbnet_link_change(dev, link, 1);
55 netdev_dbg(dev->net, "Link Status is: %d\n", link);
56 }
57 }
58
asix_set_netdev_dev_addr(struct usbnet * dev,u8 * addr)59 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
60 {
61 if (is_valid_ether_addr(addr)) {
62 eth_hw_addr_set(dev->net, addr);
63 } else {
64 netdev_info(dev->net, "invalid hw address, using random\n");
65 eth_hw_addr_random(dev->net);
66 }
67 }
68
69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
asix_get_phyid(struct usbnet * dev)70 static u32 asix_get_phyid(struct usbnet *dev)
71 {
72 int phy_reg;
73 u32 phy_id;
74 int i;
75
76 /* Poll for the rare case the FW or phy isn't ready yet. */
77 for (i = 0; i < 100; i++) {
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
79 if (phy_reg < 0)
80 return 0;
81 if (phy_reg != 0 && phy_reg != 0xFFFF)
82 break;
83 mdelay(1);
84 }
85
86 if (phy_reg <= 0 || phy_reg == 0xFFFF)
87 return 0;
88
89 phy_id = (phy_reg & 0xffff) << 16;
90
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
92 if (phy_reg < 0)
93 return 0;
94
95 phy_id |= (phy_reg & 0xffff);
96
97 return phy_id;
98 }
99
asix_get_link(struct net_device * net)100 static u32 asix_get_link(struct net_device *net)
101 {
102 struct usbnet *dev = netdev_priv(net);
103
104 return mii_link_ok(&dev->mii);
105 }
106
asix_ioctl(struct net_device * net,struct ifreq * rq,int cmd)107 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
108 {
109 struct usbnet *dev = netdev_priv(net);
110
111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
112 }
113
114 /* We need to override some ethtool_ops so we require our
115 own structure so we don't interfere with other usbnet
116 devices that may be connected at the same time. */
117 static const struct ethtool_ops ax88172_ethtool_ops = {
118 .get_drvinfo = asix_get_drvinfo,
119 .get_link = asix_get_link,
120 .get_msglevel = usbnet_get_msglevel,
121 .set_msglevel = usbnet_set_msglevel,
122 .get_wol = asix_get_wol,
123 .set_wol = asix_set_wol,
124 .get_eeprom_len = asix_get_eeprom_len,
125 .get_eeprom = asix_get_eeprom,
126 .set_eeprom = asix_set_eeprom,
127 .nway_reset = usbnet_nway_reset,
128 .get_link_ksettings = usbnet_get_link_ksettings_mii,
129 .set_link_ksettings = usbnet_set_link_ksettings_mii,
130 };
131
ax88172_set_multicast(struct net_device * net)132 static void ax88172_set_multicast(struct net_device *net)
133 {
134 struct usbnet *dev = netdev_priv(net);
135 struct asix_data *data = (struct asix_data *)&dev->data;
136 u8 rx_ctl = 0x8c;
137
138 if (net->flags & IFF_PROMISC) {
139 rx_ctl |= 0x01;
140 } else if (net->flags & IFF_ALLMULTI ||
141 netdev_mc_count(net) > AX_MAX_MCAST) {
142 rx_ctl |= 0x02;
143 } else if (netdev_mc_empty(net)) {
144 /* just broadcast and directed */
145 } else {
146 /* We use the 20 byte dev->data
147 * for our 8 byte filter buffer
148 * to avoid allocating memory that
149 * is tricky to free later */
150 struct netdev_hw_addr *ha;
151 u32 crc_bits;
152
153 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
154
155 /* Build the multicast hash filter. */
156 netdev_for_each_mc_addr(ha, net) {
157 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
158 data->multi_filter[crc_bits >> 3] |=
159 1 << (crc_bits & 7);
160 }
161
162 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
163 AX_MCAST_FILTER_SIZE, data->multi_filter);
164
165 rx_ctl |= 0x10;
166 }
167
168 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
169 }
170
ax88172_link_reset(struct usbnet * dev)171 static int ax88172_link_reset(struct usbnet *dev)
172 {
173 u8 mode;
174 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
175
176 mii_check_media(&dev->mii, 1, 1);
177 mii_ethtool_gset(&dev->mii, &ecmd);
178 mode = AX88172_MEDIUM_DEFAULT;
179
180 if (ecmd.duplex != DUPLEX_FULL)
181 mode |= ~AX88172_MEDIUM_FD;
182
183 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
184 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
185
186 asix_write_medium_mode(dev, mode, 0);
187
188 return 0;
189 }
190
191 static const struct net_device_ops ax88172_netdev_ops = {
192 .ndo_open = usbnet_open,
193 .ndo_stop = usbnet_stop,
194 .ndo_start_xmit = usbnet_start_xmit,
195 .ndo_tx_timeout = usbnet_tx_timeout,
196 .ndo_change_mtu = usbnet_change_mtu,
197 .ndo_get_stats64 = dev_get_tstats64,
198 .ndo_set_mac_address = eth_mac_addr,
199 .ndo_validate_addr = eth_validate_addr,
200 .ndo_eth_ioctl = asix_ioctl,
201 .ndo_set_rx_mode = ax88172_set_multicast,
202 };
203
asix_phy_reset(struct usbnet * dev,unsigned int reset_bits)204 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
205 {
206 unsigned int timeout = 5000;
207
208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
209
210 /* give phy_id a chance to process reset */
211 udelay(500);
212
213 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
214 while (timeout--) {
215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
216 & BMCR_RESET)
217 udelay(100);
218 else
219 return;
220 }
221
222 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
223 dev->mii.phy_id);
224 }
225
ax88172_bind(struct usbnet * dev,struct usb_interface * intf)226 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
227 {
228 int ret = 0;
229 u8 buf[ETH_ALEN] = {0};
230 int i;
231 unsigned long gpio_bits = dev->driver_info->data;
232
233 usbnet_get_endpoints(dev,intf);
234
235 /* Toggle the GPIOs in a manufacturer/model specific way */
236 for (i = 2; i >= 0; i--) {
237 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
238 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
239 if (ret < 0)
240 goto out;
241 msleep(5);
242 }
243
244 ret = asix_write_rx_ctl(dev, 0x80, 0);
245 if (ret < 0)
246 goto out;
247
248 /* Get the MAC address */
249 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
250 0, 0, ETH_ALEN, buf, 0);
251 if (ret < 0) {
252 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
253 ret);
254 goto out;
255 }
256
257 asix_set_netdev_dev_addr(dev, buf);
258
259 /* Initialize MII structure */
260 dev->mii.dev = dev->net;
261 dev->mii.mdio_read = asix_mdio_read;
262 dev->mii.mdio_write = asix_mdio_write;
263 dev->mii.phy_id_mask = 0x3f;
264 dev->mii.reg_num_mask = 0x1f;
265
266 dev->mii.phy_id = asix_read_phy_addr(dev, true);
267 if (dev->mii.phy_id < 0)
268 return dev->mii.phy_id;
269
270 dev->net->netdev_ops = &ax88172_netdev_ops;
271 dev->net->ethtool_ops = &ax88172_ethtool_ops;
272 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
273 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
274
275 asix_phy_reset(dev, BMCR_RESET);
276 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
277 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
278 mii_nway_restart(&dev->mii);
279
280 return 0;
281
282 out:
283 return ret;
284 }
285
ax88772_ethtool_get_strings(struct net_device * netdev,u32 sset,u8 * data)286 static void ax88772_ethtool_get_strings(struct net_device *netdev, u32 sset,
287 u8 *data)
288 {
289 switch (sset) {
290 case ETH_SS_TEST:
291 net_selftest_get_strings(data);
292 break;
293 }
294 }
295
ax88772_ethtool_get_sset_count(struct net_device * ndev,int sset)296 static int ax88772_ethtool_get_sset_count(struct net_device *ndev, int sset)
297 {
298 switch (sset) {
299 case ETH_SS_TEST:
300 return net_selftest_get_count();
301 default:
302 return -EOPNOTSUPP;
303 }
304 }
305
ax88772_ethtool_get_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)306 static void ax88772_ethtool_get_pauseparam(struct net_device *ndev,
307 struct ethtool_pauseparam *pause)
308 {
309 struct usbnet *dev = netdev_priv(ndev);
310 struct asix_common_private *priv = dev->driver_priv;
311
312 phylink_ethtool_get_pauseparam(priv->phylink, pause);
313 }
314
ax88772_ethtool_set_pauseparam(struct net_device * ndev,struct ethtool_pauseparam * pause)315 static int ax88772_ethtool_set_pauseparam(struct net_device *ndev,
316 struct ethtool_pauseparam *pause)
317 {
318 struct usbnet *dev = netdev_priv(ndev);
319 struct asix_common_private *priv = dev->driver_priv;
320
321 return phylink_ethtool_set_pauseparam(priv->phylink, pause);
322 }
323
324 static const struct ethtool_ops ax88772_ethtool_ops = {
325 .get_drvinfo = asix_get_drvinfo,
326 .get_link = usbnet_get_link,
327 .get_msglevel = usbnet_get_msglevel,
328 .set_msglevel = usbnet_set_msglevel,
329 .get_wol = asix_get_wol,
330 .set_wol = asix_set_wol,
331 .get_eeprom_len = asix_get_eeprom_len,
332 .get_eeprom = asix_get_eeprom,
333 .set_eeprom = asix_set_eeprom,
334 .nway_reset = phy_ethtool_nway_reset,
335 .get_link_ksettings = phy_ethtool_get_link_ksettings,
336 .set_link_ksettings = phy_ethtool_set_link_ksettings,
337 .self_test = net_selftest,
338 .get_strings = ax88772_ethtool_get_strings,
339 .get_sset_count = ax88772_ethtool_get_sset_count,
340 .get_pauseparam = ax88772_ethtool_get_pauseparam,
341 .set_pauseparam = ax88772_ethtool_set_pauseparam,
342 };
343
ax88772_reset(struct usbnet * dev)344 static int ax88772_reset(struct usbnet *dev)
345 {
346 struct asix_data *data = (struct asix_data *)&dev->data;
347 struct asix_common_private *priv = dev->driver_priv;
348 int ret;
349
350 /* Rewrite MAC address */
351 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
352 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
353 ETH_ALEN, data->mac_addr, 0);
354 if (ret < 0)
355 goto out;
356
357 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
358 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
359 if (ret < 0)
360 goto out;
361
362 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
363 if (ret < 0)
364 goto out;
365
366 phylink_start(priv->phylink);
367
368 return 0;
369
370 out:
371 return ret;
372 }
373
ax88772_hw_reset(struct usbnet * dev,int in_pm)374 static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
375 {
376 struct asix_data *data = (struct asix_data *)&dev->data;
377 struct asix_common_private *priv = dev->driver_priv;
378 u16 rx_ctl;
379 int ret;
380
381 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
382 AX_GPIO_GPO2EN, 5, in_pm);
383 if (ret < 0)
384 goto out;
385
386 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy,
387 0, 0, NULL, in_pm);
388 if (ret < 0) {
389 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
390 goto out;
391 }
392
393 if (priv->embd_phy) {
394 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
395 if (ret < 0)
396 goto out;
397
398 usleep_range(10000, 11000);
399
400 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
401 if (ret < 0)
402 goto out;
403
404 msleep(60);
405
406 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
407 in_pm);
408 if (ret < 0)
409 goto out;
410 } else {
411 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
412 in_pm);
413 if (ret < 0)
414 goto out;
415 }
416
417 msleep(150);
418
419 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
420 MII_PHYSID1))){
421 ret = -EIO;
422 goto out;
423 }
424
425 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
426 if (ret < 0)
427 goto out;
428
429 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
430 if (ret < 0)
431 goto out;
432
433 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
434 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
435 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
436 if (ret < 0) {
437 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
438 goto out;
439 }
440
441 /* Rewrite MAC address */
442 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
443 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
444 ETH_ALEN, data->mac_addr, in_pm);
445 if (ret < 0)
446 goto out;
447
448 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
449 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
450 if (ret < 0)
451 goto out;
452
453 rx_ctl = asix_read_rx_ctl(dev, in_pm);
454 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
455 rx_ctl);
456
457 rx_ctl = asix_read_medium_status(dev, in_pm);
458 netdev_dbg(dev->net,
459 "Medium Status is 0x%04x after all initializations\n",
460 rx_ctl);
461
462 return 0;
463
464 out:
465 return ret;
466 }
467
ax88772a_hw_reset(struct usbnet * dev,int in_pm)468 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
469 {
470 struct asix_data *data = (struct asix_data *)&dev->data;
471 struct asix_common_private *priv = dev->driver_priv;
472 u16 rx_ctl, phy14h, phy15h, phy16h;
473 int ret;
474
475 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
476 if (ret < 0)
477 goto out;
478
479 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy |
480 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
481 if (ret < 0) {
482 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
483 goto out;
484 }
485 usleep_range(10000, 11000);
486
487 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
488 if (ret < 0)
489 goto out;
490
491 usleep_range(10000, 11000);
492
493 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
494 if (ret < 0)
495 goto out;
496
497 msleep(160);
498
499 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
500 if (ret < 0)
501 goto out;
502
503 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
504 if (ret < 0)
505 goto out;
506
507 msleep(200);
508
509 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
510 MII_PHYSID1))) {
511 ret = -1;
512 goto out;
513 }
514
515 if (priv->chipcode == AX_AX88772B_CHIPCODE) {
516 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
517 0, NULL, in_pm);
518 if (ret < 0) {
519 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
520 ret);
521 goto out;
522 }
523 } else if (priv->chipcode == AX_AX88772A_CHIPCODE) {
524 /* Check if the PHY registers have default settings */
525 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
526 AX88772A_PHY14H);
527 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
528 AX88772A_PHY15H);
529 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
530 AX88772A_PHY16H);
531
532 netdev_dbg(dev->net,
533 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
534 phy14h, phy15h, phy16h);
535
536 /* Restore PHY registers default setting if not */
537 if (phy14h != AX88772A_PHY14H_DEFAULT)
538 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
539 AX88772A_PHY14H,
540 AX88772A_PHY14H_DEFAULT);
541 if (phy15h != AX88772A_PHY15H_DEFAULT)
542 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
543 AX88772A_PHY15H,
544 AX88772A_PHY15H_DEFAULT);
545 if (phy16h != AX88772A_PHY16H_DEFAULT)
546 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
547 AX88772A_PHY16H,
548 AX88772A_PHY16H_DEFAULT);
549 }
550
551 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
552 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
553 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
554 if (ret < 0) {
555 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
556 goto out;
557 }
558
559 /* Rewrite MAC address */
560 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
561 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
562 data->mac_addr, in_pm);
563 if (ret < 0)
564 goto out;
565
566 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
567 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
568 if (ret < 0)
569 goto out;
570
571 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
572 if (ret < 0)
573 return ret;
574
575 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
576 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
577 if (ret < 0)
578 goto out;
579
580 rx_ctl = asix_read_rx_ctl(dev, in_pm);
581 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
582 rx_ctl);
583
584 rx_ctl = asix_read_medium_status(dev, in_pm);
585 netdev_dbg(dev->net,
586 "Medium Status is 0x%04x after all initializations\n",
587 rx_ctl);
588
589 return 0;
590
591 out:
592 return ret;
593 }
594
595 static const struct net_device_ops ax88772_netdev_ops = {
596 .ndo_open = usbnet_open,
597 .ndo_stop = usbnet_stop,
598 .ndo_start_xmit = usbnet_start_xmit,
599 .ndo_tx_timeout = usbnet_tx_timeout,
600 .ndo_change_mtu = usbnet_change_mtu,
601 .ndo_get_stats64 = dev_get_tstats64,
602 .ndo_set_mac_address = asix_set_mac_address,
603 .ndo_validate_addr = eth_validate_addr,
604 .ndo_eth_ioctl = phy_do_ioctl_running,
605 .ndo_set_rx_mode = asix_set_multicast,
606 };
607
ax88772_suspend(struct usbnet * dev)608 static void ax88772_suspend(struct usbnet *dev)
609 {
610 struct asix_common_private *priv = dev->driver_priv;
611 u16 medium;
612
613 if (netif_running(dev->net)) {
614 rtnl_lock();
615 phylink_suspend(priv->phylink, false);
616 rtnl_unlock();
617 }
618
619 /* Stop MAC operation */
620 medium = asix_read_medium_status(dev, 1);
621 medium &= ~AX_MEDIUM_RE;
622 asix_write_medium_mode(dev, medium, 1);
623
624 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
625 asix_read_medium_status(dev, 1));
626 }
627
asix_suspend(struct usb_interface * intf,pm_message_t message)628 static int asix_suspend(struct usb_interface *intf, pm_message_t message)
629 {
630 struct usbnet *dev = usb_get_intfdata(intf);
631 struct asix_common_private *priv = dev->driver_priv;
632
633 if (priv && priv->suspend)
634 priv->suspend(dev);
635
636 return usbnet_suspend(intf, message);
637 }
638
ax88772_resume(struct usbnet * dev)639 static void ax88772_resume(struct usbnet *dev)
640 {
641 struct asix_common_private *priv = dev->driver_priv;
642 int i;
643
644 for (i = 0; i < 3; i++)
645 if (!priv->reset(dev, 1))
646 break;
647
648 if (netif_running(dev->net)) {
649 rtnl_lock();
650 phylink_resume(priv->phylink);
651 rtnl_unlock();
652 }
653 }
654
asix_resume(struct usb_interface * intf)655 static int asix_resume(struct usb_interface *intf)
656 {
657 struct usbnet *dev = usb_get_intfdata(intf);
658 struct asix_common_private *priv = dev->driver_priv;
659
660 if (priv && priv->resume)
661 priv->resume(dev);
662
663 return usbnet_resume(intf);
664 }
665
ax88772_init_mdio(struct usbnet * dev)666 static int ax88772_init_mdio(struct usbnet *dev)
667 {
668 struct asix_common_private *priv = dev->driver_priv;
669 int ret;
670
671 priv->mdio = mdiobus_alloc();
672 if (!priv->mdio)
673 return -ENOMEM;
674
675 priv->mdio->priv = dev;
676 priv->mdio->read = &asix_mdio_bus_read;
677 priv->mdio->write = &asix_mdio_bus_write;
678 priv->mdio->name = "Asix MDIO Bus";
679 /* mii bus name is usb-<usb bus number>-<usb device number> */
680 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
681 dev->udev->bus->busnum, dev->udev->devnum);
682
683 ret = mdiobus_register(priv->mdio);
684 if (ret) {
685 netdev_err(dev->net, "Could not register MDIO bus (err %d)\n", ret);
686 mdiobus_free(priv->mdio);
687 priv->mdio = NULL;
688 }
689
690 return ret;
691 }
692
ax88772_mdio_unregister(struct asix_common_private * priv)693 static void ax88772_mdio_unregister(struct asix_common_private *priv)
694 {
695 mdiobus_unregister(priv->mdio);
696 mdiobus_free(priv->mdio);
697 }
698
ax88772_init_phy(struct usbnet * dev)699 static int ax88772_init_phy(struct usbnet *dev)
700 {
701 struct asix_common_private *priv = dev->driver_priv;
702 int ret;
703
704 priv->phydev = mdiobus_get_phy(priv->mdio, priv->phy_addr);
705 if (!priv->phydev) {
706 netdev_err(dev->net, "Could not find PHY\n");
707 return -ENODEV;
708 }
709
710 ret = phylink_connect_phy(priv->phylink, priv->phydev);
711 if (ret) {
712 netdev_err(dev->net, "Could not connect PHY\n");
713 return ret;
714 }
715
716 phy_suspend(priv->phydev);
717 priv->phydev->mac_managed_pm = true;
718
719 phy_attached_info(priv->phydev);
720
721 if (priv->embd_phy)
722 return 0;
723
724 /* In case main PHY is not the embedded PHY and MAC is RMII clock
725 * provider, we need to suspend embedded PHY by keeping PLL enabled
726 * (AX_SWRESET_IPPD == 0).
727 */
728 priv->phydev_int = mdiobus_get_phy(priv->mdio, AX_EMBD_PHY_ADDR);
729 if (!priv->phydev_int) {
730 rtnl_lock();
731 phylink_disconnect_phy(priv->phylink);
732 rtnl_unlock();
733 netdev_err(dev->net, "Could not find internal PHY\n");
734 return -ENODEV;
735 }
736
737 priv->phydev_int->mac_managed_pm = true;
738 phy_suspend(priv->phydev_int);
739
740 return 0;
741 }
742
ax88772_mac_config(struct phylink_config * config,unsigned int mode,const struct phylink_link_state * state)743 static void ax88772_mac_config(struct phylink_config *config, unsigned int mode,
744 const struct phylink_link_state *state)
745 {
746 /* Nothing to do */
747 }
748
ax88772_mac_link_down(struct phylink_config * config,unsigned int mode,phy_interface_t interface)749 static void ax88772_mac_link_down(struct phylink_config *config,
750 unsigned int mode, phy_interface_t interface)
751 {
752 struct usbnet *dev = netdev_priv(to_net_dev(config->dev));
753
754 asix_write_medium_mode(dev, 0, 0);
755 }
756
ax88772_mac_link_up(struct phylink_config * config,struct phy_device * phy,unsigned int mode,phy_interface_t interface,int speed,int duplex,bool tx_pause,bool rx_pause)757 static void ax88772_mac_link_up(struct phylink_config *config,
758 struct phy_device *phy,
759 unsigned int mode, phy_interface_t interface,
760 int speed, int duplex,
761 bool tx_pause, bool rx_pause)
762 {
763 struct usbnet *dev = netdev_priv(to_net_dev(config->dev));
764 u16 m = AX_MEDIUM_AC | AX_MEDIUM_RE;
765
766 m |= duplex ? AX_MEDIUM_FD : 0;
767
768 switch (speed) {
769 case SPEED_100:
770 m |= AX_MEDIUM_PS;
771 break;
772 case SPEED_10:
773 break;
774 default:
775 return;
776 }
777
778 if (tx_pause)
779 m |= AX_MEDIUM_TFC;
780
781 if (rx_pause)
782 m |= AX_MEDIUM_RFC;
783
784 asix_write_medium_mode(dev, m, 0);
785 }
786
787 static const struct phylink_mac_ops ax88772_phylink_mac_ops = {
788 .mac_config = ax88772_mac_config,
789 .mac_link_down = ax88772_mac_link_down,
790 .mac_link_up = ax88772_mac_link_up,
791 };
792
ax88772_phylink_setup(struct usbnet * dev)793 static int ax88772_phylink_setup(struct usbnet *dev)
794 {
795 struct asix_common_private *priv = dev->driver_priv;
796 phy_interface_t phy_if_mode;
797 struct phylink *phylink;
798
799 priv->phylink_config.dev = &dev->net->dev;
800 priv->phylink_config.type = PHYLINK_NETDEV;
801 priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
802 MAC_10 | MAC_100;
803
804 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
805 priv->phylink_config.supported_interfaces);
806 __set_bit(PHY_INTERFACE_MODE_RMII,
807 priv->phylink_config.supported_interfaces);
808
809 if (priv->embd_phy)
810 phy_if_mode = PHY_INTERFACE_MODE_INTERNAL;
811 else
812 phy_if_mode = PHY_INTERFACE_MODE_RMII;
813
814 phylink = phylink_create(&priv->phylink_config, dev->net->dev.fwnode,
815 phy_if_mode, &ax88772_phylink_mac_ops);
816 if (IS_ERR(phylink))
817 return PTR_ERR(phylink);
818
819 priv->phylink = phylink;
820 return 0;
821 }
822
ax88772_bind(struct usbnet * dev,struct usb_interface * intf)823 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
824 {
825 struct asix_common_private *priv;
826 u8 buf[ETH_ALEN] = {0};
827 int ret, i;
828
829 priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL);
830 if (!priv)
831 return -ENOMEM;
832
833 dev->driver_priv = priv;
834
835 usbnet_get_endpoints(dev, intf);
836
837 /* Maybe the boot loader passed the MAC address via device tree */
838 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) {
839 netif_dbg(dev, ifup, dev->net,
840 "MAC address read from device tree");
841 } else {
842 /* Try getting the MAC address from EEPROM */
843 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
844 for (i = 0; i < (ETH_ALEN >> 1); i++) {
845 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM,
846 0x04 + i, 0, 2, buf + i * 2,
847 0);
848 if (ret < 0)
849 break;
850 }
851 } else {
852 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
853 0, 0, ETH_ALEN, buf, 0);
854 }
855
856 if (ret < 0) {
857 netdev_dbg(dev->net, "Failed to read MAC address: %d\n",
858 ret);
859 return ret;
860 }
861 }
862
863 asix_set_netdev_dev_addr(dev, buf);
864
865 dev->net->netdev_ops = &ax88772_netdev_ops;
866 dev->net->ethtool_ops = &ax88772_ethtool_ops;
867 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
868 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
869
870 ret = asix_read_phy_addr(dev, true);
871 if (ret < 0)
872 return ret;
873
874 priv->phy_addr = ret;
875 priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR);
876
877 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1,
878 &priv->chipcode, 0);
879 if (ret < 0) {
880 netdev_dbg(dev->net, "Failed to read STATMNGSTS_REG: %d\n", ret);
881 return ret;
882 }
883
884 priv->chipcode &= AX_CHIPCODE_MASK;
885
886 priv->resume = ax88772_resume;
887 priv->suspend = ax88772_suspend;
888 if (priv->chipcode == AX_AX88772_CHIPCODE)
889 priv->reset = ax88772_hw_reset;
890 else
891 priv->reset = ax88772a_hw_reset;
892
893 ret = priv->reset(dev, 0);
894 if (ret < 0) {
895 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret);
896 return ret;
897 }
898
899 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
900 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
901 /* hard_mtu is still the default - the device does not support
902 jumbo eth frames */
903 dev->rx_urb_size = 2048;
904 }
905
906 priv->presvd_phy_bmcr = 0;
907 priv->presvd_phy_advertise = 0;
908
909 ret = ax88772_init_mdio(dev);
910 if (ret)
911 goto mdio_err;
912
913 ret = ax88772_phylink_setup(dev);
914 if (ret)
915 goto phylink_err;
916
917 ret = ax88772_init_phy(dev);
918 if (ret)
919 goto initphy_err;
920
921 return 0;
922
923 initphy_err:
924 phylink_destroy(priv->phylink);
925 phylink_err:
926 ax88772_mdio_unregister(priv);
927 mdio_err:
928 return ret;
929 }
930
ax88772_stop(struct usbnet * dev)931 static int ax88772_stop(struct usbnet *dev)
932 {
933 struct asix_common_private *priv = dev->driver_priv;
934
935 phylink_stop(priv->phylink);
936
937 return 0;
938 }
939
ax88772_unbind(struct usbnet * dev,struct usb_interface * intf)940 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
941 {
942 struct asix_common_private *priv = dev->driver_priv;
943
944 rtnl_lock();
945 phylink_disconnect_phy(priv->phylink);
946 rtnl_unlock();
947 phylink_destroy(priv->phylink);
948 ax88772_mdio_unregister(priv);
949 asix_rx_fixup_common_free(dev->driver_priv);
950 }
951
ax88178_unbind(struct usbnet * dev,struct usb_interface * intf)952 static void ax88178_unbind(struct usbnet *dev, struct usb_interface *intf)
953 {
954 asix_rx_fixup_common_free(dev->driver_priv);
955 kfree(dev->driver_priv);
956 }
957
958 static const struct ethtool_ops ax88178_ethtool_ops = {
959 .get_drvinfo = asix_get_drvinfo,
960 .get_link = asix_get_link,
961 .get_msglevel = usbnet_get_msglevel,
962 .set_msglevel = usbnet_set_msglevel,
963 .get_wol = asix_get_wol,
964 .set_wol = asix_set_wol,
965 .get_eeprom_len = asix_get_eeprom_len,
966 .get_eeprom = asix_get_eeprom,
967 .set_eeprom = asix_set_eeprom,
968 .nway_reset = usbnet_nway_reset,
969 .get_link_ksettings = usbnet_get_link_ksettings_mii,
970 .set_link_ksettings = usbnet_set_link_ksettings_mii,
971 };
972
marvell_phy_init(struct usbnet * dev)973 static int marvell_phy_init(struct usbnet *dev)
974 {
975 struct asix_data *data = (struct asix_data *)&dev->data;
976 u16 reg;
977
978 netdev_dbg(dev->net, "marvell_phy_init()\n");
979
980 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
981 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
982
983 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
984 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
985
986 if (data->ledmode) {
987 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
988 MII_MARVELL_LED_CTRL);
989 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
990
991 reg &= 0xf8ff;
992 reg |= (1 + 0x0100);
993 asix_mdio_write(dev->net, dev->mii.phy_id,
994 MII_MARVELL_LED_CTRL, reg);
995
996 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
997 MII_MARVELL_LED_CTRL);
998 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
999 }
1000
1001 return 0;
1002 }
1003
rtl8211cl_phy_init(struct usbnet * dev)1004 static int rtl8211cl_phy_init(struct usbnet *dev)
1005 {
1006 struct asix_data *data = (struct asix_data *)&dev->data;
1007
1008 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
1009
1010 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
1011 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
1012 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
1013 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
1014 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
1015
1016 if (data->ledmode == 12) {
1017 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
1018 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
1019 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
1020 }
1021
1022 return 0;
1023 }
1024
marvell_led_status(struct usbnet * dev,u16 speed)1025 static int marvell_led_status(struct usbnet *dev, u16 speed)
1026 {
1027 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
1028
1029 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
1030
1031 /* Clear out the center LED bits - 0x03F0 */
1032 reg &= 0xfc0f;
1033
1034 switch (speed) {
1035 case SPEED_1000:
1036 reg |= 0x03e0;
1037 break;
1038 case SPEED_100:
1039 reg |= 0x03b0;
1040 break;
1041 default:
1042 reg |= 0x02f0;
1043 }
1044
1045 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
1046 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
1047
1048 return 0;
1049 }
1050
ax88178_reset(struct usbnet * dev)1051 static int ax88178_reset(struct usbnet *dev)
1052 {
1053 struct asix_data *data = (struct asix_data *)&dev->data;
1054 int ret;
1055 __le16 eeprom;
1056 u8 status;
1057 int gpio0 = 0;
1058 u32 phyid;
1059
1060 ret = asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
1061 if (ret < 0) {
1062 netdev_dbg(dev->net, "Failed to read GPIOS: %d\n", ret);
1063 return ret;
1064 }
1065
1066 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
1067
1068 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
1069 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
1070 if (ret < 0) {
1071 netdev_dbg(dev->net, "Failed to read EEPROM: %d\n", ret);
1072 return ret;
1073 }
1074
1075 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
1076
1077 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
1078
1079 if (eeprom == cpu_to_le16(0xffff)) {
1080 data->phymode = PHY_MODE_MARVELL;
1081 data->ledmode = 0;
1082 gpio0 = 1;
1083 } else {
1084 data->phymode = le16_to_cpu(eeprom) & 0x7F;
1085 data->ledmode = le16_to_cpu(eeprom) >> 8;
1086 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
1087 }
1088 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
1089
1090 /* Power up external GigaPHY through AX88178 GPIO pin */
1091 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
1092 AX_GPIO_GPO1EN, 40, 0);
1093 if ((le16_to_cpu(eeprom) >> 8) != 1) {
1094 asix_write_gpio(dev, 0x003c, 30, 0);
1095 asix_write_gpio(dev, 0x001c, 300, 0);
1096 asix_write_gpio(dev, 0x003c, 30, 0);
1097 } else {
1098 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
1099 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
1100 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
1101 }
1102
1103 /* Read PHYID register *AFTER* powering up PHY */
1104 phyid = asix_get_phyid(dev);
1105 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
1106
1107 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
1108 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
1109
1110 asix_sw_reset(dev, 0, 0);
1111 msleep(150);
1112
1113 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1114 msleep(150);
1115
1116 asix_write_rx_ctl(dev, 0, 0);
1117
1118 if (data->phymode == PHY_MODE_MARVELL) {
1119 marvell_phy_init(dev);
1120 msleep(60);
1121 } else if (data->phymode == PHY_MODE_RTL8211CL)
1122 rtl8211cl_phy_init(dev);
1123
1124 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
1125 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1126 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1127 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1128 ADVERTISE_1000FULL);
1129
1130 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
1131 mii_nway_restart(&dev->mii);
1132
1133 /* Rewrite MAC address */
1134 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
1135 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
1136 data->mac_addr, 0);
1137 if (ret < 0)
1138 return ret;
1139
1140 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
1141 if (ret < 0)
1142 return ret;
1143
1144 return 0;
1145 }
1146
ax88178_link_reset(struct usbnet * dev)1147 static int ax88178_link_reset(struct usbnet *dev)
1148 {
1149 u16 mode;
1150 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
1151 struct asix_data *data = (struct asix_data *)&dev->data;
1152 u32 speed;
1153
1154 netdev_dbg(dev->net, "ax88178_link_reset()\n");
1155
1156 mii_check_media(&dev->mii, 1, 1);
1157 mii_ethtool_gset(&dev->mii, &ecmd);
1158 mode = AX88178_MEDIUM_DEFAULT;
1159 speed = ethtool_cmd_speed(&ecmd);
1160
1161 if (speed == SPEED_1000)
1162 mode |= AX_MEDIUM_GM;
1163 else if (speed == SPEED_100)
1164 mode |= AX_MEDIUM_PS;
1165 else
1166 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1167
1168 mode |= AX_MEDIUM_ENCK;
1169
1170 if (ecmd.duplex == DUPLEX_FULL)
1171 mode |= AX_MEDIUM_FD;
1172 else
1173 mode &= ~AX_MEDIUM_FD;
1174
1175 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
1176 speed, ecmd.duplex, mode);
1177
1178 asix_write_medium_mode(dev, mode, 0);
1179
1180 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1181 marvell_led_status(dev, speed);
1182
1183 return 0;
1184 }
1185
ax88178_set_mfb(struct usbnet * dev)1186 static void ax88178_set_mfb(struct usbnet *dev)
1187 {
1188 u16 mfb = AX_RX_CTL_MFB_16384;
1189 u16 rxctl;
1190 u16 medium;
1191 int old_rx_urb_size = dev->rx_urb_size;
1192
1193 if (dev->hard_mtu < 2048) {
1194 dev->rx_urb_size = 2048;
1195 mfb = AX_RX_CTL_MFB_2048;
1196 } else if (dev->hard_mtu < 4096) {
1197 dev->rx_urb_size = 4096;
1198 mfb = AX_RX_CTL_MFB_4096;
1199 } else if (dev->hard_mtu < 8192) {
1200 dev->rx_urb_size = 8192;
1201 mfb = AX_RX_CTL_MFB_8192;
1202 } else if (dev->hard_mtu < 16384) {
1203 dev->rx_urb_size = 16384;
1204 mfb = AX_RX_CTL_MFB_16384;
1205 }
1206
1207 rxctl = asix_read_rx_ctl(dev, 0);
1208 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
1209
1210 medium = asix_read_medium_status(dev, 0);
1211 if (dev->net->mtu > 1500)
1212 medium |= AX_MEDIUM_JFE;
1213 else
1214 medium &= ~AX_MEDIUM_JFE;
1215 asix_write_medium_mode(dev, medium, 0);
1216
1217 if (dev->rx_urb_size > old_rx_urb_size)
1218 usbnet_unlink_rx_urbs(dev);
1219 }
1220
ax88178_change_mtu(struct net_device * net,int new_mtu)1221 static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1222 {
1223 struct usbnet *dev = netdev_priv(net);
1224 int ll_mtu = new_mtu + net->hard_header_len + 4;
1225
1226 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
1227
1228 if ((ll_mtu % dev->maxpacket) == 0)
1229 return -EDOM;
1230
1231 net->mtu = new_mtu;
1232 dev->hard_mtu = net->mtu + net->hard_header_len;
1233 ax88178_set_mfb(dev);
1234
1235 /* max qlen depend on hard_mtu and rx_urb_size */
1236 usbnet_update_max_qlen(dev);
1237
1238 return 0;
1239 }
1240
1241 static const struct net_device_ops ax88178_netdev_ops = {
1242 .ndo_open = usbnet_open,
1243 .ndo_stop = usbnet_stop,
1244 .ndo_start_xmit = usbnet_start_xmit,
1245 .ndo_tx_timeout = usbnet_tx_timeout,
1246 .ndo_get_stats64 = dev_get_tstats64,
1247 .ndo_set_mac_address = asix_set_mac_address,
1248 .ndo_validate_addr = eth_validate_addr,
1249 .ndo_set_rx_mode = asix_set_multicast,
1250 .ndo_eth_ioctl = asix_ioctl,
1251 .ndo_change_mtu = ax88178_change_mtu,
1252 };
1253
ax88178_bind(struct usbnet * dev,struct usb_interface * intf)1254 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1255 {
1256 int ret;
1257 u8 buf[ETH_ALEN] = {0};
1258
1259 usbnet_get_endpoints(dev,intf);
1260
1261 /* Get the MAC address */
1262 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
1263 if (ret < 0) {
1264 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
1265 return ret;
1266 }
1267
1268 asix_set_netdev_dev_addr(dev, buf);
1269
1270 /* Initialize MII structure */
1271 dev->mii.dev = dev->net;
1272 dev->mii.mdio_read = asix_mdio_read;
1273 dev->mii.mdio_write = asix_mdio_write;
1274 dev->mii.phy_id_mask = 0x1f;
1275 dev->mii.reg_num_mask = 0xff;
1276 dev->mii.supports_gmii = 1;
1277
1278 dev->mii.phy_id = asix_read_phy_addr(dev, true);
1279 if (dev->mii.phy_id < 0)
1280 return dev->mii.phy_id;
1281
1282 dev->net->netdev_ops = &ax88178_netdev_ops;
1283 dev->net->ethtool_ops = &ax88178_ethtool_ops;
1284 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
1285
1286 /* Blink LEDS so users know driver saw dongle */
1287 asix_sw_reset(dev, 0, 0);
1288 msleep(150);
1289
1290 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1291 msleep(150);
1292
1293 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1294 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1295 /* hard_mtu is still the default - the device does not support
1296 jumbo eth frames */
1297 dev->rx_urb_size = 2048;
1298 }
1299
1300 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1301 if (!dev->driver_priv)
1302 return -ENOMEM;
1303
1304 return 0;
1305 }
1306
1307 static const struct driver_info ax8817x_info = {
1308 .description = "ASIX AX8817x USB 2.0 Ethernet",
1309 .bind = ax88172_bind,
1310 .status = asix_status,
1311 .link_reset = ax88172_link_reset,
1312 .reset = ax88172_link_reset,
1313 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1314 .data = 0x00130103,
1315 };
1316
1317 static const struct driver_info dlink_dub_e100_info = {
1318 .description = "DLink DUB-E100 USB Ethernet",
1319 .bind = ax88172_bind,
1320 .status = asix_status,
1321 .link_reset = ax88172_link_reset,
1322 .reset = ax88172_link_reset,
1323 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1324 .data = 0x009f9d9f,
1325 };
1326
1327 static const struct driver_info netgear_fa120_info = {
1328 .description = "Netgear FA-120 USB Ethernet",
1329 .bind = ax88172_bind,
1330 .status = asix_status,
1331 .link_reset = ax88172_link_reset,
1332 .reset = ax88172_link_reset,
1333 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1334 .data = 0x00130103,
1335 };
1336
1337 static const struct driver_info hawking_uf200_info = {
1338 .description = "Hawking UF200 USB Ethernet",
1339 .bind = ax88172_bind,
1340 .status = asix_status,
1341 .link_reset = ax88172_link_reset,
1342 .reset = ax88172_link_reset,
1343 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1344 .data = 0x001f1d1f,
1345 };
1346
1347 static const struct driver_info ax88772_info = {
1348 .description = "ASIX AX88772 USB 2.0 Ethernet",
1349 .bind = ax88772_bind,
1350 .unbind = ax88772_unbind,
1351 .reset = ax88772_reset,
1352 .stop = ax88772_stop,
1353 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET,
1354 .rx_fixup = asix_rx_fixup_common,
1355 .tx_fixup = asix_tx_fixup,
1356 };
1357
1358 static const struct driver_info ax88772b_info = {
1359 .description = "ASIX AX88772B USB 2.0 Ethernet",
1360 .bind = ax88772_bind,
1361 .unbind = ax88772_unbind,
1362 .reset = ax88772_reset,
1363 .stop = ax88772_stop,
1364 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET,
1365 .rx_fixup = asix_rx_fixup_common,
1366 .tx_fixup = asix_tx_fixup,
1367 .data = FLAG_EEPROM_MAC,
1368 };
1369
1370 static const struct driver_info lxausb_t1l_info = {
1371 .description = "Linux Automation GmbH USB 10Base-T1L",
1372 .bind = ax88772_bind,
1373 .unbind = ax88772_unbind,
1374 .reset = ax88772_reset,
1375 .stop = ax88772_stop,
1376 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET,
1377 .rx_fixup = asix_rx_fixup_common,
1378 .tx_fixup = asix_tx_fixup,
1379 .data = FLAG_EEPROM_MAC,
1380 };
1381
1382 static const struct driver_info ax88178_info = {
1383 .description = "ASIX AX88178 USB 2.0 Ethernet",
1384 .bind = ax88178_bind,
1385 .unbind = ax88178_unbind,
1386 .status = asix_status,
1387 .link_reset = ax88178_link_reset,
1388 .reset = ax88178_reset,
1389 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1390 FLAG_MULTI_PACKET,
1391 .rx_fixup = asix_rx_fixup_common,
1392 .tx_fixup = asix_tx_fixup,
1393 };
1394
1395 /*
1396 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1397 * no-name packaging.
1398 * USB device strings are:
1399 * 1: Manufacturer: USBLINK
1400 * 2: Product: HG20F9 USB2.0
1401 * 3: Serial: 000003
1402 * Appears to be compatible with Asix 88772B.
1403 */
1404 static const struct driver_info hg20f9_info = {
1405 .description = "HG20F9 USB 2.0 Ethernet",
1406 .bind = ax88772_bind,
1407 .unbind = ax88772_unbind,
1408 .reset = ax88772_reset,
1409 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_MULTI_PACKET,
1410 .rx_fixup = asix_rx_fixup_common,
1411 .tx_fixup = asix_tx_fixup,
1412 .data = FLAG_EEPROM_MAC,
1413 };
1414
1415 static const struct driver_info lyconsys_fibergecko100_info = {
1416 .description = "LyconSys FiberGecko 100 USB 2.0 to SFP Adapter",
1417 .bind = ax88178_bind,
1418 .status = asix_status,
1419 .link_reset = ax88178_link_reset,
1420 .reset = ax88178_link_reset,
1421 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1422 FLAG_MULTI_PACKET,
1423 .rx_fixup = asix_rx_fixup_common,
1424 .tx_fixup = asix_tx_fixup,
1425 .data = 0x20061201,
1426 };
1427
1428 static const struct usb_device_id products [] = {
1429 {
1430 // Linksys USB200M
1431 USB_DEVICE (0x077b, 0x2226),
1432 .driver_info = (unsigned long) &ax8817x_info,
1433 }, {
1434 // Netgear FA120
1435 USB_DEVICE (0x0846, 0x1040),
1436 .driver_info = (unsigned long) &netgear_fa120_info,
1437 }, {
1438 // DLink DUB-E100
1439 USB_DEVICE (0x2001, 0x1a00),
1440 .driver_info = (unsigned long) &dlink_dub_e100_info,
1441 }, {
1442 // Intellinet, ST Lab USB Ethernet
1443 USB_DEVICE (0x0b95, 0x1720),
1444 .driver_info = (unsigned long) &ax8817x_info,
1445 }, {
1446 // Hawking UF200, TrendNet TU2-ET100
1447 USB_DEVICE (0x07b8, 0x420a),
1448 .driver_info = (unsigned long) &hawking_uf200_info,
1449 }, {
1450 // Billionton Systems, USB2AR
1451 USB_DEVICE (0x08dd, 0x90ff),
1452 .driver_info = (unsigned long) &ax8817x_info,
1453 }, {
1454 // Billionton Systems, GUSB2AM-1G-B
1455 USB_DEVICE(0x08dd, 0x0114),
1456 .driver_info = (unsigned long) &ax88178_info,
1457 }, {
1458 // ATEN UC210T
1459 USB_DEVICE (0x0557, 0x2009),
1460 .driver_info = (unsigned long) &ax8817x_info,
1461 }, {
1462 // Buffalo LUA-U2-KTX
1463 USB_DEVICE (0x0411, 0x003d),
1464 .driver_info = (unsigned long) &ax8817x_info,
1465 }, {
1466 // Buffalo LUA-U2-GT 10/100/1000
1467 USB_DEVICE (0x0411, 0x006e),
1468 .driver_info = (unsigned long) &ax88178_info,
1469 }, {
1470 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1471 USB_DEVICE (0x6189, 0x182d),
1472 .driver_info = (unsigned long) &ax8817x_info,
1473 }, {
1474 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1475 USB_DEVICE (0x0df6, 0x0056),
1476 .driver_info = (unsigned long) &ax88178_info,
1477 }, {
1478 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1479 USB_DEVICE (0x0df6, 0x061c),
1480 .driver_info = (unsigned long) &ax88178_info,
1481 }, {
1482 // corega FEther USB2-TX
1483 USB_DEVICE (0x07aa, 0x0017),
1484 .driver_info = (unsigned long) &ax8817x_info,
1485 }, {
1486 // Surecom EP-1427X-2
1487 USB_DEVICE (0x1189, 0x0893),
1488 .driver_info = (unsigned long) &ax8817x_info,
1489 }, {
1490 // goodway corp usb gwusb2e
1491 USB_DEVICE (0x1631, 0x6200),
1492 .driver_info = (unsigned long) &ax8817x_info,
1493 }, {
1494 // JVC MP-PRX1 Port Replicator
1495 USB_DEVICE (0x04f1, 0x3008),
1496 .driver_info = (unsigned long) &ax8817x_info,
1497 }, {
1498 // Lenovo U2L100P 10/100
1499 USB_DEVICE (0x17ef, 0x7203),
1500 .driver_info = (unsigned long)&ax88772b_info,
1501 }, {
1502 // ASIX AX88772B 10/100
1503 USB_DEVICE (0x0b95, 0x772b),
1504 .driver_info = (unsigned long) &ax88772b_info,
1505 }, {
1506 // ASIX AX88772 10/100
1507 USB_DEVICE (0x0b95, 0x7720),
1508 .driver_info = (unsigned long) &ax88772_info,
1509 }, {
1510 // ASIX AX88178 10/100/1000
1511 USB_DEVICE (0x0b95, 0x1780),
1512 .driver_info = (unsigned long) &ax88178_info,
1513 }, {
1514 // Logitec LAN-GTJ/U2A
1515 USB_DEVICE (0x0789, 0x0160),
1516 .driver_info = (unsigned long) &ax88178_info,
1517 }, {
1518 // Linksys USB200M Rev 2
1519 USB_DEVICE (0x13b1, 0x0018),
1520 .driver_info = (unsigned long) &ax88772_info,
1521 }, {
1522 // 0Q0 cable ethernet
1523 USB_DEVICE (0x1557, 0x7720),
1524 .driver_info = (unsigned long) &ax88772_info,
1525 }, {
1526 // DLink DUB-E100 H/W Ver B1
1527 USB_DEVICE (0x07d1, 0x3c05),
1528 .driver_info = (unsigned long) &ax88772_info,
1529 }, {
1530 // DLink DUB-E100 H/W Ver B1 Alternate
1531 USB_DEVICE (0x2001, 0x3c05),
1532 .driver_info = (unsigned long) &ax88772_info,
1533 }, {
1534 // DLink DUB-E100 H/W Ver C1
1535 USB_DEVICE (0x2001, 0x1a02),
1536 .driver_info = (unsigned long) &ax88772_info,
1537 }, {
1538 // Linksys USB1000
1539 USB_DEVICE (0x1737, 0x0039),
1540 .driver_info = (unsigned long) &ax88178_info,
1541 }, {
1542 // IO-DATA ETG-US2
1543 USB_DEVICE (0x04bb, 0x0930),
1544 .driver_info = (unsigned long) &ax88178_info,
1545 }, {
1546 // Belkin F5D5055
1547 USB_DEVICE(0x050d, 0x5055),
1548 .driver_info = (unsigned long) &ax88178_info,
1549 }, {
1550 // Apple USB Ethernet Adapter
1551 USB_DEVICE(0x05ac, 0x1402),
1552 .driver_info = (unsigned long) &ax88772_info,
1553 }, {
1554 // Cables-to-Go USB Ethernet Adapter
1555 USB_DEVICE(0x0b95, 0x772a),
1556 .driver_info = (unsigned long) &ax88772_info,
1557 }, {
1558 // ABOCOM for pci
1559 USB_DEVICE(0x14ea, 0xab11),
1560 .driver_info = (unsigned long) &ax88178_info,
1561 }, {
1562 // ASIX 88772a
1563 USB_DEVICE(0x0db0, 0xa877),
1564 .driver_info = (unsigned long) &ax88772_info,
1565 }, {
1566 // Asus USB Ethernet Adapter
1567 USB_DEVICE (0x0b95, 0x7e2b),
1568 .driver_info = (unsigned long)&ax88772b_info,
1569 }, {
1570 /* ASIX 88172a demo board */
1571 USB_DEVICE(0x0b95, 0x172a),
1572 .driver_info = (unsigned long) &ax88172a_info,
1573 }, {
1574 /*
1575 * USBLINK HG20F9 "USB 2.0 LAN"
1576 * Appears to have gazumped Linksys's manufacturer ID but
1577 * doesn't (yet) conflict with any known Linksys product.
1578 */
1579 USB_DEVICE(0x066b, 0x20f9),
1580 .driver_info = (unsigned long) &hg20f9_info,
1581 }, {
1582 // Linux Automation GmbH USB 10Base-T1L
1583 USB_DEVICE(0x33f7, 0x0004),
1584 .driver_info = (unsigned long) &lxausb_t1l_info,
1585 }, {
1586 /* LyconSys FiberGecko 100 */
1587 USB_DEVICE(0x1d2a, 0x0801),
1588 .driver_info = (unsigned long) &lyconsys_fibergecko100_info,
1589 },
1590 { }, // END
1591 };
1592 MODULE_DEVICE_TABLE(usb, products);
1593
1594 static struct usb_driver asix_driver = {
1595 .name = DRIVER_NAME,
1596 .id_table = products,
1597 .probe = usbnet_probe,
1598 .suspend = asix_suspend,
1599 .resume = asix_resume,
1600 .reset_resume = asix_resume,
1601 .disconnect = usbnet_disconnect,
1602 .supports_autosuspend = 1,
1603 .disable_hub_initiated_lpm = 1,
1604 };
1605
1606 module_usb_driver(asix_driver);
1607
1608 MODULE_AUTHOR("David Hollis");
1609 MODULE_VERSION(DRIVER_VERSION);
1610 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1611 MODULE_LICENSE("GPL");
1612
1613