xref: /openbmc/qemu/hw/net/fsl_etsec/registers.h (revision 59b5552f)
1 /*
2  * QEMU Freescale eTSEC Emulator
3  *
4  * Copyright (c) 2011-2013 AdaCore
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #ifndef ETSEC_REGISTERS_H
26 #define ETSEC_REGISTERS_H
27 
28 enum eTSEC_Register_Access_Type {
29     ACC_RW      = 1,            /* Read/Write */
30     ACC_RO      = 2,            /* Read Only */
31     ACC_WO      = 3,            /* Write Only */
32     ACC_W1C     = 4,            /* Write 1 to clear */
33     ACC_UNKNOWN = 5             /* Unknown register*/
34 };
35 
36 typedef struct eTSEC_Register_Definition {
37     uint32_t                         offset;
38     const char                      *name;
39     const char                      *desc;
40     enum eTSEC_Register_Access_Type  access;
41     uint32_t                         reset;
42 } eTSEC_Register_Definition;
43 
44 extern const eTSEC_Register_Definition eTSEC_registers_def[];
45 
46 #define DMACTRL_LE  (1 << 15)
47 #define DMACTRL_GRS (1 <<  4)
48 #define DMACTRL_GTS (1 <<  3)
49 #define DMACTRL_WOP (1 <<  0)
50 
51 #define IEVENT_PERR  (1 <<  0)
52 #define IEVENT_DPE   (1 <<  1)
53 #define IEVENT_FIQ   (1 <<  2)
54 #define IEVENT_FIR   (1 <<  3)
55 #define IEVENT_FGPI  (1 <<  4)
56 #define IEVENT_RXF   (1 <<  7)
57 #define IEVENT_GRSC  (1 <<  8)
58 #define IEVENT_MMRW  (1 <<  9)
59 #define IEVENT_MMRD  (1 << 10)
60 #define IEVENT_MAG   (1 << 11)
61 #define IEVENT_RXB   (1 << 15)
62 #define IEVENT_XFUN  (1 << 16)
63 #define IEVENT_CRL   (1 << 17)
64 #define IEVENT_LC    (1 << 18)
65 #define IEVENT_TXF   (1 << 20)
66 #define IEVENT_TXB   (1 << 21)
67 #define IEVENT_TXE   (1 << 22)
68 #define IEVENT_TXC   (1 << 23)
69 #define IEVENT_BABT  (1 << 24)
70 #define IEVENT_GTSC  (1 << 25)
71 #define IEVENT_MSRO  (1 << 26)
72 #define IEVENT_EBERR (1 << 28)
73 #define IEVENT_BSY   (1 << 29)
74 #define IEVENT_RXC   (1 << 30)
75 #define IEVENT_BABR  (1 << 31)
76 
77 /* Mapping between interrupt pin and interrupt flags */
78 #define IEVENT_RX_MASK (IEVENT_RXF | IEVENT_RXB)
79 #define IEVENT_TX_MASK (IEVENT_TXF | IEVENT_TXB)
80 #define IEVENT_ERR_MASK (IEVENT_MAG | IEVENT_GTSC | IEVENT_GRSC | IEVENT_TXC | \
81     IEVENT_RXC | IEVENT_BABR | IEVENT_BABT | IEVENT_LC | \
82     IEVENT_CRL | IEVENT_FGPI | IEVENT_FIR | IEVENT_FIQ | \
83     IEVENT_DPE | IEVENT_PERR | IEVENT_EBERR | IEVENT_TXE | \
84     IEVENT_XFUN | IEVENT_BSY | IEVENT_MSRO | IEVENT_MMRD | \
85     IEVENT_MMRW)
86 
87 #define IMASK_RXFEN  (1 <<  7)
88 #define IMASK_GRSCEN (1 <<  8)
89 #define IMASK_RXBEN  (1 << 15)
90 #define IMASK_TXFEN  (1 << 20)
91 #define IMASK_TXBEN  (1 << 21)
92 #define IMASK_GTSCEN (1 << 25)
93 
94 #define MACCFG1_TX_EN  (1 << 0)
95 #define MACCFG1_RX_EN  (1 << 2)
96 
97 #define MACCFG2_CRC_EN  (1 << 1)
98 #define MACCFG2_PADCRC  (1 << 2)
99 
100 #define MIIMCOM_READ (1 << 0)
101 #define MIIMCOM_SCAN (1 << 1)
102 
103 #define RCTRL_PRSDEP_MASK   (0x3)
104 #define RCTRL_PRSDEP_OFFSET (6)
105 #define RCTRL_RSF           (1 << 2)
106 
107 /* Index of each register */
108 
109 #define TSEC_ID      (0x000 / 4)
110 #define TSEC_ID2     (0x004 / 4)
111 #define IEVENT       (0x010 / 4)
112 #define IMASK        (0x014 / 4)
113 #define EDIS         (0x018 / 4)
114 #define ECNTRL       (0x020 / 4)
115 #define PTV          (0x028 / 4)
116 #define DMACTRL      (0x02C / 4)
117 #define TBIPA        (0x030 / 4)
118 #define TCTRL        (0x100 / 4)
119 #define TSTAT        (0x104 / 4)
120 #define DFVLAN       (0x108 / 4)
121 #define TXIC         (0x110 / 4)
122 #define TQUEUE       (0x114 / 4)
123 #define TR03WT       (0x140 / 4)
124 #define TR47WT       (0x144 / 4)
125 #define TBDBPH       (0x180 / 4)
126 #define TBPTR0       (0x184 / 4)
127 #define TBPTR1       (0x18C / 4)
128 #define TBPTR2       (0x194 / 4)
129 #define TBPTR3       (0x19C / 4)
130 #define TBPTR4       (0x1A4 / 4)
131 #define TBPTR5       (0x1AC / 4)
132 #define TBPTR6       (0x1B4 / 4)
133 #define TBPTR7       (0x1BC / 4)
134 #define TBASEH       (0x200 / 4)
135 #define TBASE0       (0x204 / 4)
136 #define TBASE1       (0x20C / 4)
137 #define TBASE2       (0x214 / 4)
138 #define TBASE3       (0x21C / 4)
139 #define TBASE4       (0x224 / 4)
140 #define TBASE5       (0x22C / 4)
141 #define TBASE6       (0x234 / 4)
142 #define TBASE7       (0x23C / 4)
143 #define TMR_TXTS1_ID (0x280 / 4)
144 #define TMR_TXTS2_ID (0x284 / 4)
145 #define TMR_TXTS1_H  (0x2C0 / 4)
146 #define TMR_TXTS1_L  (0x2C4 / 4)
147 #define TMR_TXTS2_H  (0x2C8 / 4)
148 #define TMR_TXTS2_L  (0x2CC / 4)
149 #define RCTRL        (0x300 / 4)
150 #define RSTAT        (0x304 / 4)
151 #define RXIC         (0x310 / 4)
152 #define RQUEUE       (0x314 / 4)
153 #define RBIFX        (0x330 / 4)
154 #define RQFAR        (0x334 / 4)
155 #define RQFCR        (0x338 / 4)
156 #define RQFPR        (0x33C / 4)
157 #define MRBLR        (0x340 / 4)
158 #define RBDBPH       (0x380 / 4)
159 #define RBPTR0       (0x384 / 4)
160 #define RBPTR1       (0x38C / 4)
161 #define RBPTR2       (0x394 / 4)
162 #define RBPTR3       (0x39C / 4)
163 #define RBPTR4       (0x3A4 / 4)
164 #define RBPTR5       (0x3AC / 4)
165 #define RBPTR6       (0x3B4 / 4)
166 #define RBPTR7       (0x3BC / 4)
167 #define RBASEH       (0x400 / 4)
168 #define RBASE0       (0x404 / 4)
169 #define RBASE1       (0x40C / 4)
170 #define RBASE2       (0x414 / 4)
171 #define RBASE3       (0x41C / 4)
172 #define RBASE4       (0x424 / 4)
173 #define RBASE5       (0x42C / 4)
174 #define RBASE6       (0x434 / 4)
175 #define RBASE7       (0x43C / 4)
176 #define TMR_RXTS_H   (0x4C0 / 4)
177 #define TMR_RXTS_L   (0x4C4 / 4)
178 #define MACCFG1      (0x500 / 4)
179 #define MACCFG2      (0x504 / 4)
180 #define IPGIFG       (0x508 / 4)
181 #define HAFDUP       (0x50C / 4)
182 #define MAXFRM       (0x510 / 4)
183 #define MIIMCFG      (0x520 / 4)
184 #define MIIMCOM      (0x524 / 4)
185 #define MIIMADD      (0x528 / 4)
186 #define MIIMCON      (0x52C / 4)
187 #define MIIMSTAT     (0x530 / 4)
188 #define MIIMIND      (0x534 / 4)
189 #define IFSTAT       (0x53C / 4)
190 #define MACSTNADDR1  (0x540 / 4)
191 #define MACSTNADDR2  (0x544 / 4)
192 #define MAC01ADDR1   (0x548 / 4)
193 #define MAC01ADDR2   (0x54C / 4)
194 #define MAC02ADDR1   (0x550 / 4)
195 #define MAC02ADDR2   (0x554 / 4)
196 #define MAC03ADDR1   (0x558 / 4)
197 #define MAC03ADDR2   (0x55C / 4)
198 #define MAC04ADDR1   (0x560 / 4)
199 #define MAC04ADDR2   (0x564 / 4)
200 #define MAC05ADDR1   (0x568 / 4)
201 #define MAC05ADDR2   (0x56C / 4)
202 #define MAC06ADDR1   (0x570 / 4)
203 #define MAC06ADDR2   (0x574 / 4)
204 #define MAC07ADDR1   (0x578 / 4)
205 #define MAC07ADDR2   (0x57C / 4)
206 #define MAC08ADDR1   (0x580 / 4)
207 #define MAC08ADDR2   (0x584 / 4)
208 #define MAC09ADDR1   (0x588 / 4)
209 #define MAC09ADDR2   (0x58C / 4)
210 #define MAC10ADDR1   (0x590 / 4)
211 #define MAC10ADDR2   (0x594 / 4)
212 #define MAC11ADDR1   (0x598 / 4)
213 #define MAC11ADDR2   (0x59C / 4)
214 #define MAC12ADDR1   (0x5A0 / 4)
215 #define MAC12ADDR2   (0x5A4 / 4)
216 #define MAC13ADDR1   (0x5A8 / 4)
217 #define MAC13ADDR2   (0x5AC / 4)
218 #define MAC14ADDR1   (0x5B0 / 4)
219 #define MAC14ADDR2   (0x5B4 / 4)
220 #define MAC15ADDR1   (0x5B8 / 4)
221 #define MAC15ADDR2   (0x5BC / 4)
222 #define TR64         (0x680 / 4)
223 #define TR127        (0x684 / 4)
224 #define TR255        (0x688 / 4)
225 #define TR511        (0x68C / 4)
226 #define TR1K         (0x690 / 4)
227 #define TRMAX        (0x694 / 4)
228 #define TRMGV        (0x698 / 4)
229 #define RBYT         (0x69C / 4)
230 #define RPKT         (0x6A0 / 4)
231 #define RFCS         (0x6A4 / 4)
232 #define RMCA         (0x6A8 / 4)
233 #define RBCA         (0x6AC / 4)
234 #define RXCF         (0x6B0 / 4)
235 #define RXPF         (0x6B4 / 4)
236 #define RXUO         (0x6B8 / 4)
237 #define RALN         (0x6BC / 4)
238 #define RFLR         (0x6C0 / 4)
239 #define RCDE         (0x6C4 / 4)
240 #define RCSE         (0x6C8 / 4)
241 #define RUND         (0x6CC / 4)
242 #define ROVR         (0x6D0 / 4)
243 #define RFRG         (0x6D4 / 4)
244 #define RJBR         (0x6D8 / 4)
245 #define RDRP         (0x6DC / 4)
246 #define TBYT         (0x6E0 / 4)
247 #define TPKT         (0x6E4 / 4)
248 #define TMCA         (0x6E8 / 4)
249 #define TBCA         (0x6EC / 4)
250 #define TXPF         (0x6F0 / 4)
251 #define TDFR         (0x6F4 / 4)
252 #define TEDF         (0x6F8 / 4)
253 #define TSCL         (0x6FC / 4)
254 #define TMCL         (0x700 / 4)
255 #define TLCL         (0x704 / 4)
256 #define TXCL         (0x708 / 4)
257 #define TNCL         (0x70C / 4)
258 #define TDRP         (0x714 / 4)
259 #define TJBR         (0x718 / 4)
260 #define TFCS         (0x71C / 4)
261 #define TXCF         (0x720 / 4)
262 #define TOVR         (0x724 / 4)
263 #define TUND         (0x728 / 4)
264 #define TFRG         (0x72C / 4)
265 #define CAR1         (0x730 / 4)
266 #define CAR2         (0x734 / 4)
267 #define CAM1         (0x738 / 4)
268 #define CAM2         (0x73C / 4)
269 #define RREJ         (0x740 / 4)
270 #define IGADDR0      (0x800 / 4)
271 #define IGADDR1      (0x804 / 4)
272 #define IGADDR2      (0x808 / 4)
273 #define IGADDR3      (0x80C / 4)
274 #define IGADDR4      (0x810 / 4)
275 #define IGADDR5      (0x814 / 4)
276 #define IGADDR6      (0x818 / 4)
277 #define IGADDR7      (0x81C / 4)
278 #define GADDR0       (0x880 / 4)
279 #define GADDR1       (0x884 / 4)
280 #define GADDR2       (0x888 / 4)
281 #define GADDR3       (0x88C / 4)
282 #define GADDR4       (0x890 / 4)
283 #define GADDR5       (0x894 / 4)
284 #define GADDR6       (0x898 / 4)
285 #define GADDR7       (0x89C / 4)
286 #define ATTR         (0xBF8 / 4)
287 #define ATTRELI      (0xBFC / 4)
288 #define RQPRM0       (0xC00 / 4)
289 #define RQPRM1       (0xC04 / 4)
290 #define RQPRM2       (0xC08 / 4)
291 #define RQPRM3       (0xC0C / 4)
292 #define RQPRM4       (0xC10 / 4)
293 #define RQPRM5       (0xC14 / 4)
294 #define RQPRM6       (0xC18 / 4)
295 #define RQPRM7       (0xC1C / 4)
296 #define RFBPTR0      (0xC44 / 4)
297 #define RFBPTR1      (0xC4C / 4)
298 #define RFBPTR2      (0xC54 / 4)
299 #define RFBPTR3      (0xC5C / 4)
300 #define RFBPTR4      (0xC64 / 4)
301 #define RFBPTR5      (0xC6C / 4)
302 #define RFBPTR6      (0xC74 / 4)
303 #define RFBPTR7      (0xC7C / 4)
304 #define TMR_CTRL     (0xE00 / 4)
305 #define TMR_TEVENT   (0xE04 / 4)
306 #define TMR_TEMASK   (0xE08 / 4)
307 #define TMR_PEVENT   (0xE0C / 4)
308 #define TMR_PEMASK   (0xE10 / 4)
309 #define TMR_STAT     (0xE14 / 4)
310 #define TMR_CNT_H    (0xE18 / 4)
311 #define TMR_CNT_L    (0xE1C / 4)
312 #define TMR_ADD      (0xE20 / 4)
313 #define TMR_ACC      (0xE24 / 4)
314 #define TMR_PRSC     (0xE28 / 4)
315 #define TMROFF_H     (0xE30 / 4)
316 #define TMROFF_L     (0xE34 / 4)
317 #define TMR_ALARM1_H (0xE40 / 4)
318 #define TMR_ALARM1_L (0xE44 / 4)
319 #define TMR_ALARM2_H (0xE48 / 4)
320 #define TMR_ALARM2_L (0xE4C / 4)
321 #define TMR_FIPER1   (0xE80 / 4)
322 #define TMR_FIPER2   (0xE84 / 4)
323 #define TMR_FIPER3   (0xE88 / 4)
324 #define TMR_ETTS1_H  (0xEA0 / 4)
325 #define TMR_ETTS1_L  (0xEA4 / 4)
326 #define TMR_ETTS2_H  (0xEA8 / 4)
327 #define TMR_ETTS2_L  (0xEAC / 4)
328 
329 #endif /* ETSEC_REGISTERS_H */
330