1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_CPUTYPE_H
6 #define __ASM_CPUTYPE_H
7
8 #define INVALID_HWID ULONG_MAX
9
10 #define MPIDR_UP_BITMASK (0x1 << 30)
11 #define MPIDR_MT_BITMASK (0x1 << 24)
12 #define MPIDR_HWID_BITMASK UL(0xff00ffffff)
13
14 #define MPIDR_LEVEL_BITS_SHIFT 3
15 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT)
16 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
17
18 #define MPIDR_LEVEL_SHIFT(level) \
19 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
20
21 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \
22 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
23
24 #define MIDR_REVISION_MASK 0xf
25 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK)
26 #define MIDR_PARTNUM_SHIFT 4
27 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
28 #define MIDR_PARTNUM(midr) \
29 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT)
30 #define MIDR_ARCHITECTURE_SHIFT 16
31 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
32 #define MIDR_ARCHITECTURE(midr) \
33 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT)
34 #define MIDR_VARIANT_SHIFT 20
35 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT)
36 #define MIDR_VARIANT(midr) \
37 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT)
38 #define MIDR_IMPLEMENTOR_SHIFT 24
39 #define MIDR_IMPLEMENTOR_MASK (0xffU << MIDR_IMPLEMENTOR_SHIFT)
40 #define MIDR_IMPLEMENTOR(midr) \
41 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT)
42
43 #define MIDR_CPU_MODEL(imp, partnum) \
44 ((_AT(u32, imp) << MIDR_IMPLEMENTOR_SHIFT) | \
45 (0xf << MIDR_ARCHITECTURE_SHIFT) | \
46 ((partnum) << MIDR_PARTNUM_SHIFT))
47
48 #define MIDR_CPU_VAR_REV(var, rev) \
49 (((var) << MIDR_VARIANT_SHIFT) | (rev))
50
51 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \
52 MIDR_ARCHITECTURE_MASK)
53
54 #define ARM_CPU_IMP_ARM 0x41
55 #define ARM_CPU_IMP_APM 0x50
56 #define ARM_CPU_IMP_CAVIUM 0x43
57 #define ARM_CPU_IMP_BRCM 0x42
58 #define ARM_CPU_IMP_QCOM 0x51
59 #define ARM_CPU_IMP_NVIDIA 0x4E
60 #define ARM_CPU_IMP_FUJITSU 0x46
61 #define ARM_CPU_IMP_HISI 0x48
62 #define ARM_CPU_IMP_APPLE 0x61
63 #define ARM_CPU_IMP_AMPERE 0xC0
64 #define ARM_CPU_IMP_MICROSOFT 0x6D
65
66 #define ARM_CPU_PART_AEM_V8 0xD0F
67 #define ARM_CPU_PART_FOUNDATION 0xD00
68 #define ARM_CPU_PART_CORTEX_A57 0xD07
69 #define ARM_CPU_PART_CORTEX_A72 0xD08
70 #define ARM_CPU_PART_CORTEX_A53 0xD03
71 #define ARM_CPU_PART_CORTEX_A73 0xD09
72 #define ARM_CPU_PART_CORTEX_A75 0xD0A
73 #define ARM_CPU_PART_CORTEX_A35 0xD04
74 #define ARM_CPU_PART_CORTEX_A55 0xD05
75 #define ARM_CPU_PART_CORTEX_A76 0xD0B
76 #define ARM_CPU_PART_NEOVERSE_N1 0xD0C
77 #define ARM_CPU_PART_CORTEX_A77 0xD0D
78 #define ARM_CPU_PART_NEOVERSE_V1 0xD40
79 #define ARM_CPU_PART_CORTEX_A78 0xD41
80 #define ARM_CPU_PART_CORTEX_A78AE 0xD42
81 #define ARM_CPU_PART_CORTEX_X1 0xD44
82 #define ARM_CPU_PART_CORTEX_A510 0xD46
83 #define ARM_CPU_PART_CORTEX_A520 0xD80
84 #define ARM_CPU_PART_CORTEX_A710 0xD47
85 #define ARM_CPU_PART_CORTEX_A715 0xD4D
86 #define ARM_CPU_PART_CORTEX_X2 0xD48
87 #define ARM_CPU_PART_NEOVERSE_N2 0xD49
88 #define ARM_CPU_PART_CORTEX_A78C 0xD4B
89 #define ARM_CPU_PART_CORTEX_X1C 0xD4C
90 #define ARM_CPU_PART_CORTEX_X3 0xD4E
91 #define ARM_CPU_PART_NEOVERSE_V2 0xD4F
92 #define ARM_CPU_PART_CORTEX_A720 0xD81
93 #define ARM_CPU_PART_CORTEX_X4 0xD82
94 #define ARM_CPU_PART_NEOVERSE_V3 0xD84
95 #define ARM_CPU_PART_CORTEX_X925 0xD85
96 #define ARM_CPU_PART_CORTEX_A725 0xD87
97
98 #define APM_CPU_PART_XGENE 0x000
99 #define APM_CPU_VAR_POTENZA 0x00
100
101 #define CAVIUM_CPU_PART_THUNDERX 0x0A1
102 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
103 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3
104 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF
105 /* OcteonTx2 series */
106 #define CAVIUM_CPU_PART_OCTX2_98XX 0x0B1
107 #define CAVIUM_CPU_PART_OCTX2_96XX 0x0B2
108 #define CAVIUM_CPU_PART_OCTX2_95XX 0x0B3
109 #define CAVIUM_CPU_PART_OCTX2_95XXN 0x0B4
110 #define CAVIUM_CPU_PART_OCTX2_95XXMM 0x0B5
111 #define CAVIUM_CPU_PART_OCTX2_95XXO 0x0B6
112
113 #define BRCM_CPU_PART_BRAHMA_B53 0x100
114 #define BRCM_CPU_PART_VULCAN 0x516
115
116 #define QCOM_CPU_PART_FALKOR_V1 0x800
117 #define QCOM_CPU_PART_FALKOR 0xC00
118 #define QCOM_CPU_PART_KRYO 0x200
119 #define QCOM_CPU_PART_KRYO_2XX_GOLD 0x800
120 #define QCOM_CPU_PART_KRYO_2XX_SILVER 0x801
121 #define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
122 #define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
123 #define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
124
125 #define NVIDIA_CPU_PART_DENVER 0x003
126 #define NVIDIA_CPU_PART_CARMEL 0x004
127
128 #define FUJITSU_CPU_PART_A64FX 0x001
129
130 #define HISI_CPU_PART_TSV110 0xD01
131
132 #define APPLE_CPU_PART_M1_ICESTORM 0x022
133 #define APPLE_CPU_PART_M1_FIRESTORM 0x023
134 #define APPLE_CPU_PART_M1_ICESTORM_PRO 0x024
135 #define APPLE_CPU_PART_M1_FIRESTORM_PRO 0x025
136 #define APPLE_CPU_PART_M1_ICESTORM_MAX 0x028
137 #define APPLE_CPU_PART_M1_FIRESTORM_MAX 0x029
138 #define APPLE_CPU_PART_M2_BLIZZARD 0x032
139 #define APPLE_CPU_PART_M2_AVALANCHE 0x033
140 #define APPLE_CPU_PART_M2_BLIZZARD_PRO 0x034
141 #define APPLE_CPU_PART_M2_AVALANCHE_PRO 0x035
142 #define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
143 #define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
144
145 #define AMPERE_CPU_PART_AMPERE1 0xAC3
146
147 #define MICROSOFT_CPU_PART_AZURE_COBALT_100 0xD49 /* Based on r0p0 of ARM Neoverse N2 */
148
149 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
150 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
151 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
152 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
153 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75)
154 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35)
155 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55)
156 #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76)
157 #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1)
158 #define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77)
159 #define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1)
160 #define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78)
161 #define MIDR_CORTEX_A78AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78AE)
162 #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1)
163 #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A510)
164 #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A520)
165 #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710)
166 #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A715)
167 #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
168 #define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
169 #define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
170 #define MIDR_CORTEX_X1C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1C)
171 #define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
172 #define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
173 #define MIDR_CORTEX_A720 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A720)
174 #define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
175 #define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
176 #define MIDR_CORTEX_X925 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X925)
177 #define MIDR_CORTEX_A725 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A725)
178 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
179 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
180 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
181 #define MIDR_OCTX2_98XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_98XX)
182 #define MIDR_OCTX2_96XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_96XX)
183 #define MIDR_OCTX2_95XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XX)
184 #define MIDR_OCTX2_95XXN MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXN)
185 #define MIDR_OCTX2_95XXMM MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXMM)
186 #define MIDR_OCTX2_95XXO MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_OCTX2_95XXO)
187 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2)
188 #define MIDR_BRAHMA_B53 MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_BRAHMA_B53)
189 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN)
190 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
191 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
192 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
193 #define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)
194 #define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)
195 #define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
196 #define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
197 #define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
198 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
199 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
200 #define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)
201 #define MIDR_HISI_TSV110 MIDR_CPU_MODEL(ARM_CPU_IMP_HISI, HISI_CPU_PART_TSV110)
202 #define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)
203 #define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)
204 #define MIDR_APPLE_M1_ICESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_PRO)
205 #define MIDR_APPLE_M1_FIRESTORM_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_PRO)
206 #define MIDR_APPLE_M1_ICESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM_MAX)
207 #define MIDR_APPLE_M1_FIRESTORM_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM_MAX)
208 #define MIDR_APPLE_M2_BLIZZARD MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD)
209 #define MIDR_APPLE_M2_AVALANCHE MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE)
210 #define MIDR_APPLE_M2_BLIZZARD_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_PRO)
211 #define MIDR_APPLE_M2_AVALANCHE_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_PRO)
212 #define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)
213 #define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)
214 #define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)
215 #define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)
216
217 /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
218 #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
219 #define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_CPU_VAR_REV(1, 0))
220 #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
221
222 #ifndef __ASSEMBLY__
223
224 #include <asm/sysreg.h>
225
226 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg)
227
228 /*
229 * Represent a range of MIDR values for a given CPU model and a
230 * range of variant/revision values.
231 *
232 * @model - CPU model as defined by MIDR_CPU_MODEL
233 * @rv_min - Minimum value for the revision/variant as defined by
234 * MIDR_CPU_VAR_REV
235 * @rv_max - Maximum value for the variant/revision for the range.
236 */
237 struct midr_range {
238 u32 model;
239 u32 rv_min;
240 u32 rv_max;
241 };
242
243 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \
244 { \
245 .model = m, \
246 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \
247 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \
248 }
249
250 #define MIDR_REV_RANGE(m, v, r_min, r_max) MIDR_RANGE(m, v, r_min, v, r_max)
251 #define MIDR_REV(m, v, r) MIDR_RANGE(m, v, r, v, r)
252 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf)
253
midr_is_cpu_model_range(u32 midr,u32 model,u32 rv_min,u32 rv_max)254 static inline bool midr_is_cpu_model_range(u32 midr, u32 model, u32 rv_min,
255 u32 rv_max)
256 {
257 u32 _model = midr & MIDR_CPU_MODEL_MASK;
258 u32 rv = midr & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK);
259
260 return _model == model && rv >= rv_min && rv <= rv_max;
261 }
262
is_midr_in_range(u32 midr,struct midr_range const * range)263 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range)
264 {
265 return midr_is_cpu_model_range(midr, range->model,
266 range->rv_min, range->rv_max);
267 }
268
269 static inline bool
is_midr_in_range_list(u32 midr,struct midr_range const * ranges)270 is_midr_in_range_list(u32 midr, struct midr_range const *ranges)
271 {
272 while (ranges->model)
273 if (is_midr_in_range(midr, ranges++))
274 return true;
275 return false;
276 }
277
278 /*
279 * The CPU ID never changes at run time, so we might as well tell the
280 * compiler that it's constant. Use this function to read the CPU ID
281 * rather than directly reading processor_id or read_cpuid() directly.
282 */
read_cpuid_id(void)283 static inline u32 __attribute_const__ read_cpuid_id(void)
284 {
285 return read_cpuid(MIDR_EL1);
286 }
287
read_cpuid_mpidr(void)288 static inline u64 __attribute_const__ read_cpuid_mpidr(void)
289 {
290 return read_cpuid(MPIDR_EL1);
291 }
292
read_cpuid_implementor(void)293 static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
294 {
295 return MIDR_IMPLEMENTOR(read_cpuid_id());
296 }
297
read_cpuid_part_number(void)298 static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
299 {
300 return MIDR_PARTNUM(read_cpuid_id());
301 }
302
read_cpuid_cachetype(void)303 static inline u32 __attribute_const__ read_cpuid_cachetype(void)
304 {
305 return read_cpuid(CTR_EL0);
306 }
307 #endif /* __ASSEMBLY__ */
308
309 #endif
310