1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright 2010 Matt Turner.
4  * Copyright 2012 Red Hat
5  *
6  * Authors: Matthew Garrett
7  * 	    Matt Turner
8  *	    Dave Airlie
9  */
10 #ifndef __MGAG200_DRV_H__
11 #define __MGAG200_DRV_H__
12 
13 #include <linux/i2c-algo-bit.h>
14 #include <linux/i2c.h>
15 
16 #include <video/vga.h>
17 
18 #include <drm/drm_connector.h>
19 #include <drm/drm_crtc.h>
20 #include <drm/drm_encoder.h>
21 #include <drm/drm_gem.h>
22 #include <drm/drm_gem_shmem_helper.h>
23 #include <drm/drm_plane.h>
24 
25 #include "mgag200_reg.h"
26 
27 #define DRIVER_AUTHOR		"Matthew Garrett"
28 
29 #define DRIVER_NAME		"mgag200"
30 #define DRIVER_DESC		"MGA G200 SE"
31 #define DRIVER_DATE		"20110418"
32 
33 #define DRIVER_MAJOR		1
34 #define DRIVER_MINOR		0
35 #define DRIVER_PATCHLEVEL	0
36 
37 #define RREG8(reg) ioread8(((void __iomem *)mdev->rmmio) + (reg))
38 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)mdev->rmmio) + (reg))
39 #define RREG32(reg) ioread32(((void __iomem *)mdev->rmmio) + (reg))
40 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)mdev->rmmio) + (reg))
41 
42 #define MGA_BIOS_OFFSET		0x7ffc
43 
44 #define ATTR_INDEX 0x1fc0
45 #define ATTR_DATA 0x1fc1
46 
47 #define WREG_MISC(v)						\
48 	WREG8(MGA_MISC_OUT, v)
49 
50 #define RREG_MISC(v)						\
51 	((v) = RREG8(MGA_MISC_IN))
52 
53 #define WREG_MISC_MASKED(v, mask)				\
54 	do {							\
55 		u8 misc_;					\
56 		u8 mask_ = (mask);				\
57 		RREG_MISC(misc_);				\
58 		misc_ &= ~mask_;				\
59 		misc_ |= ((v) & mask_);				\
60 		WREG_MISC(misc_);				\
61 	} while (0)
62 
63 #define WREG_ATTR(reg, v)					\
64 	do {							\
65 		RREG8(0x1fda);					\
66 		WREG8(ATTR_INDEX, reg);				\
67 		WREG8(ATTR_DATA, v);				\
68 	} while (0)						\
69 
70 #define RREG_SEQ(reg, v)					\
71 	do {							\
72 		WREG8(MGAREG_SEQ_INDEX, reg);			\
73 		v = RREG8(MGAREG_SEQ_DATA);			\
74 	} while (0)						\
75 
76 #define WREG_SEQ(reg, v)					\
77 	do {							\
78 		WREG8(MGAREG_SEQ_INDEX, reg);			\
79 		WREG8(MGAREG_SEQ_DATA, v);			\
80 	} while (0)						\
81 
82 #define RREG_CRT(reg, v)					\
83 	do {							\
84 		WREG8(MGAREG_CRTC_INDEX, reg);			\
85 		v = RREG8(MGAREG_CRTC_DATA);			\
86 	} while (0)						\
87 
88 #define WREG_CRT(reg, v)					\
89 	do {							\
90 		WREG8(MGAREG_CRTC_INDEX, reg);			\
91 		WREG8(MGAREG_CRTC_DATA, v);			\
92 	} while (0)						\
93 
94 #define RREG_ECRT(reg, v)					\
95 	do {							\
96 		WREG8(MGAREG_CRTCEXT_INDEX, reg);		\
97 		v = RREG8(MGAREG_CRTCEXT_DATA);			\
98 	} while (0)						\
99 
100 #define WREG_ECRT(reg, v)					\
101 	do {							\
102 		WREG8(MGAREG_CRTCEXT_INDEX, reg);				\
103 		WREG8(MGAREG_CRTCEXT_DATA, v);				\
104 	} while (0)						\
105 
106 #define GFX_INDEX 0x1fce
107 #define GFX_DATA 0x1fcf
108 
109 #define WREG_GFX(reg, v)					\
110 	do {							\
111 		WREG8(GFX_INDEX, reg);				\
112 		WREG8(GFX_DATA, v);				\
113 	} while (0)						\
114 
115 #define DAC_INDEX 0x3c00
116 #define DAC_DATA 0x3c0a
117 
118 #define WREG_DAC(reg, v)					\
119 	do {							\
120 		WREG8(DAC_INDEX, reg);				\
121 		WREG8(DAC_DATA, v);				\
122 	} while (0)						\
123 
124 #define MGA_MISC_OUT 0x1fc2
125 #define MGA_MISC_IN 0x1fcc
126 
127 /*
128  * TODO: This is a pretty large set of default values for all kinds of
129  *       settings. It should be split and set in the various DRM helpers,
130  *       such as the CRTC reset or atomic_enable helpers. The PLL values
131  *       probably belong to each model's PLL code.
132  */
133 #define MGAG200_DAC_DEFAULT(xvrefctrl, xpixclkctrl, xmiscctrl, xsyspllm, xsysplln, xsyspllp)	\
134 	/* 0x00: */        0,    0,    0,    0,    0,    0, 0x00,    0,				\
135 	/* 0x08: */        0,    0,    0,    0,    0,    0,    0,    0,				\
136 	/* 0x10: */        0,    0,    0,    0,    0,    0,    0,    0,				\
137 	/* 0x18: */     (xvrefctrl),								\
138 	/* 0x19: */        0,									\
139 	/* 0x1a: */     (xpixclkctrl),								\
140 	/* 0x1b: */     0xff, 0xbf, 0x20,							\
141 	/* 0x1e: */	(xmiscctrl),								\
142 	/* 0x1f: */	0x20,									\
143 	/* 0x20: */     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,				\
144 	/* 0x28: */     0x00, 0x00, 0x00, 0x00,							\
145 	/* 0x2c: */     (xsyspllm),								\
146 	/* 0x2d: */     (xsysplln),								\
147 	/* 0x2e: */     (xsyspllp),								\
148 	/* 0x2f: */     0x40,									\
149 	/* 0x30: */     0x00, 0xb0, 0x00, 0xc2, 0x34, 0x14, 0x02, 0x83,				\
150 	/* 0x38: */     0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3a,				\
151 	/* 0x40: */        0,    0,    0,    0,    0,    0,    0,    0,				\
152 	/* 0x48: */        0,    0,    0,    0,    0,    0,    0,    0				\
153 
154 #define MGAG200_LUT_SIZE 256
155 
156 #define MGAG200_MAX_FB_HEIGHT 4096
157 #define MGAG200_MAX_FB_WIDTH 4096
158 
159 struct mga_device;
160 
161 /*
162  * Stores parameters for programming the PLLs
163  *
164  * Fref: reference frequency (A: 25.175 Mhz, B: 28.361, C: XX Mhz)
165  * Fo: output frequency
166  * Fvco = Fref * (N / M)
167  * Fo = Fvco / P
168  *
169  * S = [0..3]
170  */
171 struct mgag200_pll_values {
172 	unsigned int m;
173 	unsigned int n;
174 	unsigned int p;
175 	unsigned int s;
176 };
177 
178 struct mgag200_crtc_state {
179 	struct drm_crtc_state base;
180 
181 	/* Primary-plane format; required for modesetting and color mgmt. */
182 	const struct drm_format_info *format;
183 
184 	struct mgag200_pll_values pixpllc;
185 };
186 
to_mgag200_crtc_state(struct drm_crtc_state * base)187 static inline struct mgag200_crtc_state *to_mgag200_crtc_state(struct drm_crtc_state *base)
188 {
189 	return container_of(base, struct mgag200_crtc_state, base);
190 }
191 
192 struct mga_i2c_chan {
193 	struct i2c_adapter adapter;
194 	struct drm_device *dev;
195 	struct i2c_algo_bit_data bit;
196 	int data, clock;
197 };
198 
199 enum mga_type {
200 	G200_PCI,
201 	G200_AGP,
202 	G200_SE_A,
203 	G200_SE_B,
204 	G200_WB,
205 	G200_EV,
206 	G200_EH,
207 	G200_EH3,
208 	G200_ER,
209 	G200_EW3,
210 };
211 
212 struct mgag200_device_info {
213 	u16 max_hdisplay;
214 	u16 max_vdisplay;
215 
216 	/*
217 	 * Maximum memory bandwidth (MiB/sec). Setting this to zero disables
218 	 * the rsp test during mode validation.
219 	 */
220 	unsigned long max_mem_bandwidth;
221 
222 	/* HW has external source (e.g., BMC) to synchronize with */
223 	bool has_vidrst:1;
224 
225 	struct {
226 		unsigned data_bit:3;
227 		unsigned clock_bit:3;
228 	} i2c;
229 
230 	/*
231 	 * HW does not handle 'startadd' register correctly. Always set
232 	 * it's value to 0.
233 	 */
234 	bool bug_no_startadd:1;
235 };
236 
237 #define MGAG200_DEVICE_INFO_INIT(_max_hdisplay, _max_vdisplay, _max_mem_bandwidth, \
238 				 _has_vidrst, _i2c_data_bit, _i2c_clock_bit, \
239 				 _bug_no_startadd) \
240 	{ \
241 		.max_hdisplay = (_max_hdisplay), \
242 		.max_vdisplay = (_max_vdisplay), \
243 		.max_mem_bandwidth = (_max_mem_bandwidth), \
244 		.has_vidrst = (_has_vidrst), \
245 		.i2c = { \
246 			.data_bit = (_i2c_data_bit), \
247 			.clock_bit = (_i2c_clock_bit), \
248 		}, \
249 		.bug_no_startadd = (_bug_no_startadd), \
250 	}
251 
252 struct mgag200_device_funcs {
253 	/*
254 	 * Disables an external reset source (i.e., BMC) before programming
255 	 * a new display mode.
256 	 */
257 	void (*disable_vidrst)(struct mga_device *mdev);
258 
259 	/*
260 	 * Enables an external reset source (i.e., BMC) after programming
261 	 * a new display mode.
262 	 */
263 	void (*enable_vidrst)(struct mga_device *mdev);
264 
265 	/*
266 	 * Validate that the given state can be programmed into PIXPLLC. On
267 	 * success, the calculated parameters should be stored in the CRTC's
268 	 * state in struct @mgag200_crtc_state.pixpllc.
269 	 */
270 	int (*pixpllc_atomic_check)(struct drm_crtc *crtc, struct drm_atomic_state *new_state);
271 
272 	/*
273 	 * Program PIXPLLC from the CRTC state. The parameters should have been
274 	 * stored in struct @mgag200_crtc_state.pixpllc by the corresponding
275 	 * implementation of @pixpllc_atomic_check.
276 	 */
277 	void (*pixpllc_atomic_update)(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
278 };
279 
280 struct mga_device {
281 	struct drm_device base;
282 
283 	const struct mgag200_device_info *info;
284 	const struct mgag200_device_funcs *funcs;
285 
286 	struct resource			*rmmio_res;
287 	void __iomem			*rmmio;
288 	struct mutex			rmmio_lock; /* Protects access to rmmio */
289 
290 	struct resource			*vram_res;
291 	void __iomem			*vram;
292 	resource_size_t			vram_available;
293 
294 	struct drm_plane primary_plane;
295 	struct drm_crtc crtc;
296 	struct drm_encoder encoder;
297 	struct mga_i2c_chan i2c;
298 	struct drm_connector connector;
299 };
300 
to_mga_device(struct drm_device * dev)301 static inline struct mga_device *to_mga_device(struct drm_device *dev)
302 {
303 	return container_of(dev, struct mga_device, base);
304 }
305 
306 struct mgag200_g200_device {
307 	struct mga_device base;
308 
309 	/* PLL constants */
310 	long ref_clk;
311 	long pclk_min;
312 	long pclk_max;
313 };
314 
to_mgag200_g200_device(struct drm_device * dev)315 static inline struct mgag200_g200_device *to_mgag200_g200_device(struct drm_device *dev)
316 {
317 	return container_of(to_mga_device(dev), struct mgag200_g200_device, base);
318 }
319 
320 struct mgag200_g200se_device {
321 	struct mga_device base;
322 
323 	/* SE model number stored in reg 0x1e24 */
324 	u32 unique_rev_id;
325 };
326 
to_mgag200_g200se_device(struct drm_device * dev)327 static inline struct mgag200_g200se_device *to_mgag200_g200se_device(struct drm_device *dev)
328 {
329 	return container_of(to_mga_device(dev), struct mgag200_g200se_device, base);
330 }
331 
332 				/* mgag200_drv.c */
333 int mgag200_init_pci_options(struct pci_dev *pdev, u32 option, u32 option2);
334 resource_size_t mgag200_probe_vram(void __iomem *mem, resource_size_t size);
335 resource_size_t mgag200_device_probe_vram(struct mga_device *mdev);
336 int mgag200_device_preinit(struct mga_device *mdev);
337 int mgag200_device_init(struct mga_device *mdev,
338 			const struct mgag200_device_info *info,
339 			const struct mgag200_device_funcs *funcs);
340 
341 				/* mgag200_<device type>.c */
342 struct mga_device *mgag200_g200_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
343 struct mga_device *mgag200_g200se_device_create(struct pci_dev *pdev, const struct drm_driver *drv,
344 						enum mga_type type);
345 void mgag200_g200wb_init_registers(struct mga_device *mdev);
346 void mgag200_g200wb_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
347 struct mga_device *mgag200_g200wb_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
348 struct mga_device *mgag200_g200ev_device_create(struct pci_dev *pdev, const struct drm_driver *drv);
349 void mgag200_g200eh_init_registers(struct mga_device *mdev);
350 void mgag200_g200eh_pixpllc_atomic_update(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
351 struct mga_device *mgag200_g200eh_device_create(struct pci_dev *pdev,
352 						const struct drm_driver *drv);
353 struct mga_device *mgag200_g200eh3_device_create(struct pci_dev *pdev,
354 						 const struct drm_driver *drv);
355 struct mga_device *mgag200_g200er_device_create(struct pci_dev *pdev,
356 						const struct drm_driver *drv);
357 struct mga_device *mgag200_g200ew3_device_create(struct pci_dev *pdev,
358 						 const struct drm_driver *drv);
359 
360 /*
361  * mgag200_mode.c
362  */
363 
364 struct drm_crtc;
365 struct drm_crtc_state;
366 struct drm_display_mode;
367 struct drm_plane;
368 struct drm_atomic_state;
369 
370 extern const uint32_t mgag200_primary_plane_formats[];
371 extern const size_t   mgag200_primary_plane_formats_size;
372 extern const uint64_t mgag200_primary_plane_fmtmods[];
373 
374 int mgag200_primary_plane_helper_atomic_check(struct drm_plane *plane,
375 					      struct drm_atomic_state *new_state);
376 void mgag200_primary_plane_helper_atomic_update(struct drm_plane *plane,
377 						struct drm_atomic_state *old_state);
378 void mgag200_primary_plane_helper_atomic_enable(struct drm_plane *plane,
379 						struct drm_atomic_state *state);
380 void mgag200_primary_plane_helper_atomic_disable(struct drm_plane *plane,
381 						 struct drm_atomic_state *old_state);
382 #define MGAG200_PRIMARY_PLANE_HELPER_FUNCS \
383 	DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, \
384 	.atomic_check = mgag200_primary_plane_helper_atomic_check, \
385 	.atomic_update = mgag200_primary_plane_helper_atomic_update, \
386 	.atomic_enable = mgag200_primary_plane_helper_atomic_enable, \
387 	.atomic_disable = mgag200_primary_plane_helper_atomic_disable
388 
389 #define MGAG200_PRIMARY_PLANE_FUNCS \
390 	.update_plane = drm_atomic_helper_update_plane, \
391 	.disable_plane = drm_atomic_helper_disable_plane, \
392 	.destroy = drm_plane_cleanup, \
393 	DRM_GEM_SHADOW_PLANE_FUNCS
394 
395 void mgag200_crtc_set_gamma_linear(struct mga_device *mdev, const struct drm_format_info *format);
396 void mgag200_crtc_set_gamma(struct mga_device *mdev,
397 			    const struct drm_format_info *format,
398 			    struct drm_color_lut *lut);
399 
400 enum drm_mode_status mgag200_crtc_helper_mode_valid(struct drm_crtc *crtc,
401 						    const struct drm_display_mode *mode);
402 int mgag200_crtc_helper_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *new_state);
403 void mgag200_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
404 void mgag200_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
405 void mgag200_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *old_state);
406 
407 #define MGAG200_CRTC_HELPER_FUNCS \
408 	.mode_valid = mgag200_crtc_helper_mode_valid, \
409 	.atomic_check = mgag200_crtc_helper_atomic_check, \
410 	.atomic_flush = mgag200_crtc_helper_atomic_flush, \
411 	.atomic_enable = mgag200_crtc_helper_atomic_enable, \
412 	.atomic_disable = mgag200_crtc_helper_atomic_disable
413 
414 void mgag200_crtc_reset(struct drm_crtc *crtc);
415 struct drm_crtc_state *mgag200_crtc_atomic_duplicate_state(struct drm_crtc *crtc);
416 void mgag200_crtc_atomic_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state);
417 
418 #define MGAG200_CRTC_FUNCS \
419 	.reset = mgag200_crtc_reset, \
420 	.destroy = drm_crtc_cleanup, \
421 	.set_config = drm_atomic_helper_set_config, \
422 	.page_flip = drm_atomic_helper_page_flip, \
423 	.atomic_duplicate_state = mgag200_crtc_atomic_duplicate_state, \
424 	.atomic_destroy_state = mgag200_crtc_atomic_destroy_state
425 
426 #define MGAG200_DAC_ENCODER_FUNCS \
427 	.destroy = drm_encoder_cleanup
428 
429 int mgag200_vga_connector_helper_get_modes(struct drm_connector *connector);
430 
431 #define MGAG200_VGA_CONNECTOR_HELPER_FUNCS \
432 	.get_modes  = mgag200_vga_connector_helper_get_modes
433 
434 #define MGAG200_VGA_CONNECTOR_FUNCS \
435 	.reset                  = drm_atomic_helper_connector_reset, \
436 	.fill_modes             = drm_helper_probe_single_connector_modes, \
437 	.destroy                = drm_connector_cleanup, \
438 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, \
439 	.atomic_destroy_state   = drm_atomic_helper_connector_destroy_state
440 
441 void mgag200_set_mode_regs(struct mga_device *mdev, const struct drm_display_mode *mode);
442 void mgag200_set_format_regs(struct mga_device *mdev, const struct drm_format_info *format);
443 void mgag200_enable_display(struct mga_device *mdev);
444 void mgag200_init_registers(struct mga_device *mdev);
445 int mgag200_mode_config_init(struct mga_device *mdev, resource_size_t vram_available);
446 
447 				/* mgag200_bmc.c */
448 void mgag200_bmc_disable_vidrst(struct mga_device *mdev);
449 void mgag200_bmc_enable_vidrst(struct mga_device *mdev);
450 
451 				/* mgag200_i2c.c */
452 int mgag200_i2c_init(struct mga_device *mdev, struct mga_i2c_chan *i2c);
453 
454 #endif				/* __MGAG200_DRV_H__ */
455