1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Samsung S5P Multi Format Codec v 5.0
4  *
5  * This file contains definitions of enums and structs used by the codec
6  * driver.
7  *
8  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
9  * Kamil Debski, <k.debski@samsung.com>
10  */
11 
12 #ifndef S5P_MFC_COMMON_H_
13 #define S5P_MFC_COMMON_H_
14 
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <media/v4l2-ctrls.h>
18 #include <media/v4l2-device.h>
19 #include <media/v4l2-ioctl.h>
20 #include <media/videobuf2-v4l2.h>
21 #include "regs-mfc.h"
22 #include "regs-mfc-v10.h"
23 
24 #define S5P_MFC_NAME		"s5p-mfc"
25 
26 /* Definitions related to MFC memory */
27 
28 /* Offset base used to differentiate between CAPTURE and OUTPUT
29 *  while mmaping */
30 #define DST_QUEUE_OFF_BASE	(1 << 30)
31 
32 #define BANK_L_CTX	0
33 #define BANK_R_CTX	1
34 #define BANK_CTX_NUM	2
35 
36 #define MFC_BANK1_ALIGN_ORDER	13
37 #define MFC_BANK2_ALIGN_ORDER	13
38 #define MFC_BASE_ALIGN_ORDER	17
39 
40 #define MFC_FW_MAX_VERSIONS	2
41 
42 #include <media/videobuf2-dma-contig.h>
43 
44 /* MFC definitions */
45 #define MFC_MAX_EXTRA_DPB       5
46 #define MFC_MAX_BUFFERS		32
47 #define MFC_NUM_CONTEXTS	4
48 /* Interrupt timeout */
49 #define MFC_INT_TIMEOUT		2000
50 /* Busy wait timeout */
51 #define MFC_BW_TIMEOUT		500
52 /* Watchdog interval */
53 #define MFC_WATCHDOG_INTERVAL   1000
54 /* After how many executions watchdog should assume lock up */
55 #define MFC_WATCHDOG_CNT        10
56 #define MFC_NO_INSTANCE_SET	-1
57 #define MFC_ENC_CAP_PLANE_COUNT	1
58 #define MFC_ENC_OUT_PLANE_COUNT	2
59 #define STUFF_BYTE		4
60 #define MFC_MAX_CTRLS		128
61 
62 #define S5P_MFC_CODEC_NONE		-1
63 #define S5P_MFC_CODEC_H264_DEC		0
64 #define S5P_MFC_CODEC_H264_MVC_DEC	1
65 #define S5P_MFC_CODEC_VC1_DEC		2
66 #define S5P_MFC_CODEC_MPEG4_DEC		3
67 #define S5P_MFC_CODEC_MPEG2_DEC		4
68 #define S5P_MFC_CODEC_H263_DEC		5
69 #define S5P_MFC_CODEC_VC1RCV_DEC	6
70 #define S5P_MFC_CODEC_VP8_DEC		7
71 #define S5P_MFC_CODEC_HEVC_DEC		17
72 #define S5P_MFC_CODEC_VP9_DEC		18
73 
74 #define S5P_MFC_CODEC_H264_ENC		20
75 #define S5P_MFC_CODEC_H264_MVC_ENC	21
76 #define S5P_MFC_CODEC_MPEG4_ENC		22
77 #define S5P_MFC_CODEC_H263_ENC		23
78 #define S5P_MFC_CODEC_VP8_ENC		24
79 #define S5P_MFC_CODEC_HEVC_ENC		26
80 
81 #define S5P_MFC_R2H_CMD_EMPTY			0
82 #define S5P_MFC_R2H_CMD_SYS_INIT_RET		1
83 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET	2
84 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET		3
85 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET	4
86 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET	6
87 #define S5P_MFC_R2H_CMD_SLEEP_RET		7
88 #define S5P_MFC_R2H_CMD_WAKEUP_RET		8
89 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET	9
90 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET		10
91 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET		11
92 #define S5P_MFC_R2H_CMD_FW_STATUS_RET		12
93 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET		13
94 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET		14
95 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET		15
96 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET	16
97 #define S5P_MFC_R2H_CMD_ERR_RET			32
98 
99 #define MFC_MAX_CLOCKS		4
100 
101 #define mfc_read(dev, offset)		readl(dev->regs_base + (offset))
102 #define mfc_write(dev, data, offset)	writel((data), dev->regs_base + \
103 								(offset))
104 
105 /*
106  * enum s5p_mfc_fmt_type - type of the pixelformat
107  */
108 enum s5p_mfc_fmt_type {
109 	MFC_FMT_DEC,
110 	MFC_FMT_ENC,
111 	MFC_FMT_RAW,
112 };
113 
114 /*
115  * enum s5p_mfc_inst_type - The type of an MFC instance.
116  */
117 enum s5p_mfc_inst_type {
118 	MFCINST_INVALID,
119 	MFCINST_DECODER,
120 	MFCINST_ENCODER,
121 };
122 
123 /*
124  * enum s5p_mfc_inst_state - The state of an MFC instance.
125  */
126 enum s5p_mfc_inst_state {
127 	MFCINST_FREE = 0,
128 	MFCINST_INIT = 100,
129 	MFCINST_GOT_INST,
130 	MFCINST_HEAD_PARSED,
131 	MFCINST_HEAD_PRODUCED,
132 	MFCINST_BUFS_SET,
133 	MFCINST_RUNNING,
134 	MFCINST_FINISHING,
135 	MFCINST_FINISHED,
136 	MFCINST_RETURN_INST,
137 	MFCINST_ERROR,
138 	MFCINST_ABORT,
139 	MFCINST_FLUSH,
140 	MFCINST_RES_CHANGE_INIT,
141 	MFCINST_RES_CHANGE_FLUSH,
142 	MFCINST_RES_CHANGE_END,
143 };
144 
145 /*
146  * enum s5p_mfc_queue_state - The state of buffer queue.
147  */
148 enum s5p_mfc_queue_state {
149 	QUEUE_FREE,
150 	QUEUE_BUFS_REQUESTED,
151 	QUEUE_BUFS_QUERIED,
152 	QUEUE_BUFS_MMAPED,
153 };
154 
155 /*
156  * enum s5p_mfc_decode_arg - type of frame decoding
157  */
158 enum s5p_mfc_decode_arg {
159 	MFC_DEC_FRAME,
160 	MFC_DEC_LAST_FRAME,
161 	MFC_DEC_RES_CHANGE,
162 };
163 
164 enum s5p_mfc_fw_ver {
165 	MFC_FW_V1,
166 	MFC_FW_V2,
167 };
168 
169 #define MFC_BUF_FLAG_USED	(1 << 0)
170 #define MFC_BUF_FLAG_EOS	(1 << 1)
171 
172 struct s5p_mfc_ctx;
173 
174 /*
175  * struct s5p_mfc_buf - MFC buffer
176  */
177 struct s5p_mfc_buf {
178 	struct vb2_v4l2_buffer *b;
179 	struct list_head list;
180 	union {
181 		struct {
182 			size_t luma;
183 			size_t chroma;
184 		} raw;
185 		size_t stream;
186 	} cookie;
187 	int flags;
188 };
189 
190 /*
191  * struct s5p_mfc_pm - power management data structure
192  */
193 struct s5p_mfc_pm {
194 	struct clk	*clock_gate;
195 	const char * const *clk_names;
196 	struct clk	*clocks[MFC_MAX_CLOCKS];
197 	int		num_clocks;
198 	bool		use_clock_gating;
199 
200 	struct device	*device;
201 };
202 
203 struct s5p_mfc_buf_size_v5 {
204 	unsigned int h264_ctx;
205 	unsigned int non_h264_ctx;
206 	unsigned int dsc;
207 	unsigned int shm;
208 };
209 
210 struct s5p_mfc_buf_size_v6 {
211 	unsigned int dev_ctx;
212 	unsigned int h264_dec_ctx;
213 	unsigned int other_dec_ctx;
214 	unsigned int h264_enc_ctx;
215 	unsigned int hevc_enc_ctx;
216 	unsigned int other_enc_ctx;
217 };
218 
219 struct s5p_mfc_buf_size {
220 	unsigned int fw;
221 	unsigned int cpb;
222 	void *priv;
223 };
224 
225 struct s5p_mfc_variant {
226 	unsigned int version;
227 	unsigned int port_num;
228 	u32 version_bit;
229 	struct s5p_mfc_buf_size *buf_size;
230 	char	*fw_name[MFC_FW_MAX_VERSIONS];
231 	const char	*clk_names[MFC_MAX_CLOCKS];
232 	int		num_clocks;
233 	bool		use_clock_gating;
234 };
235 
236 /**
237  * struct s5p_mfc_priv_buf - represents internal used buffer
238  * @ofs:		offset of each buffer, will be used for MFC
239  * @virt:		kernel virtual address, only valid when the
240  *			buffer accessed by driver
241  * @dma:		DMA address, only valid when kernel DMA API used
242  * @size:		size of the buffer
243  * @ctx:		memory context (bank) used for this allocation
244  */
245 struct s5p_mfc_priv_buf {
246 	unsigned long	ofs;
247 	void		*virt;
248 	dma_addr_t	dma;
249 	size_t		size;
250 	unsigned int	ctx;
251 };
252 
253 /**
254  * struct s5p_mfc_dev - The struct containing driver internal parameters.
255  *
256  * @v4l2_dev:		v4l2_device
257  * @vfd_dec:		video device for decoding
258  * @vfd_enc:		video device for encoding
259  * @plat_dev:		platform device
260  * @mem_dev:		child devices of the memory banks
261  * @regs_base:		base address of the MFC hw registers
262  * @irq:		irq resource
263  * @dec_ctrl_handler:	control framework handler for decoding
264  * @enc_ctrl_handler:	control framework handler for encoding
265  * @pm:			power management control
266  * @variant:		MFC hardware variant information
267  * @num_inst:		counter of active MFC instances
268  * @irqlock:		lock for operations on videobuf2 queues
269  * @condlock:		lock for changing/checking if a context is ready to be
270  *			processed
271  * @mfc_mutex:		lock for video_device
272  * @int_cond:		variable used by the waitqueue
273  * @int_type:		type of last interrupt
274  * @int_err:		error number for last interrupt
275  * @queue:		waitqueue for waiting for completion of device commands
276  * @fw_buf:		the firmware buffer data structure
277  * @mem_size:		size of the firmware operation memory
278  * @mem_base:		base DMA address of the firmware operation memory
279  * @mem_bitmap:		bitmap for managing MFC internal buffer allocations
280  * @mem_virt:		virtual address of the firmware operation memory
281  * @dma_base:		address of the beginning of memory banks
282  * @hw_lock:		used for hardware locking
283  * @ctx:		array of driver contexts
284  * @curr_ctx:		number of the currently running context
285  * @ctx_work_bits:	used to mark which contexts are waiting for hardware
286  * @watchdog_cnt:	counter for the watchdog
287  * @watchdog_timer:	timer for the watchdog
288  * @watchdog_workqueue:	workqueue for the watchdog
289  * @watchdog_work:	worker for the watchdog
290  * @enter_suspend:	flag set when entering suspend
291  * @ctx_buf:		common context memory (MFCv6)
292  * @warn_start:		hardware error code from which warnings start
293  * @mfc_ops:		ops structure holding HW operation function pointers
294  * @mfc_cmds:		cmd structure holding HW commands function pointers
295  * @mfc_regs:		structure holding MFC registers
296  * @fw_ver:		loaded firmware sub-version
297  * @fw_get_done:	flag set when request_firmware() is complete and
298  *			copied into fw_buf
299  * @risc_on:		flag indicates RISC is on or off
300  *
301  */
302 struct s5p_mfc_dev {
303 	struct v4l2_device	v4l2_dev;
304 	struct video_device	*vfd_dec;
305 	struct video_device	*vfd_enc;
306 	struct platform_device	*plat_dev;
307 	struct device		*mem_dev[BANK_CTX_NUM];
308 	void __iomem		*regs_base;
309 	int			irq;
310 	struct v4l2_ctrl_handler dec_ctrl_handler;
311 	struct v4l2_ctrl_handler enc_ctrl_handler;
312 	struct s5p_mfc_pm	pm;
313 	const struct s5p_mfc_variant	*variant;
314 	int num_inst;
315 	spinlock_t irqlock;	/* lock when operating on context */
316 	spinlock_t condlock;	/* lock when changing/checking if a context is
317 					ready to be processed */
318 	struct mutex mfc_mutex; /* video_device lock */
319 	int int_cond;
320 	int int_type;
321 	unsigned int int_err;
322 	wait_queue_head_t queue;
323 	struct s5p_mfc_priv_buf fw_buf;
324 	size_t mem_size;
325 	dma_addr_t mem_base;
326 	unsigned long *mem_bitmap;
327 	void *mem_virt;
328 	dma_addr_t dma_base[BANK_CTX_NUM];
329 	unsigned long hw_lock;
330 	struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
331 	int curr_ctx;
332 	unsigned long ctx_work_bits;
333 	atomic_t watchdog_cnt;
334 	struct timer_list watchdog_timer;
335 	struct workqueue_struct *watchdog_workqueue;
336 	struct work_struct watchdog_work;
337 	unsigned long enter_suspend;
338 
339 	struct s5p_mfc_priv_buf ctx_buf;
340 	int warn_start;
341 	struct s5p_mfc_hw_ops *mfc_ops;
342 	struct s5p_mfc_hw_cmds *mfc_cmds;
343 	const struct s5p_mfc_regs *mfc_regs;
344 	enum s5p_mfc_fw_ver fw_ver;
345 	bool fw_get_done;
346 	bool risc_on; /* indicates if RISC is on or off */
347 };
348 
349 /*
350  * struct s5p_mfc_h264_enc_params - encoding parameters for h264
351  */
352 struct s5p_mfc_h264_enc_params {
353 	enum v4l2_mpeg_video_h264_profile profile;
354 	enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
355 	s8 loop_filter_alpha;
356 	s8 loop_filter_beta;
357 	enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
358 	u8 max_ref_pic;
359 	u8 num_ref_pic_4p;
360 	int _8x8_transform;
361 	int rc_mb_dark;
362 	int rc_mb_smooth;
363 	int rc_mb_static;
364 	int rc_mb_activity;
365 	int vui_sar;
366 	u8 vui_sar_idc;
367 	u16 vui_ext_sar_width;
368 	u16 vui_ext_sar_height;
369 	int open_gop;
370 	u16 open_gop_size;
371 	u8 rc_frame_qp;
372 	u8 rc_min_qp;
373 	u8 rc_max_qp;
374 	u8 rc_p_frame_qp;
375 	u8 rc_b_frame_qp;
376 	enum v4l2_mpeg_video_h264_level level_v4l2;
377 	int level;
378 	u16 cpb_size;
379 	int interlace;
380 	u8 hier_qp;
381 	u8 hier_qp_type;
382 	u8 hier_qp_layer;
383 	u8 hier_qp_layer_qp[7];
384 	u8 sei_frame_packing;
385 	u8 sei_fp_curr_frame_0;
386 	u8 sei_fp_arrangement_type;
387 
388 	u8 fmo;
389 	u8 fmo_map_type;
390 	u8 fmo_slice_grp;
391 	u8 fmo_chg_dir;
392 	u32 fmo_chg_rate;
393 	u32 fmo_run_len[4];
394 	u8 aso;
395 	u32 aso_slice_order[8];
396 };
397 
398 /*
399  * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
400  */
401 struct s5p_mfc_mpeg4_enc_params {
402 	/* MPEG4 Only */
403 	enum v4l2_mpeg_video_mpeg4_profile profile;
404 	int quarter_pixel;
405 	/* Common for MPEG4, H263 */
406 	u16 vop_time_res;
407 	u16 vop_frm_delta;
408 	u8 rc_frame_qp;
409 	u8 rc_min_qp;
410 	u8 rc_max_qp;
411 	u8 rc_p_frame_qp;
412 	u8 rc_b_frame_qp;
413 	enum v4l2_mpeg_video_mpeg4_level level_v4l2;
414 	int level;
415 };
416 
417 /*
418  * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
419  */
420 struct s5p_mfc_vp8_enc_params {
421 	u8 imd_4x4;
422 	enum v4l2_vp8_num_partitions num_partitions;
423 	enum v4l2_vp8_num_ref_frames num_ref;
424 	u8 filter_level;
425 	u8 filter_sharpness;
426 	u32 golden_frame_ref_period;
427 	enum v4l2_vp8_golden_frame_sel golden_frame_sel;
428 	u8 hier_layer;
429 	u8 hier_layer_qp[3];
430 	u8 rc_min_qp;
431 	u8 rc_max_qp;
432 	u8 rc_frame_qp;
433 	u8 rc_p_frame_qp;
434 	u8 profile;
435 };
436 
437 struct s5p_mfc_hevc_enc_params {
438 	enum v4l2_mpeg_video_hevc_profile profile;
439 	int level;
440 	enum v4l2_mpeg_video_h264_level level_v4l2;
441 	u8 tier;
442 	u32 rc_framerate;
443 	u8 rc_min_qp;
444 	u8 rc_max_qp;
445 	u8 rc_lcu_dark;
446 	u8 rc_lcu_smooth;
447 	u8 rc_lcu_static;
448 	u8 rc_lcu_activity;
449 	u8 rc_frame_qp;
450 	u8 rc_p_frame_qp;
451 	u8 rc_b_frame_qp;
452 	u8 max_partition_depth;
453 	u8 num_refs_for_p;
454 	u8 refreshtype;
455 	u16 refreshperiod;
456 	s32 lf_beta_offset_div2;
457 	s32 lf_tc_offset_div2;
458 	u8 loopfilter;
459 	u8 loopfilter_disable;
460 	u8 loopfilter_across;
461 	u8 nal_control_length_filed;
462 	u8 nal_control_user_ref;
463 	u8 nal_control_store_ref;
464 	u8 const_intra_period_enable;
465 	u8 lossless_cu_enable;
466 	u8 wavefront_enable;
467 	u8 enable_ltr;
468 	u8 hier_qp_enable;
469 	enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
470 	u8 num_hier_layer;
471 	u8 hier_qp_layer[7];
472 	u32 hier_bit_layer[7];
473 	u8 sign_data_hiding;
474 	u8 general_pb_enable;
475 	u8 temporal_id_enable;
476 	u8 strong_intra_smooth;
477 	u8 intra_pu_split_disable;
478 	u8 tmv_prediction_disable;
479 	u8 max_num_merge_mv;
480 	u8 eco_mode_enable;
481 	u8 encoding_nostartcode_enable;
482 	u8 size_of_length_field;
483 	u8 prepend_sps_pps_to_idr;
484 };
485 
486 /*
487  * struct s5p_mfc_enc_params - general encoding parameters
488  */
489 struct s5p_mfc_enc_params {
490 	u16 width;
491 	u16 height;
492 	u32 mv_h_range;
493 	u32 mv_v_range;
494 
495 	u16 gop_size;
496 	enum v4l2_mpeg_video_multi_slice_mode slice_mode;
497 	u16 slice_mb;
498 	u32 slice_bit;
499 	u16 intra_refresh_mb;
500 	int pad;
501 	u8 pad_luma;
502 	u8 pad_cb;
503 	u8 pad_cr;
504 	int rc_frame;
505 	int rc_mb;
506 	u32 rc_bitrate;
507 	u16 rc_reaction_coeff;
508 	u16 vbv_size;
509 	u32 vbv_delay;
510 
511 	enum v4l2_mpeg_video_header_mode seq_hdr_mode;
512 	enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
513 	int fixed_target_bit;
514 
515 	u8 num_b_frame;
516 	u32 rc_framerate_num;
517 	u32 rc_framerate_denom;
518 
519 	struct {
520 		struct s5p_mfc_h264_enc_params h264;
521 		struct s5p_mfc_mpeg4_enc_params mpeg4;
522 		struct s5p_mfc_vp8_enc_params vp8;
523 		struct s5p_mfc_hevc_enc_params hevc;
524 	} codec;
525 
526 };
527 
528 /*
529  * struct s5p_mfc_codec_ops - codec ops, used by encoding
530  */
531 struct s5p_mfc_codec_ops {
532 	/* initialization routines */
533 	int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
534 	int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
535 	/* execution routines */
536 	int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
537 	int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
538 };
539 
540 #define call_cop(c, op, args...)				\
541 	(((c)->c_ops->op) ?					\
542 		((c)->c_ops->op(args)) : 0)
543 
544 /**
545  * struct s5p_mfc_ctx - This struct contains the instance context
546  *
547  * @dev:		pointer to the s5p_mfc_dev of the device
548  * @fh:			struct v4l2_fh
549  * @num:		number of the context that this structure describes
550  * @int_cond:		variable used by the waitqueue
551  * @int_type:		type of the last interrupt
552  * @int_err:		error number received from MFC hw in the interrupt
553  * @queue:		waitqueue that can be used to wait for this context to
554  *			finish
555  * @src_fmt:		source pixelformat information
556  * @dst_fmt:		destination pixelformat information
557  * @vq_src:		vb2 queue for source buffers
558  * @vq_dst:		vb2 queue for destination buffers
559  * @src_queue:		driver internal queue for source buffers
560  * @dst_queue:		driver internal queue for destination buffers
561  * @src_queue_cnt:	number of buffers queued on the source internal queue
562  * @dst_queue_cnt:	number of buffers queued on the dest internal queue
563  * @type:		type of the instance - decoder or encoder
564  * @state:		state of the context
565  * @inst_no:		number of hw instance associated with the context
566  * @img_width:		width of the image that is decoded or encoded
567  * @img_height:		height of the image that is decoded or encoded
568  * @buf_width:		width of the buffer for processed image
569  * @buf_height:		height of the buffer for processed image
570  * @luma_size:		size of a luma plane
571  * @chroma_size:	size of a chroma plane
572  * @mv_size:		size of a motion vectors buffer
573  * @consumed_stream:	number of bytes that have been used so far from the
574  *			decoding buffer
575  * @dpb_flush_flag:	flag used to indicate that a DPB buffers are being
576  *			flushed
577  * @head_processed:	flag mentioning whether the header data is processed
578  *			completely or not
579  * @bank1:		handle to memory allocated for temporary buffers from
580  *			memory bank 1
581  * @bank2:		handle to memory allocated for temporary buffers from
582  *			memory bank 2
583  * @capture_state:	state of the capture buffers queue
584  * @output_state:	state of the output buffers queue
585  * @src_bufs:		information on allocated source buffers
586  * @src_bufs_cnt:	number of allocated source buffers
587  * @dst_bufs:		information on allocated destination buffers
588  * @dst_bufs_cnt:	number of allocated destination buffers
589  * @sequence:		counter for the sequence number for v4l2
590  * @dec_dst_flag:	flags for buffers queued in the hardware
591  * @dec_src_buf_size:	size of the buffer for source buffers in decoding
592  * @codec_mode:		number of codec mode used by MFC hw
593  * @slice_interface:	slice interface flag
594  * @loop_filter_mpeg4:	loop filter for MPEG4 flag
595  * @display_delay:	value of the display delay for H264
596  * @display_delay_enable:	display delay for H264 enable flag
597  * @after_packed_pb:	flag used to track buffer when stream is in
598  *			Packed PB format
599  * @sei_fp_parse:	enable/disable parsing of frame packing SEI information
600  * @pb_count:		count of the DPB buffers required by MFC hw
601  * @total_dpb_count:	count of DPB buffers with additional buffers
602  *			requested by the application
603  * @ctx:		context buffer information
604  * @dsc:		descriptor buffer information
605  * @shm:		shared memory buffer information
606  * @mv_count:		number of MV buffers allocated for decoding
607  * @enc_params:		encoding parameters for MFC
608  * @enc_dst_buf_size:	size of the buffers for encoder output
609  * @luma_dpb_size:	dpb buffer size for luma
610  * @chroma_dpb_size:	dpb buffer size for chroma
611  * @me_buffer_size:	size of the motion estimation buffer
612  * @tmv_buffer_size:	size of temporal predictor motion vector buffer
613  * @frame_type:		used to force the type of the next encoded frame
614  * @ref_queue:		list of the reference buffers for encoding
615  * @force_frame_type:	encoder's frame type forcing control
616  * @ref_queue_cnt:	number of the buffers in the reference list
617  * @slice_size:		slice size
618  * @slice_mode:		mode of dividing frames into slices
619  * @c_ops:		ops for encoding
620  * @ctrls:		array of controls, used when adding controls to the
621  *			v4l2 control framework
622  * @ctrl_handler:	handler for v4l2 framework
623  * @scratch_buf_size:	scratch buffer size
624  */
625 struct s5p_mfc_ctx {
626 	struct s5p_mfc_dev *dev;
627 	struct v4l2_fh fh;
628 
629 	int num;
630 
631 	int int_cond;
632 	int int_type;
633 	unsigned int int_err;
634 	wait_queue_head_t queue;
635 
636 	struct s5p_mfc_fmt *src_fmt;
637 	struct s5p_mfc_fmt *dst_fmt;
638 
639 	struct vb2_queue vq_src;
640 	struct vb2_queue vq_dst;
641 
642 	struct list_head src_queue;
643 	struct list_head dst_queue;
644 
645 	unsigned int src_queue_cnt;
646 	unsigned int dst_queue_cnt;
647 
648 	enum s5p_mfc_inst_type type;
649 	enum s5p_mfc_inst_state state;
650 	int inst_no;
651 
652 	/* Image parameters */
653 	int img_width;
654 	int img_height;
655 	int buf_width;
656 	int buf_height;
657 
658 	int luma_size;
659 	int chroma_size;
660 	int mv_size;
661 
662 	unsigned long consumed_stream;
663 
664 	unsigned int dpb_flush_flag;
665 	unsigned int head_processed;
666 
667 	struct s5p_mfc_priv_buf bank1;
668 	struct s5p_mfc_priv_buf bank2;
669 
670 	enum s5p_mfc_queue_state capture_state;
671 	enum s5p_mfc_queue_state output_state;
672 
673 	struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
674 	int src_bufs_cnt;
675 	struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
676 	int dst_bufs_cnt;
677 
678 	unsigned int sequence;
679 	unsigned long dec_dst_flag;
680 	size_t dec_src_buf_size;
681 
682 	/* Control values */
683 	int codec_mode;
684 	int slice_interface;
685 	int loop_filter_mpeg4;
686 	int display_delay;
687 	int display_delay_enable;
688 	int after_packed_pb;
689 	int sei_fp_parse;
690 
691 	int pb_count;
692 	int total_dpb_count;
693 	int mv_count;
694 	/* Buffers */
695 	struct s5p_mfc_priv_buf ctx;
696 	struct s5p_mfc_priv_buf dsc;
697 	struct s5p_mfc_priv_buf shm;
698 
699 	struct s5p_mfc_enc_params enc_params;
700 
701 	size_t enc_dst_buf_size;
702 	size_t luma_dpb_size;
703 	size_t chroma_dpb_size;
704 	size_t me_buffer_size;
705 	size_t tmv_buffer_size;
706 
707 	enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
708 
709 	struct list_head ref_queue;
710 	unsigned int ref_queue_cnt;
711 
712 	enum v4l2_mpeg_video_multi_slice_mode slice_mode;
713 	union {
714 		unsigned int mb;
715 		unsigned int bits;
716 	} slice_size;
717 
718 	const struct s5p_mfc_codec_ops *c_ops;
719 
720 	struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
721 	struct v4l2_ctrl_handler ctrl_handler;
722 	size_t scratch_buf_size;
723 };
724 
725 /*
726  * struct s5p_mfc_fmt -	structure used to store information about pixelformats
727  *			used by the MFC
728  */
729 struct s5p_mfc_fmt {
730 	u32 fourcc;
731 	u32 codec_mode;
732 	enum s5p_mfc_fmt_type type;
733 	u32 num_planes;
734 	u32 versions;
735 	u32 flags;
736 };
737 
738 /*
739  * struct mfc_control -	structure used to store information about MFC controls
740  *			it is used to initialize the control framework.
741  */
742 struct mfc_control {
743 	__u32			id;
744 	enum v4l2_ctrl_type	type;
745 	__u8			name[32];  /* Whatever */
746 	__s32			minimum;   /* Note signedness */
747 	__s32			maximum;
748 	__s32			step;
749 	__u32			menu_skip_mask;
750 	__s32			default_value;
751 	__u32			flags;
752 	__u32			reserved[2];
753 	__u8			is_volatile;
754 };
755 
756 /* Macro for making hardware specific calls */
757 #define s5p_mfc_hw_call(f, op, args...) \
758 	((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
759 
760 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
761 #define ctrl_to_ctx(__ctrl) \
762 	container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
763 
764 void clear_work_bit(struct s5p_mfc_ctx *ctx);
765 void set_work_bit(struct s5p_mfc_ctx *ctx);
766 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
767 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
768 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
769 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
770 
771 #define HAS_PORTNUM(dev)	(dev ? (dev->variant ? \
772 				(dev->variant->port_num ? 1 : 0) : 0) : 0)
773 #define IS_TWOPORT(dev)		(dev->variant->port_num == 2 ? 1 : 0)
774 #define IS_MFCV6_PLUS(dev)	(dev->variant->version >= 0x60 ? 1 : 0)
775 #define IS_MFCV7_PLUS(dev)	(dev->variant->version >= 0x70 ? 1 : 0)
776 #define IS_MFCV8_PLUS(dev)	(dev->variant->version >= 0x80 ? 1 : 0)
777 #define IS_MFCV10(dev)		(dev->variant->version >= 0xA0 ? 1 : 0)
778 #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))
779 
780 #define MFC_V5_BIT	BIT(0)
781 #define MFC_V6_BIT	BIT(1)
782 #define MFC_V7_BIT	BIT(2)
783 #define MFC_V8_BIT	BIT(3)
784 #define MFC_V10_BIT	BIT(5)
785 
786 #define MFC_V5PLUS_BITS		(MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
787 					MFC_V8_BIT | MFC_V10_BIT)
788 #define MFC_V6PLUS_BITS		(MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
789 					MFC_V10_BIT)
790 #define MFC_V7PLUS_BITS		(MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)
791 
792 #endif /* S5P_MFC_COMMON_H_ */
793