xref: /openbmc/qemu/hw/scsi/megasas.c (revision 2d7b39a6)
1 /*
2  * QEMU MegaRAID SAS 8708EM2 Host Bus Adapter emulation
3  * Based on the linux driver code at drivers/scsi/megaraid
4  *
5  * Copyright (c) 2009-2012 Hannes Reinecke, SUSE Labs
6  *
7  * This library is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU Lesser General Public
9  * License as published by the Free Software Foundation; either
10  * version 2.1 of the License, or (at your option) any later version.
11  *
12  * This library is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15  * Lesser General Public License for more details.
16  *
17  * You should have received a copy of the GNU Lesser General Public
18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "hw/pci/pci.h"
23 #include "hw/qdev-properties.h"
24 #include "sysemu/dma.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/rtc.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "qemu/iov.h"
30 #include "qemu/module.h"
31 #include "qemu/hw-version.h"
32 #include "hw/scsi/scsi.h"
33 #include "scsi/constants.h"
34 #include "trace.h"
35 #include "qapi/error.h"
36 #include "mfi.h"
37 #include "migration/vmstate.h"
38 #include "qom/object.h"
39 
40 #define MEGASAS_VERSION_GEN1 "1.70"
41 #define MEGASAS_VERSION_GEN2 "1.80"
42 #define MEGASAS_MAX_FRAMES 2048         /* Firmware limit at 65535 */
43 #define MEGASAS_DEFAULT_FRAMES 1000     /* Windows requires this */
44 #define MEGASAS_GEN2_DEFAULT_FRAMES 1008     /* Windows requires this */
45 #define MEGASAS_MIN_SGE 64
46 #define MEGASAS_MAX_SGE 128             /* Firmware limit */
47 #define MEGASAS_DEFAULT_SGE 80
48 #define MEGASAS_MAX_SECTORS 0xFFFF      /* No real limit */
49 #define MEGASAS_MAX_ARRAYS 128
50 
51 #define MEGASAS_HBA_SERIAL "QEMU123456"
52 #define NAA_LOCALLY_ASSIGNED_ID 0x3ULL
53 #define IEEE_COMPANY_LOCALLY_ASSIGNED 0x525400
54 
55 #define MEGASAS_FLAG_USE_JBOD      0
56 #define MEGASAS_MASK_USE_JBOD      (1 << MEGASAS_FLAG_USE_JBOD)
57 #define MEGASAS_FLAG_USE_QUEUE64   1
58 #define MEGASAS_MASK_USE_QUEUE64   (1 << MEGASAS_FLAG_USE_QUEUE64)
59 
60 typedef struct MegasasCmd {
61     uint32_t index;
62     uint16_t flags;
63     uint16_t count;
64     uint64_t context;
65 
66     hwaddr pa;
67     hwaddr pa_size;
68     uint32_t dcmd_opcode;
69     union mfi_frame *frame;
70     SCSIRequest *req;
71     QEMUSGList qsg;
72     void *iov_buf;
73     size_t iov_size;
74     size_t iov_offset;
75     struct MegasasState *state;
76 } MegasasCmd;
77 
78 struct MegasasState {
79     /*< private >*/
80     PCIDevice parent_obj;
81     /*< public >*/
82 
83     MemoryRegion mmio_io;
84     MemoryRegion port_io;
85     MemoryRegion queue_io;
86     uint32_t frame_hi;
87 
88     uint32_t fw_state;
89     uint32_t fw_sge;
90     uint32_t fw_cmds;
91     uint32_t flags;
92     uint32_t fw_luns;
93     uint32_t intr_mask;
94     uint32_t doorbell;
95     uint32_t busy;
96     uint32_t diag;
97     uint32_t adp_reset;
98     OnOffAuto msi;
99     OnOffAuto msix;
100 
101     MegasasCmd *event_cmd;
102     uint16_t event_locale;
103     int event_class;
104     uint32_t event_count;
105     uint32_t shutdown_event;
106     uint32_t boot_event;
107 
108     uint64_t sas_addr;
109     char *hba_serial;
110 
111     uint64_t reply_queue_pa;
112     void *reply_queue;
113     uint16_t reply_queue_len;
114     uint32_t reply_queue_head;
115     uint32_t reply_queue_tail;
116     uint64_t consumer_pa;
117     uint64_t producer_pa;
118 
119     MegasasCmd frames[MEGASAS_MAX_FRAMES];
120     DECLARE_BITMAP(frame_map, MEGASAS_MAX_FRAMES);
121     SCSIBus bus;
122 };
123 typedef struct MegasasState MegasasState;
124 
125 struct MegasasBaseClass {
126     PCIDeviceClass parent_class;
127     const char *product_name;
128     const char *product_version;
129     int mmio_bar;
130     int ioport_bar;
131     int osts;
132 };
133 typedef struct MegasasBaseClass MegasasBaseClass;
134 
135 #define TYPE_MEGASAS_BASE "megasas-base"
136 #define TYPE_MEGASAS_GEN1 "megasas"
137 #define TYPE_MEGASAS_GEN2 "megasas-gen2"
138 
DECLARE_OBJ_CHECKERS(MegasasState,MegasasBaseClass,MEGASAS,TYPE_MEGASAS_BASE)139 DECLARE_OBJ_CHECKERS(MegasasState, MegasasBaseClass,
140                      MEGASAS, TYPE_MEGASAS_BASE)
141 
142 
143 #define MEGASAS_INTR_DISABLED_MASK 0xFFFFFFFF
144 
145 static bool megasas_intr_enabled(MegasasState *s)
146 {
147     if ((s->intr_mask & MEGASAS_INTR_DISABLED_MASK) !=
148         MEGASAS_INTR_DISABLED_MASK) {
149         return true;
150     }
151     return false;
152 }
153 
megasas_use_queue64(MegasasState * s)154 static bool megasas_use_queue64(MegasasState *s)
155 {
156     return s->flags & MEGASAS_MASK_USE_QUEUE64;
157 }
158 
megasas_use_msix(MegasasState * s)159 static bool megasas_use_msix(MegasasState *s)
160 {
161     return s->msix != ON_OFF_AUTO_OFF;
162 }
163 
megasas_is_jbod(MegasasState * s)164 static bool megasas_is_jbod(MegasasState *s)
165 {
166     return s->flags & MEGASAS_MASK_USE_JBOD;
167 }
168 
megasas_frame_set_cmd_status(MegasasState * s,unsigned long frame,uint8_t v)169 static void megasas_frame_set_cmd_status(MegasasState *s,
170                                          unsigned long frame, uint8_t v)
171 {
172     PCIDevice *pci = &s->parent_obj;
173     stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, cmd_status),
174                 v, MEMTXATTRS_UNSPECIFIED);
175 }
176 
megasas_frame_set_scsi_status(MegasasState * s,unsigned long frame,uint8_t v)177 static void megasas_frame_set_scsi_status(MegasasState *s,
178                                           unsigned long frame, uint8_t v)
179 {
180     PCIDevice *pci = &s->parent_obj;
181     stb_pci_dma(pci, frame + offsetof(struct mfi_frame_header, scsi_status),
182                 v, MEMTXATTRS_UNSPECIFIED);
183 }
184 
mfi_frame_desc(unsigned int cmd)185 static inline const char *mfi_frame_desc(unsigned int cmd)
186 {
187     static const char *mfi_frame_descs[] = {
188         "MFI init", "LD Read", "LD Write", "LD SCSI", "PD SCSI",
189         "MFI Doorbell", "MFI Abort", "MFI SMP", "MFI Stop"
190     };
191 
192     if (cmd < ARRAY_SIZE(mfi_frame_descs)) {
193         return mfi_frame_descs[cmd];
194     }
195 
196     return "Unknown";
197 }
198 
199 /*
200  * Context is considered opaque, but the HBA firmware is running
201  * in little endian mode. So convert it to little endian, too.
202  */
megasas_frame_get_context(MegasasState * s,unsigned long frame)203 static uint64_t megasas_frame_get_context(MegasasState *s,
204                                           unsigned long frame)
205 {
206     PCIDevice *pci = &s->parent_obj;
207     uint64_t val;
208 
209     ldq_le_pci_dma(pci, frame + offsetof(struct mfi_frame_header, context),
210                    &val, MEMTXATTRS_UNSPECIFIED);
211 
212     return val;
213 }
214 
megasas_frame_is_ieee_sgl(MegasasCmd * cmd)215 static bool megasas_frame_is_ieee_sgl(MegasasCmd *cmd)
216 {
217     return cmd->flags & MFI_FRAME_IEEE_SGL;
218 }
219 
megasas_frame_is_sgl64(MegasasCmd * cmd)220 static bool megasas_frame_is_sgl64(MegasasCmd *cmd)
221 {
222     return cmd->flags & MFI_FRAME_SGL64;
223 }
224 
megasas_frame_is_sense64(MegasasCmd * cmd)225 static bool megasas_frame_is_sense64(MegasasCmd *cmd)
226 {
227     return cmd->flags & MFI_FRAME_SENSE64;
228 }
229 
megasas_sgl_get_addr(MegasasCmd * cmd,union mfi_sgl * sgl)230 static uint64_t megasas_sgl_get_addr(MegasasCmd *cmd,
231                                      union mfi_sgl *sgl)
232 {
233     uint64_t addr;
234 
235     if (megasas_frame_is_ieee_sgl(cmd)) {
236         addr = le64_to_cpu(sgl->sg_skinny->addr);
237     } else if (megasas_frame_is_sgl64(cmd)) {
238         addr = le64_to_cpu(sgl->sg64->addr);
239     } else {
240         addr = le32_to_cpu(sgl->sg32->addr);
241     }
242     return addr;
243 }
244 
megasas_sgl_get_len(MegasasCmd * cmd,union mfi_sgl * sgl)245 static uint32_t megasas_sgl_get_len(MegasasCmd *cmd,
246                                     union mfi_sgl *sgl)
247 {
248     uint32_t len;
249 
250     if (megasas_frame_is_ieee_sgl(cmd)) {
251         len = le32_to_cpu(sgl->sg_skinny->len);
252     } else if (megasas_frame_is_sgl64(cmd)) {
253         len = le32_to_cpu(sgl->sg64->len);
254     } else {
255         len = le32_to_cpu(sgl->sg32->len);
256     }
257     return len;
258 }
259 
megasas_sgl_next(MegasasCmd * cmd,union mfi_sgl * sgl)260 static union mfi_sgl *megasas_sgl_next(MegasasCmd *cmd,
261                                        union mfi_sgl *sgl)
262 {
263     uint8_t *next = (uint8_t *)sgl;
264 
265     if (megasas_frame_is_ieee_sgl(cmd)) {
266         next += sizeof(struct mfi_sg_skinny);
267     } else if (megasas_frame_is_sgl64(cmd)) {
268         next += sizeof(struct mfi_sg64);
269     } else {
270         next += sizeof(struct mfi_sg32);
271     }
272 
273     if (next >= (uint8_t *)cmd->frame + cmd->pa_size) {
274         return NULL;
275     }
276     return (union mfi_sgl *)next;
277 }
278 
279 static void megasas_soft_reset(MegasasState *s);
280 
megasas_map_sgl(MegasasState * s,MegasasCmd * cmd,union mfi_sgl * sgl)281 static int megasas_map_sgl(MegasasState *s, MegasasCmd *cmd, union mfi_sgl *sgl)
282 {
283     int i;
284     int iov_count = 0;
285     size_t iov_size = 0;
286 
287     cmd->flags = le16_to_cpu(cmd->frame->header.flags);
288     iov_count = cmd->frame->header.sge_count;
289     if (!iov_count || iov_count > MEGASAS_MAX_SGE) {
290         trace_megasas_iovec_sgl_overflow(cmd->index, iov_count,
291                                          MEGASAS_MAX_SGE);
292         return -1;
293     }
294     pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), iov_count);
295     for (i = 0; i < iov_count; i++) {
296         dma_addr_t iov_pa, iov_size_p;
297 
298         if (!sgl) {
299             trace_megasas_iovec_sgl_underflow(cmd->index, i);
300             goto unmap;
301         }
302         iov_pa = megasas_sgl_get_addr(cmd, sgl);
303         iov_size_p = megasas_sgl_get_len(cmd, sgl);
304         if (!iov_pa || !iov_size_p) {
305             trace_megasas_iovec_sgl_invalid(cmd->index, i,
306                                             iov_pa, iov_size_p);
307             goto unmap;
308         }
309         qemu_sglist_add(&cmd->qsg, iov_pa, iov_size_p);
310         sgl = megasas_sgl_next(cmd, sgl);
311         iov_size += (size_t)iov_size_p;
312     }
313     if (cmd->iov_size > iov_size) {
314         trace_megasas_iovec_overflow(cmd->index, iov_size, cmd->iov_size);
315         goto unmap;
316     } else if (cmd->iov_size < iov_size) {
317         trace_megasas_iovec_underflow(cmd->index, iov_size, cmd->iov_size);
318     }
319     cmd->iov_offset = 0;
320     return 0;
321 unmap:
322     qemu_sglist_destroy(&cmd->qsg);
323     return -1;
324 }
325 
326 /*
327  * passthrough sense and io sense are at the same offset
328  */
megasas_build_sense(MegasasCmd * cmd,uint8_t * sense_ptr,uint8_t sense_len)329 static int megasas_build_sense(MegasasCmd *cmd, uint8_t *sense_ptr,
330     uint8_t sense_len)
331 {
332     PCIDevice *pcid = PCI_DEVICE(cmd->state);
333     uint32_t pa_hi = 0, pa_lo;
334     hwaddr pa;
335     int frame_sense_len;
336 
337     frame_sense_len = cmd->frame->header.sense_len;
338     if (sense_len > frame_sense_len) {
339         sense_len = frame_sense_len;
340     }
341     if (sense_len) {
342         pa_lo = le32_to_cpu(cmd->frame->pass.sense_addr_lo);
343         if (megasas_frame_is_sense64(cmd)) {
344             pa_hi = le32_to_cpu(cmd->frame->pass.sense_addr_hi);
345         }
346         pa = ((uint64_t) pa_hi << 32) | pa_lo;
347         pci_dma_write(pcid, pa, sense_ptr, sense_len);
348         cmd->frame->header.sense_len = sense_len;
349     }
350     return sense_len;
351 }
352 
megasas_write_sense(MegasasCmd * cmd,SCSISense sense)353 static void megasas_write_sense(MegasasCmd *cmd, SCSISense sense)
354 {
355     uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
356     uint8_t sense_len = 18;
357 
358     memset(sense_buf, 0, sense_len);
359     sense_buf[0] = 0xf0;
360     sense_buf[2] = sense.key;
361     sense_buf[7] = 10;
362     sense_buf[12] = sense.asc;
363     sense_buf[13] = sense.ascq;
364     megasas_build_sense(cmd, sense_buf, sense_len);
365 }
366 
megasas_copy_sense(MegasasCmd * cmd)367 static void megasas_copy_sense(MegasasCmd *cmd)
368 {
369     uint8_t sense_buf[SCSI_SENSE_BUF_SIZE];
370     uint8_t sense_len;
371 
372     sense_len = scsi_req_get_sense(cmd->req, sense_buf,
373                                    SCSI_SENSE_BUF_SIZE);
374     megasas_build_sense(cmd, sense_buf, sense_len);
375 }
376 
377 /*
378  * Format an INQUIRY CDB
379  */
megasas_setup_inquiry(uint8_t * cdb,int pg,int len)380 static int megasas_setup_inquiry(uint8_t *cdb, int pg, int len)
381 {
382     memset(cdb, 0, 6);
383     cdb[0] = INQUIRY;
384     if (pg > 0) {
385         cdb[1] = 0x1;
386         cdb[2] = pg;
387     }
388     stw_be_p(&cdb[3], len);
389     return len;
390 }
391 
392 /*
393  * Encode lba and len into a READ_16/WRITE_16 CDB
394  */
megasas_encode_lba(uint8_t * cdb,uint64_t lba,uint32_t len,bool is_write)395 static void megasas_encode_lba(uint8_t *cdb, uint64_t lba,
396                                uint32_t len, bool is_write)
397 {
398     memset(cdb, 0x0, 16);
399     if (is_write) {
400         cdb[0] = WRITE_16;
401     } else {
402         cdb[0] = READ_16;
403     }
404     stq_be_p(&cdb[2], lba);
405     stl_be_p(&cdb[2 + 8], len);
406 }
407 
408 /*
409  * Utility functions
410  */
megasas_fw_time(void)411 static uint64_t megasas_fw_time(void)
412 {
413     struct tm curtime;
414 
415     qemu_get_timedate(&curtime, 0);
416     return ((uint64_t)curtime.tm_sec & 0xff) << 48 |
417         ((uint64_t)curtime.tm_min & 0xff)  << 40 |
418         ((uint64_t)curtime.tm_hour & 0xff) << 32 |
419         ((uint64_t)curtime.tm_mday & 0xff) << 24 |
420         ((uint64_t)curtime.tm_mon & 0xff)  << 16 |
421         ((uint64_t)(curtime.tm_year + 1900) & 0xffff);
422 }
423 
424 /*
425  * Default disk sata address
426  * 0x1221 is the magic number as
427  * present in real hardware,
428  * so use it here, too.
429  */
megasas_get_sata_addr(uint16_t id)430 static uint64_t megasas_get_sata_addr(uint16_t id)
431 {
432     uint64_t addr = (0x1221ULL << 48);
433     return addr | ((uint64_t)id << 24);
434 }
435 
436 /*
437  * Frame handling
438  */
megasas_next_index(MegasasState * s,int index,int limit)439 static int megasas_next_index(MegasasState *s, int index, int limit)
440 {
441     index++;
442     if (index == limit) {
443         index = 0;
444     }
445     return index;
446 }
447 
megasas_lookup_frame(MegasasState * s,hwaddr frame)448 static MegasasCmd *megasas_lookup_frame(MegasasState *s,
449     hwaddr frame)
450 {
451     MegasasCmd *cmd = NULL;
452     int num = 0, index;
453 
454     index = s->reply_queue_head;
455 
456     while (num < s->fw_cmds && index < MEGASAS_MAX_FRAMES) {
457         if (s->frames[index].pa && s->frames[index].pa == frame) {
458             cmd = &s->frames[index];
459             break;
460         }
461         index = megasas_next_index(s, index, s->fw_cmds);
462         num++;
463     }
464 
465     return cmd;
466 }
467 
megasas_unmap_frame(MegasasState * s,MegasasCmd * cmd)468 static void megasas_unmap_frame(MegasasState *s, MegasasCmd *cmd)
469 {
470     PCIDevice *p = PCI_DEVICE(s);
471 
472     if (cmd->pa_size) {
473         pci_dma_unmap(p, cmd->frame, cmd->pa_size, 0, 0);
474     }
475     cmd->frame = NULL;
476     cmd->pa = 0;
477     cmd->pa_size = 0;
478     qemu_sglist_destroy(&cmd->qsg);
479     clear_bit(cmd->index, s->frame_map);
480 }
481 
482 /*
483  * This absolutely needs to be locked if
484  * qemu ever goes multithreaded.
485  */
megasas_enqueue_frame(MegasasState * s,hwaddr frame,uint64_t context,int count)486 static MegasasCmd *megasas_enqueue_frame(MegasasState *s,
487     hwaddr frame, uint64_t context, int count)
488 {
489     PCIDevice *pcid = PCI_DEVICE(s);
490     MegasasCmd *cmd = NULL;
491     int frame_size = MEGASAS_MAX_SGE * sizeof(union mfi_sgl);
492     hwaddr frame_size_p = frame_size;
493     unsigned long index;
494 
495     index = 0;
496     while (index < s->fw_cmds) {
497         index = find_next_zero_bit(s->frame_map, s->fw_cmds, index);
498         if (!s->frames[index].pa)
499             break;
500         /* Busy frame found */
501         trace_megasas_qf_mapped(index);
502     }
503     if (index >= s->fw_cmds) {
504         /* All frames busy */
505         trace_megasas_qf_busy(frame);
506         return NULL;
507     }
508     cmd = &s->frames[index];
509     set_bit(index, s->frame_map);
510     trace_megasas_qf_new(index, frame);
511 
512     cmd->pa = frame;
513     /* Map all possible frames */
514     cmd->frame = pci_dma_map(pcid, frame, &frame_size_p, 0);
515     if (!cmd->frame || frame_size_p != frame_size) {
516         trace_megasas_qf_map_failed(cmd->index, (unsigned long)frame);
517         if (cmd->frame) {
518             megasas_unmap_frame(s, cmd);
519         }
520         s->event_count++;
521         return NULL;
522     }
523     cmd->pa_size = frame_size_p;
524     cmd->context = context;
525     if (!megasas_use_queue64(s)) {
526         cmd->context &= (uint64_t)0xFFFFFFFF;
527     }
528     cmd->count = count;
529     cmd->dcmd_opcode = -1;
530     s->busy++;
531 
532     if (s->consumer_pa) {
533         ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail,
534                        MEMTXATTRS_UNSPECIFIED);
535     }
536     trace_megasas_qf_enqueue(cmd->index, cmd->count, cmd->context,
537                              s->reply_queue_head, s->reply_queue_tail, s->busy);
538 
539     return cmd;
540 }
541 
megasas_complete_frame(MegasasState * s,uint64_t context)542 static void megasas_complete_frame(MegasasState *s, uint64_t context)
543 {
544     const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
545     PCIDevice *pci_dev = PCI_DEVICE(s);
546     int tail, queue_offset;
547 
548     /* Decrement busy count */
549     s->busy--;
550     if (s->reply_queue_pa) {
551         /*
552          * Put command on the reply queue.
553          * Context is opaque, but emulation is running in
554          * little endian. So convert it.
555          */
556         if (megasas_use_queue64(s)) {
557             queue_offset = s->reply_queue_head * sizeof(uint64_t);
558             stq_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset,
559                            context, attrs);
560         } else {
561             queue_offset = s->reply_queue_head * sizeof(uint32_t);
562             stl_le_pci_dma(pci_dev, s->reply_queue_pa + queue_offset,
563                            context, attrs);
564         }
565         ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attrs);
566         trace_megasas_qf_complete(context, s->reply_queue_head,
567                                   s->reply_queue_tail, s->busy);
568     }
569 
570     if (megasas_intr_enabled(s)) {
571         /* Update reply queue pointer */
572         ldl_le_pci_dma(pci_dev, s->consumer_pa, &s->reply_queue_tail, attrs);
573         tail = s->reply_queue_head;
574         s->reply_queue_head = megasas_next_index(s, tail, s->fw_cmds);
575         trace_megasas_qf_update(s->reply_queue_head, s->reply_queue_tail,
576                                 s->busy);
577         stl_le_pci_dma(pci_dev, s->producer_pa, s->reply_queue_head, attrs);
578         /* Notify HBA */
579         if (msix_enabled(pci_dev)) {
580             trace_megasas_msix_raise(0);
581             msix_notify(pci_dev, 0);
582         } else if (msi_enabled(pci_dev)) {
583             trace_megasas_msi_raise(0);
584             msi_notify(pci_dev, 0);
585         } else {
586             s->doorbell++;
587             if (s->doorbell == 1) {
588                 trace_megasas_irq_raise();
589                 pci_irq_assert(pci_dev);
590             }
591         }
592     } else {
593         trace_megasas_qf_complete_noirq(context);
594     }
595 }
596 
megasas_complete_command(MegasasCmd * cmd)597 static void megasas_complete_command(MegasasCmd *cmd)
598 {
599     cmd->iov_size = 0;
600     cmd->iov_offset = 0;
601 
602     cmd->req->hba_private = NULL;
603     scsi_req_unref(cmd->req);
604     cmd->req = NULL;
605 
606     megasas_unmap_frame(cmd->state, cmd);
607     megasas_complete_frame(cmd->state, cmd->context);
608 }
609 
megasas_reset_frames(MegasasState * s)610 static void megasas_reset_frames(MegasasState *s)
611 {
612     int i;
613     MegasasCmd *cmd;
614 
615     for (i = 0; i < s->fw_cmds; i++) {
616         cmd = &s->frames[i];
617         if (cmd->pa) {
618             megasas_unmap_frame(s, cmd);
619         }
620     }
621     bitmap_zero(s->frame_map, MEGASAS_MAX_FRAMES);
622 }
623 
megasas_abort_command(MegasasCmd * cmd)624 static void megasas_abort_command(MegasasCmd *cmd)
625 {
626     /* Never abort internal commands.  */
627     if (cmd->dcmd_opcode != -1) {
628         return;
629     }
630     if (cmd->req != NULL) {
631         scsi_req_cancel(cmd->req);
632     }
633 }
634 
megasas_init_firmware(MegasasState * s,MegasasCmd * cmd)635 static int megasas_init_firmware(MegasasState *s, MegasasCmd *cmd)
636 {
637     const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
638     PCIDevice *pcid = PCI_DEVICE(s);
639     uint32_t pa_hi, pa_lo;
640     hwaddr iq_pa, initq_size = sizeof(struct mfi_init_qinfo);
641     struct mfi_init_qinfo *initq = NULL;
642     uint32_t flags;
643     int ret = MFI_STAT_OK;
644 
645     if (s->reply_queue_pa) {
646         trace_megasas_initq_mapped(s->reply_queue_pa);
647         goto out;
648     }
649     pa_lo = le32_to_cpu(cmd->frame->init.qinfo_new_addr_lo);
650     pa_hi = le32_to_cpu(cmd->frame->init.qinfo_new_addr_hi);
651     iq_pa = (((uint64_t) pa_hi << 32) | pa_lo);
652     trace_megasas_init_firmware((uint64_t)iq_pa);
653     initq = pci_dma_map(pcid, iq_pa, &initq_size, 0);
654     if (!initq || initq_size != sizeof(*initq)) {
655         trace_megasas_initq_map_failed(cmd->index);
656         s->event_count++;
657         ret = MFI_STAT_MEMORY_NOT_AVAILABLE;
658         goto out;
659     }
660     s->reply_queue_len = le32_to_cpu(initq->rq_entries) & 0xFFFF;
661     if (s->reply_queue_len > s->fw_cmds) {
662         trace_megasas_initq_mismatch(s->reply_queue_len, s->fw_cmds);
663         s->event_count++;
664         ret = MFI_STAT_INVALID_PARAMETER;
665         goto out;
666     }
667     pa_lo = le32_to_cpu(initq->rq_addr_lo);
668     pa_hi = le32_to_cpu(initq->rq_addr_hi);
669     s->reply_queue_pa = ((uint64_t) pa_hi << 32) | pa_lo;
670     pa_lo = le32_to_cpu(initq->ci_addr_lo);
671     pa_hi = le32_to_cpu(initq->ci_addr_hi);
672     s->consumer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
673     pa_lo = le32_to_cpu(initq->pi_addr_lo);
674     pa_hi = le32_to_cpu(initq->pi_addr_hi);
675     s->producer_pa = ((uint64_t) pa_hi << 32) | pa_lo;
676     ldl_le_pci_dma(pcid, s->producer_pa, &s->reply_queue_head, attrs);
677     s->reply_queue_head %= MEGASAS_MAX_FRAMES;
678     ldl_le_pci_dma(pcid, s->consumer_pa, &s->reply_queue_tail, attrs);
679     s->reply_queue_tail %= MEGASAS_MAX_FRAMES;
680     flags = le32_to_cpu(initq->flags);
681     if (flags & MFI_QUEUE_FLAG_CONTEXT64) {
682         s->flags |= MEGASAS_MASK_USE_QUEUE64;
683     }
684     trace_megasas_init_queue((unsigned long)s->reply_queue_pa,
685                              s->reply_queue_len, s->reply_queue_head,
686                              s->reply_queue_tail, flags);
687     megasas_reset_frames(s);
688     s->fw_state = MFI_FWSTATE_OPERATIONAL;
689 out:
690     if (initq) {
691         pci_dma_unmap(pcid, initq, initq_size, 0, 0);
692     }
693     return ret;
694 }
695 
megasas_map_dcmd(MegasasState * s,MegasasCmd * cmd)696 static int megasas_map_dcmd(MegasasState *s, MegasasCmd *cmd)
697 {
698     dma_addr_t iov_pa, iov_size;
699     int iov_count;
700 
701     cmd->flags = le16_to_cpu(cmd->frame->header.flags);
702     iov_count = cmd->frame->header.sge_count;
703     if (!iov_count) {
704         trace_megasas_dcmd_zero_sge(cmd->index);
705         cmd->iov_size = 0;
706         return 0;
707     } else if (iov_count > 1) {
708         trace_megasas_dcmd_invalid_sge(cmd->index, iov_count);
709         cmd->iov_size = 0;
710         return -EINVAL;
711     }
712     iov_pa = megasas_sgl_get_addr(cmd, &cmd->frame->dcmd.sgl);
713     iov_size = megasas_sgl_get_len(cmd, &cmd->frame->dcmd.sgl);
714     pci_dma_sglist_init(&cmd->qsg, PCI_DEVICE(s), 1);
715     qemu_sglist_add(&cmd->qsg, iov_pa, iov_size);
716     cmd->iov_size = iov_size;
717     return 0;
718 }
719 
megasas_finish_dcmd(MegasasCmd * cmd,uint32_t iov_size)720 static void megasas_finish_dcmd(MegasasCmd *cmd, uint32_t iov_size)
721 {
722     trace_megasas_finish_dcmd(cmd->index, iov_size);
723 
724     if (iov_size > cmd->iov_size) {
725         if (megasas_frame_is_ieee_sgl(cmd)) {
726             cmd->frame->dcmd.sgl.sg_skinny->len = cpu_to_le32(iov_size);
727         } else if (megasas_frame_is_sgl64(cmd)) {
728             cmd->frame->dcmd.sgl.sg64->len = cpu_to_le32(iov_size);
729         } else {
730             cmd->frame->dcmd.sgl.sg32->len = cpu_to_le32(iov_size);
731         }
732     }
733 }
734 
megasas_ctrl_get_info(MegasasState * s,MegasasCmd * cmd)735 static int megasas_ctrl_get_info(MegasasState *s, MegasasCmd *cmd)
736 {
737     PCIDevice *pci_dev = PCI_DEVICE(s);
738     PCIDeviceClass *pci_class = PCI_DEVICE_GET_CLASS(pci_dev);
739     MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
740     struct mfi_ctrl_info info;
741     size_t dcmd_size = sizeof(info);
742     BusChild *kid;
743     int num_pd_disks = 0;
744     dma_addr_t residual;
745 
746     memset(&info, 0x0, dcmd_size);
747     if (cmd->iov_size < dcmd_size) {
748         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
749                                             dcmd_size);
750         return MFI_STAT_INVALID_PARAMETER;
751     }
752 
753     info.pci.vendor = cpu_to_le16(pci_class->vendor_id);
754     info.pci.device = cpu_to_le16(pci_class->device_id);
755     info.pci.subvendor = cpu_to_le16(pci_class->subsystem_vendor_id);
756     info.pci.subdevice = cpu_to_le16(pci_class->subsystem_id);
757 
758     /*
759      * For some reason the firmware supports
760      * only up to 8 device ports.
761      * Despite supporting a far larger number
762      * of devices for the physical devices.
763      * So just display the first 8 devices
764      * in the device port list, independent
765      * of how many logical devices are actually
766      * present.
767      */
768     info.host.type = MFI_INFO_HOST_PCIE;
769     info.device.type = MFI_INFO_DEV_SAS3G;
770     info.device.port_count = 8;
771     QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
772         SCSIDevice *sdev = SCSI_DEVICE(kid->child);
773         uint16_t pd_id;
774 
775         if (num_pd_disks < 8) {
776             pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
777             info.device.port_addr[num_pd_disks] =
778                 cpu_to_le64(megasas_get_sata_addr(pd_id));
779         }
780         num_pd_disks++;
781     }
782 
783     memcpy(info.product_name, base_class->product_name, 24);
784     snprintf(info.serial_number, 32, "%s", s->hba_serial);
785     snprintf(info.package_version, 0x60, "%s-QEMU", qemu_hw_version());
786     memcpy(info.image_component[0].name, "APP", 3);
787     snprintf(info.image_component[0].version, 10, "%s-QEMU",
788              base_class->product_version);
789     memcpy(info.image_component[0].build_date, "Apr  1 2014", 11);
790     memcpy(info.image_component[0].build_time, "12:34:56", 8);
791     info.image_component_count = 1;
792     if (pci_dev->has_rom) {
793         uint8_t biosver[32];
794         uint8_t *ptr;
795 
796         ptr = memory_region_get_ram_ptr(&pci_dev->rom);
797         memcpy(biosver, ptr + 0x41, 31);
798         biosver[31] = 0;
799         memcpy(info.image_component[1].name, "BIOS", 4);
800         memcpy(info.image_component[1].version, biosver,
801                strlen((const char *)biosver));
802         info.image_component_count++;
803     }
804     info.current_fw_time = cpu_to_le32(megasas_fw_time());
805     info.max_arms = 32;
806     info.max_spans = 8;
807     info.max_arrays = MEGASAS_MAX_ARRAYS;
808     info.max_lds = MFI_MAX_LD;
809     info.max_cmds = cpu_to_le16(s->fw_cmds);
810     info.max_sg_elements = cpu_to_le16(s->fw_sge);
811     info.max_request_size = cpu_to_le32(MEGASAS_MAX_SECTORS);
812     if (!megasas_is_jbod(s))
813         info.lds_present = cpu_to_le16(num_pd_disks);
814     info.pd_present = cpu_to_le16(num_pd_disks);
815     info.pd_disks_present = cpu_to_le16(num_pd_disks);
816     info.hw_present = cpu_to_le32(MFI_INFO_HW_NVRAM |
817                                    MFI_INFO_HW_MEM |
818                                    MFI_INFO_HW_FLASH);
819     info.memory_size = cpu_to_le16(512);
820     info.nvram_size = cpu_to_le16(32);
821     info.flash_size = cpu_to_le16(16);
822     info.raid_levels = cpu_to_le32(MFI_INFO_RAID_0);
823     info.adapter_ops = cpu_to_le32(MFI_INFO_AOPS_RBLD_RATE |
824                                     MFI_INFO_AOPS_SELF_DIAGNOSTIC |
825                                     MFI_INFO_AOPS_MIXED_ARRAY);
826     info.ld_ops = cpu_to_le32(MFI_INFO_LDOPS_DISK_CACHE_POLICY |
827                                MFI_INFO_LDOPS_ACCESS_POLICY |
828                                MFI_INFO_LDOPS_IO_POLICY |
829                                MFI_INFO_LDOPS_WRITE_POLICY |
830                                MFI_INFO_LDOPS_READ_POLICY);
831     info.max_strips_per_io = cpu_to_le16(s->fw_sge);
832     info.stripe_sz_ops.min = 3;
833     info.stripe_sz_ops.max = ctz32(MEGASAS_MAX_SECTORS + 1);
834     info.properties.pred_fail_poll_interval = cpu_to_le16(300);
835     info.properties.intr_throttle_cnt = cpu_to_le16(16);
836     info.properties.intr_throttle_timeout = cpu_to_le16(50);
837     info.properties.rebuild_rate = 30;
838     info.properties.patrol_read_rate = 30;
839     info.properties.bgi_rate = 30;
840     info.properties.cc_rate = 30;
841     info.properties.recon_rate = 30;
842     info.properties.cache_flush_interval = 4;
843     info.properties.spinup_drv_cnt = 2;
844     info.properties.spinup_delay = 6;
845     info.properties.ecc_bucket_size = 15;
846     info.properties.ecc_bucket_leak_rate = cpu_to_le16(1440);
847     info.properties.expose_encl_devices = 1;
848     info.properties.OnOffProperties = cpu_to_le32(MFI_CTRL_PROP_EnableJBOD);
849     info.pd_ops = cpu_to_le32(MFI_INFO_PDOPS_FORCE_ONLINE |
850                                MFI_INFO_PDOPS_FORCE_OFFLINE);
851     info.pd_mix_support = cpu_to_le32(MFI_INFO_PDMIX_SAS |
852                                        MFI_INFO_PDMIX_SATA |
853                                        MFI_INFO_PDMIX_LD);
854 
855     dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
856                  MEMTXATTRS_UNSPECIFIED);
857     cmd->iov_size -= residual;
858     return MFI_STAT_OK;
859 }
860 
megasas_mfc_get_defaults(MegasasState * s,MegasasCmd * cmd)861 static int megasas_mfc_get_defaults(MegasasState *s, MegasasCmd *cmd)
862 {
863     struct mfi_defaults info;
864     size_t dcmd_size = sizeof(struct mfi_defaults);
865     dma_addr_t residual;
866 
867     memset(&info, 0x0, dcmd_size);
868     if (cmd->iov_size < dcmd_size) {
869         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
870                                             dcmd_size);
871         return MFI_STAT_INVALID_PARAMETER;
872     }
873 
874     info.sas_addr = cpu_to_le64(s->sas_addr);
875     info.stripe_size = 3;
876     info.flush_time = 4;
877     info.background_rate = 30;
878     info.allow_mix_in_enclosure = 1;
879     info.allow_mix_in_ld = 1;
880     info.direct_pd_mapping = 1;
881     /* Enable for BIOS support */
882     info.bios_enumerate_lds = 1;
883     info.disable_ctrl_r = 1;
884     info.expose_enclosure_devices = 1;
885     info.disable_preboot_cli = 1;
886     info.cluster_disable = 1;
887 
888     dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
889                  MEMTXATTRS_UNSPECIFIED);
890     cmd->iov_size -= residual;
891     return MFI_STAT_OK;
892 }
893 
megasas_dcmd_get_bios_info(MegasasState * s,MegasasCmd * cmd)894 static int megasas_dcmd_get_bios_info(MegasasState *s, MegasasCmd *cmd)
895 {
896     struct mfi_bios_data info;
897     size_t dcmd_size = sizeof(info);
898     dma_addr_t residual;
899 
900     memset(&info, 0x0, dcmd_size);
901     if (cmd->iov_size < dcmd_size) {
902         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
903                                             dcmd_size);
904         return MFI_STAT_INVALID_PARAMETER;
905     }
906     info.continue_on_error = 1;
907     info.verbose = 1;
908     if (megasas_is_jbod(s)) {
909         info.expose_all_drives = 1;
910     }
911 
912     dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
913                  MEMTXATTRS_UNSPECIFIED);
914     cmd->iov_size -= residual;
915     return MFI_STAT_OK;
916 }
917 
megasas_dcmd_get_fw_time(MegasasState * s,MegasasCmd * cmd)918 static int megasas_dcmd_get_fw_time(MegasasState *s, MegasasCmd *cmd)
919 {
920     uint64_t fw_time;
921     size_t dcmd_size = sizeof(fw_time);
922     dma_addr_t residual;
923 
924     fw_time = cpu_to_le64(megasas_fw_time());
925 
926     dma_buf_read(&fw_time, dcmd_size, &residual, &cmd->qsg,
927                  MEMTXATTRS_UNSPECIFIED);
928     cmd->iov_size -= residual;
929     return MFI_STAT_OK;
930 }
931 
megasas_dcmd_set_fw_time(MegasasState * s,MegasasCmd * cmd)932 static int megasas_dcmd_set_fw_time(MegasasState *s, MegasasCmd *cmd)
933 {
934     uint64_t fw_time;
935 
936     /* This is a dummy; setting of firmware time is not allowed */
937     memcpy(&fw_time, cmd->frame->dcmd.mbox, sizeof(fw_time));
938 
939     trace_megasas_dcmd_set_fw_time(cmd->index, fw_time);
940     fw_time = cpu_to_le64(megasas_fw_time());
941     return MFI_STAT_OK;
942 }
943 
megasas_event_info(MegasasState * s,MegasasCmd * cmd)944 static int megasas_event_info(MegasasState *s, MegasasCmd *cmd)
945 {
946     struct mfi_evt_log_state info;
947     size_t dcmd_size = sizeof(info);
948     dma_addr_t residual;
949 
950     memset(&info, 0, dcmd_size);
951 
952     info.newest_seq_num = cpu_to_le32(s->event_count);
953     info.shutdown_seq_num = cpu_to_le32(s->shutdown_event);
954     info.boot_seq_num = cpu_to_le32(s->boot_event);
955 
956     dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
957                  MEMTXATTRS_UNSPECIFIED);
958     cmd->iov_size -= residual;
959     return MFI_STAT_OK;
960 }
961 
megasas_event_wait(MegasasState * s,MegasasCmd * cmd)962 static int megasas_event_wait(MegasasState *s, MegasasCmd *cmd)
963 {
964     union mfi_evt event;
965 
966     if (cmd->iov_size < sizeof(struct mfi_evt_detail)) {
967         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
968                                             sizeof(struct mfi_evt_detail));
969         return MFI_STAT_INVALID_PARAMETER;
970     }
971     s->event_count = cpu_to_le32(cmd->frame->dcmd.mbox[0]);
972     event.word = cpu_to_le32(cmd->frame->dcmd.mbox[4]);
973     s->event_locale = event.members.locale;
974     s->event_class = event.members.class;
975     s->event_cmd = cmd;
976     /* Decrease busy count; event frame doesn't count here */
977     s->busy--;
978     cmd->iov_size = sizeof(struct mfi_evt_detail);
979     return MFI_STAT_INVALID_STATUS;
980 }
981 
megasas_dcmd_pd_get_list(MegasasState * s,MegasasCmd * cmd)982 static int megasas_dcmd_pd_get_list(MegasasState *s, MegasasCmd *cmd)
983 {
984     struct mfi_pd_list info;
985     size_t dcmd_size = sizeof(info);
986     BusChild *kid;
987     uint32_t offset, dcmd_limit, num_pd_disks = 0, max_pd_disks;
988     dma_addr_t residual;
989 
990     memset(&info, 0, dcmd_size);
991     offset = 8;
992     dcmd_limit = offset + sizeof(struct mfi_pd_address);
993     if (cmd->iov_size < dcmd_limit) {
994         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
995                                             dcmd_limit);
996         return MFI_STAT_INVALID_PARAMETER;
997     }
998 
999     max_pd_disks = (cmd->iov_size - offset) / sizeof(struct mfi_pd_address);
1000     if (max_pd_disks > MFI_MAX_SYS_PDS) {
1001         max_pd_disks = MFI_MAX_SYS_PDS;
1002     }
1003     QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1004         SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1005         uint16_t pd_id;
1006 
1007         if (num_pd_disks >= max_pd_disks)
1008             break;
1009 
1010         pd_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1011         info.addr[num_pd_disks].device_id = cpu_to_le16(pd_id);
1012         info.addr[num_pd_disks].encl_device_id = 0xFFFF;
1013         info.addr[num_pd_disks].encl_index = 0;
1014         info.addr[num_pd_disks].slot_number = sdev->id & 0xFF;
1015         info.addr[num_pd_disks].scsi_dev_type = sdev->type;
1016         info.addr[num_pd_disks].connect_port_bitmap = 0x1;
1017         info.addr[num_pd_disks].sas_addr[0] =
1018             cpu_to_le64(megasas_get_sata_addr(pd_id));
1019         num_pd_disks++;
1020         offset += sizeof(struct mfi_pd_address);
1021     }
1022     trace_megasas_dcmd_pd_get_list(cmd->index, num_pd_disks,
1023                                    max_pd_disks, offset);
1024 
1025     info.size = cpu_to_le32(offset);
1026     info.count = cpu_to_le32(num_pd_disks);
1027 
1028     dma_buf_read(&info, offset, &residual, &cmd->qsg,
1029                  MEMTXATTRS_UNSPECIFIED);
1030     cmd->iov_size -= residual;
1031     return MFI_STAT_OK;
1032 }
1033 
megasas_dcmd_pd_list_query(MegasasState * s,MegasasCmd * cmd)1034 static int megasas_dcmd_pd_list_query(MegasasState *s, MegasasCmd *cmd)
1035 {
1036     uint16_t flags;
1037 
1038     /* mbox0 contains flags */
1039     flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1040     trace_megasas_dcmd_pd_list_query(cmd->index, flags);
1041     if (flags == MR_PD_QUERY_TYPE_ALL ||
1042         megasas_is_jbod(s)) {
1043         return megasas_dcmd_pd_get_list(s, cmd);
1044     }
1045 
1046     return MFI_STAT_OK;
1047 }
1048 
megasas_pd_get_info_submit(SCSIDevice * sdev,int lun,MegasasCmd * cmd)1049 static int megasas_pd_get_info_submit(SCSIDevice *sdev, int lun,
1050                                       MegasasCmd *cmd)
1051 {
1052     struct mfi_pd_info *info = cmd->iov_buf;
1053     size_t dcmd_size = sizeof(struct mfi_pd_info);
1054     uint64_t pd_size;
1055     uint16_t pd_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1056     uint8_t cmdbuf[6];
1057     size_t len;
1058     dma_addr_t residual;
1059 
1060     if (!cmd->iov_buf) {
1061         cmd->iov_buf = g_malloc0(dcmd_size);
1062         info = cmd->iov_buf;
1063         info->inquiry_data[0] = 0x7f; /* Force PQual 0x3, PType 0x1f */
1064         info->vpd_page83[0] = 0x7f;
1065         megasas_setup_inquiry(cmdbuf, 0, sizeof(info->inquiry_data));
1066         cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, sizeof(cmdbuf), cmd);
1067         if (!cmd->req) {
1068             trace_megasas_dcmd_req_alloc_failed(cmd->index,
1069                                                 "PD get info std inquiry");
1070             g_free(cmd->iov_buf);
1071             cmd->iov_buf = NULL;
1072             return MFI_STAT_FLASH_ALLOC_FAIL;
1073         }
1074         trace_megasas_dcmd_internal_submit(cmd->index,
1075                                            "PD get info std inquiry", lun);
1076         len = scsi_req_enqueue(cmd->req);
1077         if (len > 0) {
1078             cmd->iov_size = len;
1079             scsi_req_continue(cmd->req);
1080         }
1081         return MFI_STAT_INVALID_STATUS;
1082     } else if (info->inquiry_data[0] != 0x7f && info->vpd_page83[0] == 0x7f) {
1083         megasas_setup_inquiry(cmdbuf, 0x83, sizeof(info->vpd_page83));
1084         cmd->req = scsi_req_new(sdev, cmd->index, lun, cmdbuf, sizeof(cmdbuf), cmd);
1085         if (!cmd->req) {
1086             trace_megasas_dcmd_req_alloc_failed(cmd->index,
1087                                                 "PD get info vpd inquiry");
1088             return MFI_STAT_FLASH_ALLOC_FAIL;
1089         }
1090         trace_megasas_dcmd_internal_submit(cmd->index,
1091                                            "PD get info vpd inquiry", lun);
1092         len = scsi_req_enqueue(cmd->req);
1093         if (len > 0) {
1094             cmd->iov_size = len;
1095             scsi_req_continue(cmd->req);
1096         }
1097         return MFI_STAT_INVALID_STATUS;
1098     }
1099     /* Finished, set FW state */
1100     if ((info->inquiry_data[0] >> 5) == 0) {
1101         if (megasas_is_jbod(cmd->state)) {
1102             info->fw_state = cpu_to_le16(MFI_PD_STATE_SYSTEM);
1103         } else {
1104             info->fw_state = cpu_to_le16(MFI_PD_STATE_ONLINE);
1105         }
1106     } else {
1107         info->fw_state = cpu_to_le16(MFI_PD_STATE_OFFLINE);
1108     }
1109 
1110     info->ref.v.device_id = cpu_to_le16(pd_id);
1111     info->state.ddf.pd_type = cpu_to_le16(MFI_PD_DDF_TYPE_IN_VD|
1112                                           MFI_PD_DDF_TYPE_INTF_SAS);
1113     blk_get_geometry(sdev->conf.blk, &pd_size);
1114     info->raw_size = cpu_to_le64(pd_size);
1115     info->non_coerced_size = cpu_to_le64(pd_size);
1116     info->coerced_size = cpu_to_le64(pd_size);
1117     info->encl_device_id = 0xFFFF;
1118     info->slot_number = (sdev->id & 0xFF);
1119     info->path_info.count = 1;
1120     info->path_info.sas_addr[0] =
1121         cpu_to_le64(megasas_get_sata_addr(pd_id));
1122     info->connected_port_bitmap = 0x1;
1123     info->device_speed = 1;
1124     info->link_speed = 1;
1125     dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
1126                  MEMTXATTRS_UNSPECIFIED);
1127     cmd->iov_size -= residual;
1128     g_free(cmd->iov_buf);
1129     cmd->iov_size = dcmd_size - residual;
1130     cmd->iov_buf = NULL;
1131     return MFI_STAT_OK;
1132 }
1133 
megasas_dcmd_pd_get_info(MegasasState * s,MegasasCmd * cmd)1134 static int megasas_dcmd_pd_get_info(MegasasState *s, MegasasCmd *cmd)
1135 {
1136     size_t dcmd_size = sizeof(struct mfi_pd_info);
1137     uint16_t pd_id;
1138     uint8_t target_id, lun_id;
1139     SCSIDevice *sdev = NULL;
1140     int retval = MFI_STAT_DEVICE_NOT_FOUND;
1141 
1142     if (cmd->iov_size < dcmd_size) {
1143         return MFI_STAT_INVALID_PARAMETER;
1144     }
1145 
1146     /* mbox0 has the ID */
1147     pd_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1148     target_id = (pd_id >> 8) & 0xFF;
1149     lun_id = pd_id & 0xFF;
1150     sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1151     trace_megasas_dcmd_pd_get_info(cmd->index, pd_id);
1152 
1153     if (sdev) {
1154         /* Submit inquiry */
1155         retval = megasas_pd_get_info_submit(sdev, pd_id, cmd);
1156     }
1157 
1158     return retval;
1159 }
1160 
megasas_dcmd_ld_get_list(MegasasState * s,MegasasCmd * cmd)1161 static int megasas_dcmd_ld_get_list(MegasasState *s, MegasasCmd *cmd)
1162 {
1163     struct mfi_ld_list info;
1164     size_t dcmd_size = sizeof(info);
1165     dma_addr_t residual;
1166     uint32_t num_ld_disks = 0, max_ld_disks;
1167     uint64_t ld_size;
1168     BusChild *kid;
1169 
1170     memset(&info, 0, dcmd_size);
1171     if (cmd->iov_size > dcmd_size) {
1172         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1173                                             dcmd_size);
1174         return MFI_STAT_INVALID_PARAMETER;
1175     }
1176 
1177     max_ld_disks = (cmd->iov_size - 8) / 16;
1178     if (megasas_is_jbod(s)) {
1179         max_ld_disks = 0;
1180     }
1181     if (max_ld_disks > MFI_MAX_LD) {
1182         max_ld_disks = MFI_MAX_LD;
1183     }
1184     QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1185         SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1186 
1187         if (num_ld_disks >= max_ld_disks) {
1188             break;
1189         }
1190         /* Logical device size is in blocks */
1191         blk_get_geometry(sdev->conf.blk, &ld_size);
1192         info.ld_list[num_ld_disks].ld.v.target_id = sdev->id;
1193         info.ld_list[num_ld_disks].state = MFI_LD_STATE_OPTIMAL;
1194         info.ld_list[num_ld_disks].size = cpu_to_le64(ld_size);
1195         num_ld_disks++;
1196     }
1197     info.ld_count = cpu_to_le32(num_ld_disks);
1198     trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1199 
1200     dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1201                  MEMTXATTRS_UNSPECIFIED);
1202     cmd->iov_size = dcmd_size - residual;
1203     return MFI_STAT_OK;
1204 }
1205 
megasas_dcmd_ld_list_query(MegasasState * s,MegasasCmd * cmd)1206 static int megasas_dcmd_ld_list_query(MegasasState *s, MegasasCmd *cmd)
1207 {
1208     uint16_t flags;
1209     struct mfi_ld_targetid_list info;
1210     size_t dcmd_size = sizeof(info);
1211     dma_addr_t residual;
1212     uint32_t num_ld_disks = 0, max_ld_disks = s->fw_luns;
1213     BusChild *kid;
1214 
1215     /* mbox0 contains flags */
1216     flags = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1217     trace_megasas_dcmd_ld_list_query(cmd->index, flags);
1218     if (flags != MR_LD_QUERY_TYPE_ALL &&
1219         flags != MR_LD_QUERY_TYPE_EXPOSED_TO_HOST) {
1220         max_ld_disks = 0;
1221     }
1222 
1223     memset(&info, 0, dcmd_size);
1224     if (cmd->iov_size < 12) {
1225         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1226                                             dcmd_size);
1227         return MFI_STAT_INVALID_PARAMETER;
1228     }
1229     dcmd_size = sizeof(uint32_t) * 2 + 3;
1230     max_ld_disks = cmd->iov_size - dcmd_size;
1231     if (megasas_is_jbod(s)) {
1232         max_ld_disks = 0;
1233     }
1234     if (max_ld_disks > MFI_MAX_LD) {
1235         max_ld_disks = MFI_MAX_LD;
1236     }
1237     QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1238         SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1239 
1240         if (num_ld_disks >= max_ld_disks) {
1241             break;
1242         }
1243         info.targetid[num_ld_disks] = sdev->lun;
1244         num_ld_disks++;
1245         dcmd_size++;
1246     }
1247     info.ld_count = cpu_to_le32(num_ld_disks);
1248     info.size = dcmd_size;
1249     trace_megasas_dcmd_ld_get_list(cmd->index, num_ld_disks, max_ld_disks);
1250 
1251     dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1252                  MEMTXATTRS_UNSPECIFIED);
1253     cmd->iov_size = dcmd_size - residual;
1254     return MFI_STAT_OK;
1255 }
1256 
megasas_ld_get_info_submit(SCSIDevice * sdev,int lun,MegasasCmd * cmd)1257 static int megasas_ld_get_info_submit(SCSIDevice *sdev, int lun,
1258                                       MegasasCmd *cmd)
1259 {
1260     struct mfi_ld_info *info = cmd->iov_buf;
1261     size_t dcmd_size = sizeof(struct mfi_ld_info);
1262     uint8_t cdb[6];
1263     ssize_t len;
1264     dma_addr_t residual;
1265     uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (lun & 0xFF);
1266     uint64_t ld_size;
1267 
1268     if (!cmd->iov_buf) {
1269         cmd->iov_buf = g_malloc0(dcmd_size);
1270         info = cmd->iov_buf;
1271         megasas_setup_inquiry(cdb, 0x83, sizeof(info->vpd_page83));
1272         cmd->req = scsi_req_new(sdev, cmd->index, lun, cdb, sizeof(cdb), cmd);
1273         if (!cmd->req) {
1274             trace_megasas_dcmd_req_alloc_failed(cmd->index,
1275                                                 "LD get info vpd inquiry");
1276             g_free(cmd->iov_buf);
1277             cmd->iov_buf = NULL;
1278             return MFI_STAT_FLASH_ALLOC_FAIL;
1279         }
1280         trace_megasas_dcmd_internal_submit(cmd->index,
1281                                            "LD get info vpd inquiry", lun);
1282         len = scsi_req_enqueue(cmd->req);
1283         if (len > 0) {
1284             cmd->iov_size = len;
1285             scsi_req_continue(cmd->req);
1286         }
1287         return MFI_STAT_INVALID_STATUS;
1288     }
1289 
1290     info->ld_config.params.state = MFI_LD_STATE_OPTIMAL;
1291     info->ld_config.properties.ld.v.target_id = lun;
1292     info->ld_config.params.stripe_size = 3;
1293     info->ld_config.params.num_drives = 1;
1294     info->ld_config.params.is_consistent = 1;
1295     /* Logical device size is in blocks */
1296     blk_get_geometry(sdev->conf.blk, &ld_size);
1297     info->size = cpu_to_le64(ld_size);
1298     memset(info->ld_config.span, 0, sizeof(info->ld_config.span));
1299     info->ld_config.span[0].start_block = 0;
1300     info->ld_config.span[0].num_blocks = info->size;
1301     info->ld_config.span[0].array_ref = cpu_to_le16(sdev_id);
1302 
1303     dma_buf_read(cmd->iov_buf, dcmd_size, &residual, &cmd->qsg,
1304                  MEMTXATTRS_UNSPECIFIED);
1305     g_free(cmd->iov_buf);
1306     cmd->iov_size = dcmd_size - residual;
1307     cmd->iov_buf = NULL;
1308     return MFI_STAT_OK;
1309 }
1310 
megasas_dcmd_ld_get_info(MegasasState * s,MegasasCmd * cmd)1311 static int megasas_dcmd_ld_get_info(MegasasState *s, MegasasCmd *cmd)
1312 {
1313     struct mfi_ld_info info;
1314     size_t dcmd_size = sizeof(info);
1315     uint16_t ld_id;
1316     uint32_t max_ld_disks = s->fw_luns;
1317     SCSIDevice *sdev = NULL;
1318     int retval = MFI_STAT_DEVICE_NOT_FOUND;
1319 
1320     if (cmd->iov_size < dcmd_size) {
1321         return MFI_STAT_INVALID_PARAMETER;
1322     }
1323 
1324     /* mbox0 has the ID */
1325     ld_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1326     trace_megasas_dcmd_ld_get_info(cmd->index, ld_id);
1327 
1328     if (megasas_is_jbod(s)) {
1329         return MFI_STAT_DEVICE_NOT_FOUND;
1330     }
1331 
1332     if (ld_id < max_ld_disks) {
1333         sdev = scsi_device_find(&s->bus, 0, ld_id, 0);
1334     }
1335 
1336     if (sdev) {
1337         retval = megasas_ld_get_info_submit(sdev, ld_id, cmd);
1338     }
1339 
1340     return retval;
1341 }
1342 
megasas_dcmd_cfg_read(MegasasState * s,MegasasCmd * cmd)1343 static int megasas_dcmd_cfg_read(MegasasState *s, MegasasCmd *cmd)
1344 {
1345     uint8_t data[4096] = { 0 };
1346     struct mfi_config_data *info;
1347     int num_pd_disks = 0, array_offset, ld_offset;
1348     BusChild *kid;
1349     dma_addr_t residual;
1350 
1351     if (cmd->iov_size > 4096) {
1352         return MFI_STAT_INVALID_PARAMETER;
1353     }
1354 
1355     QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1356         num_pd_disks++;
1357     }
1358     info = (struct mfi_config_data *)&data;
1359     /*
1360      * Array mapping:
1361      * - One array per SCSI device
1362      * - One logical drive per SCSI device
1363      *   spanning the entire device
1364      */
1365     info->array_count = num_pd_disks;
1366     info->array_size = sizeof(struct mfi_array) * num_pd_disks;
1367     info->log_drv_count = num_pd_disks;
1368     info->log_drv_size = sizeof(struct mfi_ld_config) * num_pd_disks;
1369     info->spares_count = 0;
1370     info->spares_size = sizeof(struct mfi_spare);
1371     info->size = sizeof(struct mfi_config_data) + info->array_size +
1372         info->log_drv_size;
1373     if (info->size > 4096) {
1374         return MFI_STAT_INVALID_PARAMETER;
1375     }
1376 
1377     array_offset = sizeof(struct mfi_config_data);
1378     ld_offset = array_offset + sizeof(struct mfi_array) * num_pd_disks;
1379 
1380     QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
1381         SCSIDevice *sdev = SCSI_DEVICE(kid->child);
1382         uint16_t sdev_id = ((sdev->id & 0xFF) << 8) | (sdev->lun & 0xFF);
1383         struct mfi_array *array;
1384         struct mfi_ld_config *ld;
1385         uint64_t pd_size;
1386         int i;
1387 
1388         array = (struct mfi_array *)(data + array_offset);
1389         blk_get_geometry(sdev->conf.blk, &pd_size);
1390         array->size = cpu_to_le64(pd_size);
1391         array->num_drives = 1;
1392         array->array_ref = cpu_to_le16(sdev_id);
1393         array->pd[0].ref.v.device_id = cpu_to_le16(sdev_id);
1394         array->pd[0].ref.v.seq_num = 0;
1395         array->pd[0].fw_state = MFI_PD_STATE_ONLINE;
1396         array->pd[0].encl.pd = 0xFF;
1397         array->pd[0].encl.slot = (sdev->id & 0xFF);
1398         for (i = 1; i < MFI_MAX_ROW_SIZE; i++) {
1399             array->pd[i].ref.v.device_id = 0xFFFF;
1400             array->pd[i].ref.v.seq_num = 0;
1401             array->pd[i].fw_state = MFI_PD_STATE_UNCONFIGURED_GOOD;
1402             array->pd[i].encl.pd = 0xFF;
1403             array->pd[i].encl.slot = 0xFF;
1404         }
1405         array_offset += sizeof(struct mfi_array);
1406         ld = (struct mfi_ld_config *)(data + ld_offset);
1407         memset(ld, 0, sizeof(struct mfi_ld_config));
1408         ld->properties.ld.v.target_id = sdev->id;
1409         ld->properties.default_cache_policy = MR_LD_CACHE_READ_AHEAD |
1410             MR_LD_CACHE_READ_ADAPTIVE;
1411         ld->properties.current_cache_policy = MR_LD_CACHE_READ_AHEAD |
1412             MR_LD_CACHE_READ_ADAPTIVE;
1413         ld->params.state = MFI_LD_STATE_OPTIMAL;
1414         ld->params.stripe_size = 3;
1415         ld->params.num_drives = 1;
1416         ld->params.span_depth = 1;
1417         ld->params.is_consistent = 1;
1418         ld->span[0].start_block = 0;
1419         ld->span[0].num_blocks = cpu_to_le64(pd_size);
1420         ld->span[0].array_ref = cpu_to_le16(sdev_id);
1421         ld_offset += sizeof(struct mfi_ld_config);
1422     }
1423 
1424     dma_buf_read(data, info->size, &residual, &cmd->qsg,
1425                  MEMTXATTRS_UNSPECIFIED);
1426     cmd->iov_size -= residual;
1427     return MFI_STAT_OK;
1428 }
1429 
megasas_dcmd_get_properties(MegasasState * s,MegasasCmd * cmd)1430 static int megasas_dcmd_get_properties(MegasasState *s, MegasasCmd *cmd)
1431 {
1432     struct mfi_ctrl_props info;
1433     size_t dcmd_size = sizeof(info);
1434     dma_addr_t residual;
1435 
1436     memset(&info, 0x0, dcmd_size);
1437     if (cmd->iov_size < dcmd_size) {
1438         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1439                                             dcmd_size);
1440         return MFI_STAT_INVALID_PARAMETER;
1441     }
1442     info.pred_fail_poll_interval = cpu_to_le16(300);
1443     info.intr_throttle_cnt = cpu_to_le16(16);
1444     info.intr_throttle_timeout = cpu_to_le16(50);
1445     info.rebuild_rate = 30;
1446     info.patrol_read_rate = 30;
1447     info.bgi_rate = 30;
1448     info.cc_rate = 30;
1449     info.recon_rate = 30;
1450     info.cache_flush_interval = 4;
1451     info.spinup_drv_cnt = 2;
1452     info.spinup_delay = 6;
1453     info.ecc_bucket_size = 15;
1454     info.ecc_bucket_leak_rate = cpu_to_le16(1440);
1455     info.expose_encl_devices = 1;
1456 
1457     dma_buf_read(&info, dcmd_size, &residual, &cmd->qsg,
1458                  MEMTXATTRS_UNSPECIFIED);
1459     cmd->iov_size -= residual;
1460     return MFI_STAT_OK;
1461 }
1462 
megasas_cache_flush(MegasasState * s,MegasasCmd * cmd)1463 static int megasas_cache_flush(MegasasState *s, MegasasCmd *cmd)
1464 {
1465     blk_drain_all();
1466     return MFI_STAT_OK;
1467 }
1468 
megasas_ctrl_shutdown(MegasasState * s,MegasasCmd * cmd)1469 static int megasas_ctrl_shutdown(MegasasState *s, MegasasCmd *cmd)
1470 {
1471     s->fw_state = MFI_FWSTATE_READY;
1472     return MFI_STAT_OK;
1473 }
1474 
1475 /* Some implementations use CLUSTER RESET LD to simulate a device reset */
megasas_cluster_reset_ld(MegasasState * s,MegasasCmd * cmd)1476 static int megasas_cluster_reset_ld(MegasasState *s, MegasasCmd *cmd)
1477 {
1478     uint16_t target_id;
1479     int i;
1480 
1481     /* mbox0 contains the device index */
1482     target_id = le16_to_cpu(cmd->frame->dcmd.mbox[0]);
1483     trace_megasas_dcmd_reset_ld(cmd->index, target_id);
1484     for (i = 0; i < s->fw_cmds; i++) {
1485         MegasasCmd *tmp_cmd = &s->frames[i];
1486         if (tmp_cmd->req && tmp_cmd->req->dev->id == target_id) {
1487             SCSIDevice *d = tmp_cmd->req->dev;
1488             device_cold_reset(&d->qdev);
1489         }
1490     }
1491     return MFI_STAT_OK;
1492 }
1493 
megasas_dcmd_set_properties(MegasasState * s,MegasasCmd * cmd)1494 static int megasas_dcmd_set_properties(MegasasState *s, MegasasCmd *cmd)
1495 {
1496     struct mfi_ctrl_props info;
1497     size_t dcmd_size = sizeof(info);
1498 
1499     if (cmd->iov_size < dcmd_size) {
1500         trace_megasas_dcmd_invalid_xfer_len(cmd->index, cmd->iov_size,
1501                                             dcmd_size);
1502         return MFI_STAT_INVALID_PARAMETER;
1503     }
1504     dma_buf_write(&info, dcmd_size, NULL, &cmd->qsg, MEMTXATTRS_UNSPECIFIED);
1505     trace_megasas_dcmd_unsupported(cmd->index, cmd->iov_size);
1506     return MFI_STAT_OK;
1507 }
1508 
megasas_dcmd_dummy(MegasasState * s,MegasasCmd * cmd)1509 static int megasas_dcmd_dummy(MegasasState *s, MegasasCmd *cmd)
1510 {
1511     trace_megasas_dcmd_dummy(cmd->index, cmd->iov_size);
1512     return MFI_STAT_OK;
1513 }
1514 
1515 static const struct dcmd_cmd_tbl_t {
1516     int opcode;
1517     const char *desc;
1518     int (*func)(MegasasState *s, MegasasCmd *cmd);
1519 } dcmd_cmd_tbl[] = {
1520     { MFI_DCMD_CTRL_MFI_HOST_MEM_ALLOC, "CTRL_HOST_MEM_ALLOC",
1521       megasas_dcmd_dummy },
1522     { MFI_DCMD_CTRL_GET_INFO, "CTRL_GET_INFO",
1523       megasas_ctrl_get_info },
1524     { MFI_DCMD_CTRL_GET_PROPERTIES, "CTRL_GET_PROPERTIES",
1525       megasas_dcmd_get_properties },
1526     { MFI_DCMD_CTRL_SET_PROPERTIES, "CTRL_SET_PROPERTIES",
1527       megasas_dcmd_set_properties },
1528     { MFI_DCMD_CTRL_ALARM_GET, "CTRL_ALARM_GET",
1529       megasas_dcmd_dummy },
1530     { MFI_DCMD_CTRL_ALARM_ENABLE, "CTRL_ALARM_ENABLE",
1531       megasas_dcmd_dummy },
1532     { MFI_DCMD_CTRL_ALARM_DISABLE, "CTRL_ALARM_DISABLE",
1533       megasas_dcmd_dummy },
1534     { MFI_DCMD_CTRL_ALARM_SILENCE, "CTRL_ALARM_SILENCE",
1535       megasas_dcmd_dummy },
1536     { MFI_DCMD_CTRL_ALARM_TEST, "CTRL_ALARM_TEST",
1537       megasas_dcmd_dummy },
1538     { MFI_DCMD_CTRL_EVENT_GETINFO, "CTRL_EVENT_GETINFO",
1539       megasas_event_info },
1540     { MFI_DCMD_CTRL_EVENT_GET, "CTRL_EVENT_GET",
1541       megasas_dcmd_dummy },
1542     { MFI_DCMD_CTRL_EVENT_WAIT, "CTRL_EVENT_WAIT",
1543       megasas_event_wait },
1544     { MFI_DCMD_CTRL_SHUTDOWN, "CTRL_SHUTDOWN",
1545       megasas_ctrl_shutdown },
1546     { MFI_DCMD_HIBERNATE_STANDBY, "CTRL_STANDBY",
1547       megasas_dcmd_dummy },
1548     { MFI_DCMD_CTRL_GET_TIME, "CTRL_GET_TIME",
1549       megasas_dcmd_get_fw_time },
1550     { MFI_DCMD_CTRL_SET_TIME, "CTRL_SET_TIME",
1551       megasas_dcmd_set_fw_time },
1552     { MFI_DCMD_CTRL_BIOS_DATA_GET, "CTRL_BIOS_DATA_GET",
1553       megasas_dcmd_get_bios_info },
1554     { MFI_DCMD_CTRL_FACTORY_DEFAULTS, "CTRL_FACTORY_DEFAULTS",
1555       megasas_dcmd_dummy },
1556     { MFI_DCMD_CTRL_MFC_DEFAULTS_GET, "CTRL_MFC_DEFAULTS_GET",
1557       megasas_mfc_get_defaults },
1558     { MFI_DCMD_CTRL_MFC_DEFAULTS_SET, "CTRL_MFC_DEFAULTS_SET",
1559       megasas_dcmd_dummy },
1560     { MFI_DCMD_CTRL_CACHE_FLUSH, "CTRL_CACHE_FLUSH",
1561       megasas_cache_flush },
1562     { MFI_DCMD_PD_GET_LIST, "PD_GET_LIST",
1563       megasas_dcmd_pd_get_list },
1564     { MFI_DCMD_PD_LIST_QUERY, "PD_LIST_QUERY",
1565       megasas_dcmd_pd_list_query },
1566     { MFI_DCMD_PD_GET_INFO, "PD_GET_INFO",
1567       megasas_dcmd_pd_get_info },
1568     { MFI_DCMD_PD_STATE_SET, "PD_STATE_SET",
1569       megasas_dcmd_dummy },
1570     { MFI_DCMD_PD_REBUILD, "PD_REBUILD",
1571       megasas_dcmd_dummy },
1572     { MFI_DCMD_PD_BLINK, "PD_BLINK",
1573       megasas_dcmd_dummy },
1574     { MFI_DCMD_PD_UNBLINK, "PD_UNBLINK",
1575       megasas_dcmd_dummy },
1576     { MFI_DCMD_LD_GET_LIST, "LD_GET_LIST",
1577       megasas_dcmd_ld_get_list},
1578     { MFI_DCMD_LD_LIST_QUERY, "LD_LIST_QUERY",
1579       megasas_dcmd_ld_list_query },
1580     { MFI_DCMD_LD_GET_INFO, "LD_GET_INFO",
1581       megasas_dcmd_ld_get_info },
1582     { MFI_DCMD_LD_GET_PROP, "LD_GET_PROP",
1583       megasas_dcmd_dummy },
1584     { MFI_DCMD_LD_SET_PROP, "LD_SET_PROP",
1585       megasas_dcmd_dummy },
1586     { MFI_DCMD_LD_DELETE, "LD_DELETE",
1587       megasas_dcmd_dummy },
1588     { MFI_DCMD_CFG_READ, "CFG_READ",
1589       megasas_dcmd_cfg_read },
1590     { MFI_DCMD_CFG_ADD, "CFG_ADD",
1591       megasas_dcmd_dummy },
1592     { MFI_DCMD_CFG_CLEAR, "CFG_CLEAR",
1593       megasas_dcmd_dummy },
1594     { MFI_DCMD_CFG_FOREIGN_READ, "CFG_FOREIGN_READ",
1595       megasas_dcmd_dummy },
1596     { MFI_DCMD_CFG_FOREIGN_IMPORT, "CFG_FOREIGN_IMPORT",
1597       megasas_dcmd_dummy },
1598     { MFI_DCMD_BBU_STATUS, "BBU_STATUS",
1599       megasas_dcmd_dummy },
1600     { MFI_DCMD_BBU_CAPACITY_INFO, "BBU_CAPACITY_INFO",
1601       megasas_dcmd_dummy },
1602     { MFI_DCMD_BBU_DESIGN_INFO, "BBU_DESIGN_INFO",
1603       megasas_dcmd_dummy },
1604     { MFI_DCMD_BBU_PROP_GET, "BBU_PROP_GET",
1605       megasas_dcmd_dummy },
1606     { MFI_DCMD_CLUSTER, "CLUSTER",
1607       megasas_dcmd_dummy },
1608     { MFI_DCMD_CLUSTER_RESET_ALL, "CLUSTER_RESET_ALL",
1609       megasas_dcmd_dummy },
1610     { MFI_DCMD_CLUSTER_RESET_LD, "CLUSTER_RESET_LD",
1611       megasas_cluster_reset_ld },
1612     { -1, NULL, NULL }
1613 };
1614 
megasas_handle_dcmd(MegasasState * s,MegasasCmd * cmd)1615 static int megasas_handle_dcmd(MegasasState *s, MegasasCmd *cmd)
1616 {
1617     int retval = 0;
1618     size_t len;
1619     const struct dcmd_cmd_tbl_t *cmdptr = dcmd_cmd_tbl;
1620 
1621     cmd->dcmd_opcode = le32_to_cpu(cmd->frame->dcmd.opcode);
1622     trace_megasas_handle_dcmd(cmd->index, cmd->dcmd_opcode);
1623     if (megasas_map_dcmd(s, cmd) < 0) {
1624         return MFI_STAT_MEMORY_NOT_AVAILABLE;
1625     }
1626     while (cmdptr->opcode != -1 && cmdptr->opcode != cmd->dcmd_opcode) {
1627         cmdptr++;
1628     }
1629     len = cmd->iov_size;
1630     if (cmdptr->opcode == -1) {
1631         trace_megasas_dcmd_unhandled(cmd->index, cmd->dcmd_opcode, len);
1632         retval = megasas_dcmd_dummy(s, cmd);
1633     } else {
1634         trace_megasas_dcmd_enter(cmd->index, cmdptr->desc, len);
1635         retval = cmdptr->func(s, cmd);
1636     }
1637     if (retval != MFI_STAT_INVALID_STATUS) {
1638         megasas_finish_dcmd(cmd, len);
1639     }
1640     return retval;
1641 }
1642 
megasas_finish_internal_dcmd(MegasasCmd * cmd,SCSIRequest * req,dma_addr_t residual)1643 static int megasas_finish_internal_dcmd(MegasasCmd *cmd,
1644                                         SCSIRequest *req, dma_addr_t residual)
1645 {
1646     int retval = MFI_STAT_OK;
1647     int lun = req->lun;
1648 
1649     trace_megasas_dcmd_internal_finish(cmd->index, cmd->dcmd_opcode, lun);
1650     cmd->iov_size -= residual;
1651     switch (cmd->dcmd_opcode) {
1652     case MFI_DCMD_PD_GET_INFO:
1653         retval = megasas_pd_get_info_submit(req->dev, lun, cmd);
1654         break;
1655     case MFI_DCMD_LD_GET_INFO:
1656         retval = megasas_ld_get_info_submit(req->dev, lun, cmd);
1657         break;
1658     default:
1659         trace_megasas_dcmd_internal_invalid(cmd->index, cmd->dcmd_opcode);
1660         retval = MFI_STAT_INVALID_DCMD;
1661         break;
1662     }
1663     if (retval != MFI_STAT_INVALID_STATUS) {
1664         megasas_finish_dcmd(cmd, cmd->iov_size);
1665     }
1666     return retval;
1667 }
1668 
megasas_enqueue_req(MegasasCmd * cmd,bool is_write)1669 static int megasas_enqueue_req(MegasasCmd *cmd, bool is_write)
1670 {
1671     int len;
1672 
1673     len = scsi_req_enqueue(cmd->req);
1674     if (len < 0) {
1675         len = -len;
1676     }
1677     if (len > 0) {
1678         if (len > cmd->iov_size) {
1679             if (is_write) {
1680                 trace_megasas_iov_write_overflow(cmd->index, len,
1681                                                  cmd->iov_size);
1682             } else {
1683                 trace_megasas_iov_read_overflow(cmd->index, len,
1684                                                 cmd->iov_size);
1685             }
1686         }
1687         if (len < cmd->iov_size) {
1688             if (is_write) {
1689                 trace_megasas_iov_write_underflow(cmd->index, len,
1690                                                   cmd->iov_size);
1691             } else {
1692                 trace_megasas_iov_read_underflow(cmd->index, len,
1693                                                  cmd->iov_size);
1694             }
1695             cmd->iov_size = len;
1696         }
1697         scsi_req_continue(cmd->req);
1698     }
1699     return len;
1700 }
1701 
megasas_handle_scsi(MegasasState * s,MegasasCmd * cmd,int frame_cmd)1702 static int megasas_handle_scsi(MegasasState *s, MegasasCmd *cmd,
1703                                int frame_cmd)
1704 {
1705     uint8_t *cdb;
1706     int target_id, lun_id, cdb_len;
1707     bool is_write;
1708     struct SCSIDevice *sdev = NULL;
1709     bool is_logical = (frame_cmd == MFI_CMD_LD_SCSI_IO);
1710 
1711     cdb = cmd->frame->pass.cdb;
1712     target_id = cmd->frame->header.target_id;
1713     lun_id = cmd->frame->header.lun_id;
1714     cdb_len = cmd->frame->header.cdb_len;
1715 
1716     if (is_logical) {
1717         if (target_id >= MFI_MAX_LD || lun_id != 0) {
1718             trace_megasas_scsi_target_not_present(
1719                 mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
1720             return MFI_STAT_DEVICE_NOT_FOUND;
1721         }
1722     }
1723     sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1724 
1725     cmd->iov_size = le32_to_cpu(cmd->frame->header.data_len);
1726     trace_megasas_handle_scsi(mfi_frame_desc(frame_cmd), is_logical,
1727                               target_id, lun_id, sdev, cmd->iov_size);
1728 
1729     if (!sdev || (megasas_is_jbod(s) && is_logical)) {
1730         trace_megasas_scsi_target_not_present(
1731             mfi_frame_desc(frame_cmd), is_logical, target_id, lun_id);
1732         return MFI_STAT_DEVICE_NOT_FOUND;
1733     }
1734 
1735     if (cdb_len > 16) {
1736         trace_megasas_scsi_invalid_cdb_len(
1737                 mfi_frame_desc(frame_cmd), is_logical,
1738                 target_id, lun_id, cdb_len);
1739         megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1740         cmd->frame->header.scsi_status = CHECK_CONDITION;
1741         s->event_count++;
1742         return MFI_STAT_SCSI_DONE_WITH_ERROR;
1743     }
1744 
1745     if (megasas_map_sgl(s, cmd, &cmd->frame->pass.sgl)) {
1746         megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1747         cmd->frame->header.scsi_status = CHECK_CONDITION;
1748         s->event_count++;
1749         return MFI_STAT_SCSI_DONE_WITH_ERROR;
1750     }
1751 
1752     cmd->req = scsi_req_new(sdev, cmd->index, lun_id, cdb, cdb_len, cmd);
1753     if (!cmd->req) {
1754         trace_megasas_scsi_req_alloc_failed(
1755                 mfi_frame_desc(frame_cmd), target_id, lun_id);
1756         megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1757         cmd->frame->header.scsi_status = BUSY;
1758         s->event_count++;
1759         return MFI_STAT_SCSI_DONE_WITH_ERROR;
1760     }
1761 
1762     is_write = (cmd->req->cmd.mode == SCSI_XFER_TO_DEV);
1763     if (cmd->iov_size) {
1764         if (is_write) {
1765             trace_megasas_scsi_write_start(cmd->index, cmd->iov_size);
1766         } else {
1767             trace_megasas_scsi_read_start(cmd->index, cmd->iov_size);
1768         }
1769     } else {
1770         trace_megasas_scsi_nodata(cmd->index);
1771     }
1772     megasas_enqueue_req(cmd, is_write);
1773     return MFI_STAT_INVALID_STATUS;
1774 }
1775 
megasas_handle_io(MegasasState * s,MegasasCmd * cmd,int frame_cmd)1776 static int megasas_handle_io(MegasasState *s, MegasasCmd *cmd, int frame_cmd)
1777 {
1778     uint32_t lba_count, lba_start_hi, lba_start_lo;
1779     uint64_t lba_start;
1780     bool is_write = (frame_cmd == MFI_CMD_LD_WRITE);
1781     uint8_t cdb[16];
1782     int len;
1783     struct SCSIDevice *sdev = NULL;
1784     int target_id, lun_id, cdb_len;
1785 
1786     lba_count = le32_to_cpu(cmd->frame->io.header.data_len);
1787     lba_start_lo = le32_to_cpu(cmd->frame->io.lba_lo);
1788     lba_start_hi = le32_to_cpu(cmd->frame->io.lba_hi);
1789     lba_start = ((uint64_t)lba_start_hi << 32) | lba_start_lo;
1790 
1791     target_id = cmd->frame->header.target_id;
1792     lun_id = cmd->frame->header.lun_id;
1793     cdb_len = cmd->frame->header.cdb_len;
1794 
1795     if (target_id < MFI_MAX_LD && lun_id == 0) {
1796         sdev = scsi_device_find(&s->bus, 0, target_id, lun_id);
1797     }
1798 
1799     trace_megasas_handle_io(cmd->index,
1800                             mfi_frame_desc(frame_cmd), target_id, lun_id,
1801                             (unsigned long)lba_start, (unsigned long)lba_count);
1802     if (!sdev) {
1803         trace_megasas_io_target_not_present(cmd->index,
1804             mfi_frame_desc(frame_cmd), target_id, lun_id);
1805         return MFI_STAT_DEVICE_NOT_FOUND;
1806     }
1807 
1808     if (cdb_len > 16) {
1809         trace_megasas_scsi_invalid_cdb_len(
1810             mfi_frame_desc(frame_cmd), 1, target_id, lun_id, cdb_len);
1811         megasas_write_sense(cmd, SENSE_CODE(INVALID_OPCODE));
1812         cmd->frame->header.scsi_status = CHECK_CONDITION;
1813         s->event_count++;
1814         return MFI_STAT_SCSI_DONE_WITH_ERROR;
1815     }
1816 
1817     cmd->iov_size = lba_count * sdev->blocksize;
1818     if (megasas_map_sgl(s, cmd, &cmd->frame->io.sgl)) {
1819         megasas_write_sense(cmd, SENSE_CODE(TARGET_FAILURE));
1820         cmd->frame->header.scsi_status = CHECK_CONDITION;
1821         s->event_count++;
1822         return MFI_STAT_SCSI_DONE_WITH_ERROR;
1823     }
1824 
1825     megasas_encode_lba(cdb, lba_start, lba_count, is_write);
1826     cmd->req = scsi_req_new(sdev, cmd->index,
1827                             lun_id, cdb, cdb_len, cmd);
1828     if (!cmd->req) {
1829         trace_megasas_scsi_req_alloc_failed(
1830             mfi_frame_desc(frame_cmd), target_id, lun_id);
1831         megasas_write_sense(cmd, SENSE_CODE(NO_SENSE));
1832         cmd->frame->header.scsi_status = BUSY;
1833         s->event_count++;
1834         return MFI_STAT_SCSI_DONE_WITH_ERROR;
1835     }
1836     len = megasas_enqueue_req(cmd, is_write);
1837     if (len > 0) {
1838         if (is_write) {
1839             trace_megasas_io_write_start(cmd->index, lba_start, lba_count, len);
1840         } else {
1841             trace_megasas_io_read_start(cmd->index, lba_start, lba_count, len);
1842         }
1843     }
1844     return MFI_STAT_INVALID_STATUS;
1845 }
1846 
megasas_get_sg_list(SCSIRequest * req)1847 static QEMUSGList *megasas_get_sg_list(SCSIRequest *req)
1848 {
1849     MegasasCmd *cmd = req->hba_private;
1850 
1851     if (cmd->dcmd_opcode != -1) {
1852         return NULL;
1853     } else {
1854         return &cmd->qsg;
1855     }
1856 }
1857 
megasas_xfer_complete(SCSIRequest * req,uint32_t len)1858 static void megasas_xfer_complete(SCSIRequest *req, uint32_t len)
1859 {
1860     MegasasCmd *cmd = req->hba_private;
1861     uint8_t *buf;
1862 
1863     trace_megasas_io_complete(cmd->index, len);
1864 
1865     if (cmd->dcmd_opcode != -1) {
1866         scsi_req_continue(req);
1867         return;
1868     }
1869 
1870     buf = scsi_req_get_buf(req);
1871     if (cmd->dcmd_opcode == MFI_DCMD_PD_GET_INFO && cmd->iov_buf) {
1872         struct mfi_pd_info *info = cmd->iov_buf;
1873 
1874         if (info->inquiry_data[0] == 0x7f) {
1875             memset(info->inquiry_data, 0, sizeof(info->inquiry_data));
1876             memcpy(info->inquiry_data, buf, len);
1877         } else if (info->vpd_page83[0] == 0x7f) {
1878             memset(info->vpd_page83, 0, sizeof(info->vpd_page83));
1879             memcpy(info->vpd_page83, buf, len);
1880         }
1881         scsi_req_continue(req);
1882     } else if (cmd->dcmd_opcode == MFI_DCMD_LD_GET_INFO) {
1883         struct mfi_ld_info *info = cmd->iov_buf;
1884 
1885         if (cmd->iov_buf) {
1886             memcpy(info->vpd_page83, buf, sizeof(info->vpd_page83));
1887             scsi_req_continue(req);
1888         }
1889     }
1890 }
1891 
megasas_command_complete(SCSIRequest * req,size_t residual)1892 static void megasas_command_complete(SCSIRequest *req, size_t residual)
1893 {
1894     MegasasCmd *cmd = req->hba_private;
1895     uint8_t cmd_status = MFI_STAT_OK;
1896 
1897     trace_megasas_command_complete(cmd->index, req->status, residual);
1898 
1899     if (req->io_canceled) {
1900         return;
1901     }
1902 
1903     if (cmd->dcmd_opcode != -1) {
1904         /*
1905          * Internal command complete
1906          */
1907         cmd_status = megasas_finish_internal_dcmd(cmd, req, residual);
1908         if (cmd_status == MFI_STAT_INVALID_STATUS) {
1909             return;
1910         }
1911     } else {
1912         trace_megasas_scsi_complete(cmd->index, req->status,
1913                                     cmd->iov_size, req->cmd.xfer);
1914         if (req->status != GOOD) {
1915             cmd_status = MFI_STAT_SCSI_DONE_WITH_ERROR;
1916         }
1917         if (req->status == CHECK_CONDITION) {
1918             megasas_copy_sense(cmd);
1919         }
1920 
1921         cmd->frame->header.scsi_status = req->status;
1922     }
1923     cmd->frame->header.cmd_status = cmd_status;
1924     megasas_complete_command(cmd);
1925 }
1926 
megasas_command_cancelled(SCSIRequest * req)1927 static void megasas_command_cancelled(SCSIRequest *req)
1928 {
1929     MegasasCmd *cmd = req->hba_private;
1930 
1931     if (!cmd) {
1932         return;
1933     }
1934     cmd->frame->header.cmd_status = MFI_STAT_SCSI_IO_FAILED;
1935     megasas_complete_command(cmd);
1936 }
1937 
megasas_handle_abort(MegasasState * s,MegasasCmd * cmd)1938 static int megasas_handle_abort(MegasasState *s, MegasasCmd *cmd)
1939 {
1940     uint64_t abort_ctx = le64_to_cpu(cmd->frame->abort.abort_context);
1941     hwaddr abort_addr, addr_hi, addr_lo;
1942     MegasasCmd *abort_cmd;
1943 
1944     addr_hi = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_hi);
1945     addr_lo = le32_to_cpu(cmd->frame->abort.abort_mfi_addr_lo);
1946     abort_addr = ((uint64_t)addr_hi << 32) | addr_lo;
1947 
1948     abort_cmd = megasas_lookup_frame(s, abort_addr);
1949     if (!abort_cmd) {
1950         trace_megasas_abort_no_cmd(cmd->index, abort_ctx);
1951         s->event_count++;
1952         return MFI_STAT_OK;
1953     }
1954     if (!megasas_use_queue64(s)) {
1955         abort_ctx &= (uint64_t)0xFFFFFFFF;
1956     }
1957     if (abort_cmd->context != abort_ctx) {
1958         trace_megasas_abort_invalid_context(cmd->index, abort_cmd->context,
1959                                             abort_cmd->index);
1960         s->event_count++;
1961         return MFI_STAT_ABORT_NOT_POSSIBLE;
1962     }
1963     trace_megasas_abort_frame(cmd->index, abort_cmd->index);
1964     megasas_abort_command(abort_cmd);
1965     if (!s->event_cmd || abort_cmd != s->event_cmd) {
1966         s->event_cmd = NULL;
1967     }
1968     s->event_count++;
1969     return MFI_STAT_OK;
1970 }
1971 
megasas_handle_frame(MegasasState * s,uint64_t frame_addr,uint32_t frame_count)1972 static void megasas_handle_frame(MegasasState *s, uint64_t frame_addr,
1973                                  uint32_t frame_count)
1974 {
1975     uint8_t frame_status = MFI_STAT_INVALID_CMD;
1976     uint64_t frame_context;
1977     int frame_cmd;
1978     MegasasCmd *cmd;
1979 
1980     /*
1981      * Always read 64bit context, top bits will be
1982      * masked out if required in megasas_enqueue_frame()
1983      */
1984     frame_context = megasas_frame_get_context(s, frame_addr);
1985 
1986     cmd = megasas_enqueue_frame(s, frame_addr, frame_context, frame_count);
1987     if (!cmd) {
1988         /* reply queue full */
1989         trace_megasas_frame_busy(frame_addr);
1990         megasas_frame_set_scsi_status(s, frame_addr, BUSY);
1991         megasas_frame_set_cmd_status(s, frame_addr, MFI_STAT_SCSI_DONE_WITH_ERROR);
1992         megasas_complete_frame(s, frame_context);
1993         s->event_count++;
1994         return;
1995     }
1996     frame_cmd = cmd->frame->header.frame_cmd;
1997     switch (frame_cmd) {
1998     case MFI_CMD_INIT:
1999         frame_status = megasas_init_firmware(s, cmd);
2000         break;
2001     case MFI_CMD_DCMD:
2002         frame_status = megasas_handle_dcmd(s, cmd);
2003         break;
2004     case MFI_CMD_ABORT:
2005         frame_status = megasas_handle_abort(s, cmd);
2006         break;
2007     case MFI_CMD_PD_SCSI_IO:
2008     case MFI_CMD_LD_SCSI_IO:
2009         frame_status = megasas_handle_scsi(s, cmd, frame_cmd);
2010         break;
2011     case MFI_CMD_LD_READ:
2012     case MFI_CMD_LD_WRITE:
2013         frame_status = megasas_handle_io(s, cmd, frame_cmd);
2014         break;
2015     default:
2016         trace_megasas_unhandled_frame_cmd(cmd->index, frame_cmd);
2017         s->event_count++;
2018         break;
2019     }
2020     if (frame_status != MFI_STAT_INVALID_STATUS) {
2021         if (cmd->frame) {
2022             cmd->frame->header.cmd_status = frame_status;
2023         } else {
2024             megasas_frame_set_cmd_status(s, frame_addr, frame_status);
2025         }
2026         megasas_unmap_frame(s, cmd);
2027         megasas_complete_frame(s, cmd->context);
2028     }
2029 }
2030 
megasas_mmio_read(void * opaque,hwaddr addr,unsigned size)2031 static uint64_t megasas_mmio_read(void *opaque, hwaddr addr,
2032                                   unsigned size)
2033 {
2034     MegasasState *s = opaque;
2035     PCIDevice *pci_dev = PCI_DEVICE(s);
2036     MegasasBaseClass *base_class = MEGASAS_GET_CLASS(s);
2037     uint32_t retval = 0;
2038 
2039     switch (addr) {
2040     case MFI_IDB:
2041         retval = 0;
2042         trace_megasas_mmio_readl("MFI_IDB", retval);
2043         break;
2044     case MFI_OMSG0:
2045     case MFI_OSP0:
2046         retval = (msix_present(pci_dev) ? MFI_FWSTATE_MSIX_SUPPORTED : 0) |
2047             (s->fw_state & MFI_FWSTATE_MASK) |
2048             ((s->fw_sge & 0xff) << 16) |
2049             (s->fw_cmds & 0xFFFF);
2050         trace_megasas_mmio_readl(addr == MFI_OMSG0 ? "MFI_OMSG0" : "MFI_OSP0",
2051                                  retval);
2052         break;
2053     case MFI_OSTS:
2054         if (megasas_intr_enabled(s) && s->doorbell) {
2055             retval = base_class->osts;
2056         }
2057         trace_megasas_mmio_readl("MFI_OSTS", retval);
2058         break;
2059     case MFI_OMSK:
2060         retval = s->intr_mask;
2061         trace_megasas_mmio_readl("MFI_OMSK", retval);
2062         break;
2063     case MFI_ODCR0:
2064         retval = s->doorbell ? 1 : 0;
2065         trace_megasas_mmio_readl("MFI_ODCR0", retval);
2066         break;
2067     case MFI_DIAG:
2068         retval = s->diag;
2069         trace_megasas_mmio_readl("MFI_DIAG", retval);
2070         break;
2071     case MFI_OSP1:
2072         retval = 15;
2073         trace_megasas_mmio_readl("MFI_OSP1", retval);
2074         break;
2075     default:
2076         trace_megasas_mmio_invalid_readl(addr);
2077         break;
2078     }
2079     return retval;
2080 }
2081 
2082 static int adp_reset_seq[] = {0x00, 0x04, 0x0b, 0x02, 0x07, 0x0d};
2083 
megasas_mmio_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)2084 static void megasas_mmio_write(void *opaque, hwaddr addr,
2085                                uint64_t val, unsigned size)
2086 {
2087     MegasasState *s = opaque;
2088     PCIDevice *pci_dev = PCI_DEVICE(s);
2089     uint64_t frame_addr;
2090     uint32_t frame_count;
2091     int i;
2092 
2093     switch (addr) {
2094     case MFI_IDB:
2095         trace_megasas_mmio_writel("MFI_IDB", val);
2096         if (val & MFI_FWINIT_ABORT) {
2097             /* Abort all pending cmds */
2098             for (i = 0; i < s->fw_cmds; i++) {
2099                 megasas_abort_command(&s->frames[i]);
2100             }
2101         }
2102         if (val & MFI_FWINIT_READY) {
2103             /* move to FW READY */
2104             megasas_soft_reset(s);
2105         }
2106         if (val & MFI_FWINIT_MFIMODE) {
2107             /* discard MFIs */
2108         }
2109         if (val & MFI_FWINIT_STOP_ADP) {
2110             /* Terminal error, stop processing */
2111             s->fw_state = MFI_FWSTATE_FAULT;
2112         }
2113         break;
2114     case MFI_OMSK:
2115         trace_megasas_mmio_writel("MFI_OMSK", val);
2116         s->intr_mask = val;
2117         if (!megasas_intr_enabled(s) &&
2118             !msi_enabled(pci_dev) &&
2119             !msix_enabled(pci_dev)) {
2120             trace_megasas_irq_lower();
2121             pci_irq_deassert(pci_dev);
2122         }
2123         if (megasas_intr_enabled(s)) {
2124             if (msix_enabled(pci_dev)) {
2125                 trace_megasas_msix_enabled(0);
2126             } else if (msi_enabled(pci_dev)) {
2127                 trace_megasas_msi_enabled(0);
2128             } else {
2129                 trace_megasas_intr_enabled();
2130             }
2131         } else {
2132             trace_megasas_intr_disabled();
2133             megasas_soft_reset(s);
2134         }
2135         break;
2136     case MFI_ODCR0:
2137         trace_megasas_mmio_writel("MFI_ODCR0", val);
2138         s->doorbell = 0;
2139         if (megasas_intr_enabled(s)) {
2140             if (!msix_enabled(pci_dev) && !msi_enabled(pci_dev)) {
2141                 trace_megasas_irq_lower();
2142                 pci_irq_deassert(pci_dev);
2143             }
2144         }
2145         break;
2146     case MFI_IQPH:
2147         trace_megasas_mmio_writel("MFI_IQPH", val);
2148         /* Received high 32 bits of a 64 bit MFI frame address */
2149         s->frame_hi = val;
2150         break;
2151     case MFI_IQPL:
2152         trace_megasas_mmio_writel("MFI_IQPL", val);
2153         /* Received low 32 bits of a 64 bit MFI frame address */
2154         /* Fallthrough */
2155     case MFI_IQP:
2156         if (addr == MFI_IQP) {
2157             trace_megasas_mmio_writel("MFI_IQP", val);
2158             /* Received 64 bit MFI frame address */
2159             s->frame_hi = 0;
2160         }
2161         frame_addr = (val & ~0x1F);
2162         /* Add possible 64 bit offset */
2163         frame_addr |= ((uint64_t)s->frame_hi << 32);
2164         s->frame_hi = 0;
2165         frame_count = (val >> 1) & 0xF;
2166         megasas_handle_frame(s, frame_addr, frame_count);
2167         break;
2168     case MFI_SEQ:
2169         trace_megasas_mmio_writel("MFI_SEQ", val);
2170         /* Magic sequence to start ADP reset */
2171         if (adp_reset_seq[s->adp_reset++] == val) {
2172             if (s->adp_reset == 6) {
2173                 s->adp_reset = 0;
2174                 s->diag = MFI_DIAG_WRITE_ENABLE;
2175             }
2176         } else {
2177             s->adp_reset = 0;
2178             s->diag = 0;
2179         }
2180         break;
2181     case MFI_DIAG:
2182         trace_megasas_mmio_writel("MFI_DIAG", val);
2183         /* ADP reset */
2184         if ((s->diag & MFI_DIAG_WRITE_ENABLE) &&
2185             (val & MFI_DIAG_RESET_ADP)) {
2186             s->diag |= MFI_DIAG_RESET_ADP;
2187             megasas_soft_reset(s);
2188             s->adp_reset = 0;
2189             s->diag = 0;
2190         }
2191         break;
2192     default:
2193         trace_megasas_mmio_invalid_writel(addr, val);
2194         break;
2195     }
2196 }
2197 
2198 static const MemoryRegionOps megasas_mmio_ops = {
2199     .read = megasas_mmio_read,
2200     .write = megasas_mmio_write,
2201     .endianness = DEVICE_LITTLE_ENDIAN,
2202     .impl = {
2203         .min_access_size = 8,
2204         .max_access_size = 8,
2205     }
2206 };
2207 
megasas_port_read(void * opaque,hwaddr addr,unsigned size)2208 static uint64_t megasas_port_read(void *opaque, hwaddr addr,
2209                                   unsigned size)
2210 {
2211     return megasas_mmio_read(opaque, addr & 0xff, size);
2212 }
2213 
megasas_port_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)2214 static void megasas_port_write(void *opaque, hwaddr addr,
2215                                uint64_t val, unsigned size)
2216 {
2217     megasas_mmio_write(opaque, addr & 0xff, val, size);
2218 }
2219 
2220 static const MemoryRegionOps megasas_port_ops = {
2221     .read = megasas_port_read,
2222     .write = megasas_port_write,
2223     .endianness = DEVICE_LITTLE_ENDIAN,
2224     .impl = {
2225         .min_access_size = 4,
2226         .max_access_size = 4,
2227     }
2228 };
2229 
megasas_queue_read(void * opaque,hwaddr addr,unsigned size)2230 static uint64_t megasas_queue_read(void *opaque, hwaddr addr,
2231                                    unsigned size)
2232 {
2233     return 0;
2234 }
2235 
megasas_queue_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)2236 static void megasas_queue_write(void *opaque, hwaddr addr,
2237                                uint64_t val, unsigned size)
2238 {
2239     return;
2240 }
2241 
2242 static const MemoryRegionOps megasas_queue_ops = {
2243     .read = megasas_queue_read,
2244     .write = megasas_queue_write,
2245     .endianness = DEVICE_LITTLE_ENDIAN,
2246     .impl = {
2247         .min_access_size = 8,
2248         .max_access_size = 8,
2249     }
2250 };
2251 
megasas_soft_reset(MegasasState * s)2252 static void megasas_soft_reset(MegasasState *s)
2253 {
2254     int i;
2255     MegasasCmd *cmd;
2256 
2257     trace_megasas_reset(s->fw_state);
2258     for (i = 0; i < s->fw_cmds; i++) {
2259         cmd = &s->frames[i];
2260         megasas_abort_command(cmd);
2261     }
2262     if (s->fw_state == MFI_FWSTATE_READY) {
2263         BusChild *kid;
2264 
2265         /*
2266          * The EFI firmware doesn't handle UA,
2267          * so we need to clear the Power On/Reset UA
2268          * after the initial reset.
2269          */
2270         QTAILQ_FOREACH(kid, &s->bus.qbus.children, sibling) {
2271             SCSIDevice *sdev = SCSI_DEVICE(kid->child);
2272 
2273             sdev->unit_attention = SENSE_CODE(NO_SENSE);
2274             scsi_device_unit_attention_reported(sdev);
2275         }
2276     }
2277     megasas_reset_frames(s);
2278     s->reply_queue_len = s->fw_cmds;
2279     s->reply_queue_pa = 0;
2280     s->consumer_pa = 0;
2281     s->producer_pa = 0;
2282     s->fw_state = MFI_FWSTATE_READY;
2283     s->doorbell = 0;
2284     s->intr_mask = MEGASAS_INTR_DISABLED_MASK;
2285     s->frame_hi = 0;
2286     s->flags &= ~MEGASAS_MASK_USE_QUEUE64;
2287     s->event_count++;
2288     s->boot_event = s->event_count;
2289 }
2290 
megasas_scsi_reset(DeviceState * dev)2291 static void megasas_scsi_reset(DeviceState *dev)
2292 {
2293     MegasasState *s = MEGASAS(dev);
2294 
2295     megasas_soft_reset(s);
2296 }
2297 
2298 static const VMStateDescription vmstate_megasas_gen1 = {
2299     .name = "megasas",
2300     .version_id = 0,
2301     .minimum_version_id = 0,
2302     .fields = (const VMStateField[]) {
2303         VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2304         VMSTATE_MSIX(parent_obj, MegasasState),
2305 
2306         VMSTATE_UINT32(fw_state, MegasasState),
2307         VMSTATE_UINT32(intr_mask, MegasasState),
2308         VMSTATE_UINT32(doorbell, MegasasState),
2309         VMSTATE_UINT64(reply_queue_pa, MegasasState),
2310         VMSTATE_UINT64(consumer_pa, MegasasState),
2311         VMSTATE_UINT64(producer_pa, MegasasState),
2312         VMSTATE_END_OF_LIST()
2313     }
2314 };
2315 
2316 static const VMStateDescription vmstate_megasas_gen2 = {
2317     .name = "megasas-gen2",
2318     .version_id = 0,
2319     .minimum_version_id = 0,
2320     .fields = (const VMStateField[]) {
2321         VMSTATE_PCI_DEVICE(parent_obj, MegasasState),
2322         VMSTATE_MSIX(parent_obj, MegasasState),
2323 
2324         VMSTATE_UINT32(fw_state, MegasasState),
2325         VMSTATE_UINT32(intr_mask, MegasasState),
2326         VMSTATE_UINT32(doorbell, MegasasState),
2327         VMSTATE_UINT64(reply_queue_pa, MegasasState),
2328         VMSTATE_UINT64(consumer_pa, MegasasState),
2329         VMSTATE_UINT64(producer_pa, MegasasState),
2330         VMSTATE_END_OF_LIST()
2331     }
2332 };
2333 
megasas_scsi_uninit(PCIDevice * d)2334 static void megasas_scsi_uninit(PCIDevice *d)
2335 {
2336     MegasasState *s = MEGASAS(d);
2337 
2338     if (megasas_use_msix(s)) {
2339         msix_uninit(d, &s->mmio_io, &s->mmio_io);
2340     }
2341     msi_uninit(d);
2342 }
2343 
2344 static const struct SCSIBusInfo megasas_scsi_info = {
2345     .tcq = true,
2346     .max_target = MFI_MAX_LD,
2347     .max_lun = 255,
2348 
2349     .transfer_data = megasas_xfer_complete,
2350     .get_sg_list = megasas_get_sg_list,
2351     .complete = megasas_command_complete,
2352     .cancel = megasas_command_cancelled,
2353 };
2354 
megasas_scsi_realize(PCIDevice * dev,Error ** errp)2355 static void megasas_scsi_realize(PCIDevice *dev, Error **errp)
2356 {
2357     MegasasState *s = MEGASAS(dev);
2358     MegasasBaseClass *b = MEGASAS_GET_CLASS(s);
2359     uint8_t *pci_conf;
2360     uint32_t sge;
2361     int i, bar_type;
2362     Error *err = NULL;
2363     int ret;
2364 
2365     pci_conf = dev->config;
2366 
2367     /* PCI latency timer = 0 */
2368     pci_conf[PCI_LATENCY_TIMER] = 0;
2369     /* Interrupt pin 1 */
2370     pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2371 
2372     if (s->msi != ON_OFF_AUTO_OFF) {
2373         ret = msi_init(dev, 0x50, 1, true, false, &err);
2374         /* Any error other than -ENOTSUP(board's MSI support is broken)
2375          * is a programming error */
2376         assert(!ret || ret == -ENOTSUP);
2377         if (ret && s->msi == ON_OFF_AUTO_ON) {
2378             /* Can't satisfy user's explicit msi=on request, fail */
2379             error_append_hint(&err, "You have to use msi=auto (default) or "
2380                     "msi=off with this machine type.\n");
2381             error_propagate(errp, err);
2382             return;
2383         } else if (ret) {
2384             /* With msi=auto, we fall back to MSI off silently */
2385             s->msi = ON_OFF_AUTO_OFF;
2386             error_free(err);
2387         }
2388     }
2389 
2390     memory_region_init_io(&s->mmio_io, OBJECT(s), &megasas_mmio_ops, s,
2391                           "megasas-mmio", 0x4000);
2392     memory_region_init_io(&s->port_io, OBJECT(s), &megasas_port_ops, s,
2393                           "megasas-io", 256);
2394     memory_region_init_io(&s->queue_io, OBJECT(s), &megasas_queue_ops, s,
2395                           "megasas-queue", 0x40000);
2396 
2397     if (megasas_use_msix(s) &&
2398         msix_init(dev, 15, &s->mmio_io, b->mmio_bar, 0x2000,
2399                   &s->mmio_io, b->mmio_bar, 0x3800, 0x68, NULL)) {
2400         /* TODO: check msix_init's error, and should fail on msix=on */
2401         s->msix = ON_OFF_AUTO_OFF;
2402     }
2403 
2404     if (pci_is_express(dev)) {
2405         pcie_endpoint_cap_init(dev, 0xa0);
2406     }
2407 
2408     bar_type = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64;
2409     pci_register_bar(dev, b->ioport_bar,
2410                      PCI_BASE_ADDRESS_SPACE_IO, &s->port_io);
2411     pci_register_bar(dev, b->mmio_bar, bar_type, &s->mmio_io);
2412     pci_register_bar(dev, 3, bar_type, &s->queue_io);
2413 
2414     if (megasas_use_msix(s)) {
2415         msix_vector_use(dev, 0);
2416     }
2417 
2418     s->fw_state = MFI_FWSTATE_READY;
2419     if (!s->sas_addr) {
2420         s->sas_addr = ((NAA_LOCALLY_ASSIGNED_ID << 24) |
2421                        IEEE_COMPANY_LOCALLY_ASSIGNED) << 36;
2422         s->sas_addr |= pci_dev_bus_num(dev) << 16;
2423         s->sas_addr |= PCI_SLOT(dev->devfn) << 8;
2424         s->sas_addr |= PCI_FUNC(dev->devfn);
2425     }
2426     if (!s->hba_serial) {
2427         s->hba_serial = g_strdup(MEGASAS_HBA_SERIAL);
2428     }
2429 
2430     sge = s->fw_sge + MFI_PASS_FRAME_SIZE;
2431     if (sge < MEGASAS_MIN_SGE) {
2432         sge = MEGASAS_MIN_SGE;
2433     } else if (sge >= MEGASAS_MAX_SGE) {
2434         sge = MEGASAS_MAX_SGE;
2435     }
2436     s->fw_sge = sge - MFI_PASS_FRAME_SIZE;
2437 
2438     if (s->fw_cmds > MEGASAS_MAX_FRAMES) {
2439         s->fw_cmds = MEGASAS_MAX_FRAMES;
2440     }
2441     trace_megasas_init(s->fw_sge, s->fw_cmds,
2442                        megasas_is_jbod(s) ? "jbod" : "raid");
2443 
2444     if (megasas_is_jbod(s)) {
2445         s->fw_luns = MFI_MAX_SYS_PDS;
2446     } else {
2447         s->fw_luns = MFI_MAX_LD;
2448     }
2449     s->producer_pa = 0;
2450     s->consumer_pa = 0;
2451     for (i = 0; i < s->fw_cmds; i++) {
2452         s->frames[i].index = i;
2453         s->frames[i].context = -1;
2454         s->frames[i].pa = 0;
2455         s->frames[i].state = s;
2456     }
2457 
2458     scsi_bus_init(&s->bus, sizeof(s->bus), DEVICE(dev), &megasas_scsi_info);
2459 }
2460 
2461 static Property megasas_properties_gen1[] = {
2462     DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2463                        MEGASAS_DEFAULT_SGE),
2464     DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2465                        MEGASAS_DEFAULT_FRAMES),
2466     DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2467     DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2468     DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2469     DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2470     DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2471                     MEGASAS_FLAG_USE_JBOD, false),
2472     DEFINE_PROP_END_OF_LIST(),
2473 };
2474 
2475 static Property megasas_properties_gen2[] = {
2476     DEFINE_PROP_UINT32("max_sge", MegasasState, fw_sge,
2477                        MEGASAS_DEFAULT_SGE),
2478     DEFINE_PROP_UINT32("max_cmds", MegasasState, fw_cmds,
2479                        MEGASAS_GEN2_DEFAULT_FRAMES),
2480     DEFINE_PROP_STRING("hba_serial", MegasasState, hba_serial),
2481     DEFINE_PROP_UINT64("sas_address", MegasasState, sas_addr, 0),
2482     DEFINE_PROP_ON_OFF_AUTO("msi", MegasasState, msi, ON_OFF_AUTO_AUTO),
2483     DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO),
2484     DEFINE_PROP_BIT("use_jbod", MegasasState, flags,
2485                     MEGASAS_FLAG_USE_JBOD, false),
2486     DEFINE_PROP_END_OF_LIST(),
2487 };
2488 
2489 typedef struct MegasasInfo {
2490     const char *name;
2491     const char *desc;
2492     const char *product_name;
2493     const char *product_version;
2494     uint16_t device_id;
2495     uint16_t subsystem_id;
2496     int ioport_bar;
2497     int mmio_bar;
2498     int osts;
2499     const VMStateDescription *vmsd;
2500     Property *props;
2501     InterfaceInfo *interfaces;
2502 } MegasasInfo;
2503 
2504 static struct MegasasInfo megasas_devices[] = {
2505     {
2506         .name = TYPE_MEGASAS_GEN1,
2507         .desc = "LSI MegaRAID SAS 1078",
2508         .product_name = "LSI MegaRAID SAS 8708EM2",
2509         .product_version = MEGASAS_VERSION_GEN1,
2510         .device_id = PCI_DEVICE_ID_LSI_SAS1078,
2511         .subsystem_id = 0x1013,
2512         .ioport_bar = 2,
2513         .mmio_bar = 0,
2514         .osts = MFI_1078_RM | 1,
2515         .vmsd = &vmstate_megasas_gen1,
2516         .props = megasas_properties_gen1,
2517         .interfaces = (InterfaceInfo[]) {
2518             { INTERFACE_CONVENTIONAL_PCI_DEVICE },
2519             { },
2520         },
2521     },{
2522         .name = TYPE_MEGASAS_GEN2,
2523         .desc = "LSI MegaRAID SAS 2108",
2524         .product_name = "LSI MegaRAID SAS 9260-8i",
2525         .product_version = MEGASAS_VERSION_GEN2,
2526         .device_id = PCI_DEVICE_ID_LSI_SAS0079,
2527         .subsystem_id = 0x9261,
2528         .ioport_bar = 0,
2529         .mmio_bar = 1,
2530         .osts = MFI_GEN2_RM,
2531         .vmsd = &vmstate_megasas_gen2,
2532         .props = megasas_properties_gen2,
2533         .interfaces = (InterfaceInfo[]) {
2534             { INTERFACE_PCIE_DEVICE },
2535             { }
2536         },
2537     }
2538 };
2539 
megasas_class_init(ObjectClass * oc,void * data)2540 static void megasas_class_init(ObjectClass *oc, void *data)
2541 {
2542     DeviceClass *dc = DEVICE_CLASS(oc);
2543     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
2544     MegasasBaseClass *e = MEGASAS_CLASS(oc);
2545     const MegasasInfo *info = data;
2546 
2547     pc->realize = megasas_scsi_realize;
2548     pc->exit = megasas_scsi_uninit;
2549     pc->vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2550     pc->device_id = info->device_id;
2551     pc->subsystem_vendor_id = PCI_VENDOR_ID_LSI_LOGIC;
2552     pc->subsystem_id = info->subsystem_id;
2553     pc->class_id = PCI_CLASS_STORAGE_RAID;
2554     e->mmio_bar = info->mmio_bar;
2555     e->ioport_bar = info->ioport_bar;
2556     e->osts = info->osts;
2557     e->product_name = info->product_name;
2558     e->product_version = info->product_version;
2559     device_class_set_props(dc, info->props);
2560     dc->reset = megasas_scsi_reset;
2561     dc->vmsd = info->vmsd;
2562     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2563     dc->desc = info->desc;
2564 }
2565 
2566 static const TypeInfo megasas_info = {
2567     .name  = TYPE_MEGASAS_BASE,
2568     .parent = TYPE_PCI_DEVICE,
2569     .instance_size = sizeof(MegasasState),
2570     .class_size = sizeof(MegasasBaseClass),
2571     .abstract = true,
2572 };
2573 
megasas_register_types(void)2574 static void megasas_register_types(void)
2575 {
2576     int i;
2577 
2578     type_register_static(&megasas_info);
2579     for (i = 0; i < ARRAY_SIZE(megasas_devices); i++) {
2580         const MegasasInfo *info = &megasas_devices[i];
2581         TypeInfo type_info = {};
2582 
2583         type_info.name = info->name;
2584         type_info.parent = TYPE_MEGASAS_BASE;
2585         type_info.class_data = (void *)info;
2586         type_info.class_init = megasas_class_init;
2587         type_info.interfaces = info->interfaces;
2588 
2589         type_register(&type_info);
2590     }
2591 }
2592 
2593 type_init(megasas_register_types)
2594