xref: /openbmc/linux/drivers/net/mdio/mdio-ipq4019.c (revision c58e3994)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright (c) 2015, The Linux Foundation. All rights reserved. */
3 /* Copyright (c) 2020 Sartura Ltd. */
4 
5 #include <linux/delay.h>
6 #include <linux/io.h>
7 #include <linux/iopoll.h>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/of_address.h>
11 #include <linux/of_mdio.h>
12 #include <linux/phy.h>
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 
16 #define MDIO_MODE_REG				0x40
17 #define MDIO_ADDR_REG				0x44
18 #define MDIO_DATA_WRITE_REG			0x48
19 #define MDIO_DATA_READ_REG			0x4c
20 #define MDIO_CMD_REG				0x50
21 #define MDIO_CMD_ACCESS_BUSY		BIT(16)
22 #define MDIO_CMD_ACCESS_START		BIT(8)
23 #define MDIO_CMD_ACCESS_CODE_READ	0
24 #define MDIO_CMD_ACCESS_CODE_WRITE	1
25 #define MDIO_CMD_ACCESS_CODE_C45_ADDR	0
26 #define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
27 #define MDIO_CMD_ACCESS_CODE_C45_READ	2
28 
29 /* 0 = Clause 22, 1 = Clause 45 */
30 #define MDIO_MODE_C45				BIT(8)
31 
32 #define IPQ4019_MDIO_TIMEOUT	10000
33 #define IPQ4019_MDIO_SLEEP		10
34 
35 /* MDIO clock source frequency is fixed to 100M */
36 #define IPQ_MDIO_CLK_RATE	100000000
37 
38 #define IPQ_PHY_SET_DELAY_US	100000
39 
40 struct ipq4019_mdio_data {
41 	void __iomem	*membase;
42 	void __iomem *eth_ldo_rdy;
43 	struct clk *mdio_clk;
44 };
45 
ipq4019_mdio_wait_busy(struct mii_bus * bus)46 static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
47 {
48 	struct ipq4019_mdio_data *priv = bus->priv;
49 	unsigned int busy;
50 
51 	return readl_poll_timeout(priv->membase + MDIO_CMD_REG, busy,
52 				  (busy & MDIO_CMD_ACCESS_BUSY) == 0,
53 				  IPQ4019_MDIO_SLEEP, IPQ4019_MDIO_TIMEOUT);
54 }
55 
ipq4019_mdio_read_c45(struct mii_bus * bus,int mii_id,int mmd,int reg)56 static int ipq4019_mdio_read_c45(struct mii_bus *bus, int mii_id, int mmd,
57 				 int reg)
58 {
59 	struct ipq4019_mdio_data *priv = bus->priv;
60 	unsigned int data;
61 	unsigned int cmd;
62 
63 	if (ipq4019_mdio_wait_busy(bus))
64 		return -ETIMEDOUT;
65 
66 	data = readl(priv->membase + MDIO_MODE_REG);
67 
68 	data |= MDIO_MODE_C45;
69 
70 	writel(data, priv->membase + MDIO_MODE_REG);
71 
72 	/* issue the phy address and mmd */
73 	writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
74 
75 	/* issue reg */
76 	writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
77 
78 	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR;
79 
80 	/* issue read command */
81 	writel(cmd, priv->membase + MDIO_CMD_REG);
82 
83 	/* Wait read complete */
84 	if (ipq4019_mdio_wait_busy(bus))
85 		return -ETIMEDOUT;
86 
87 	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_READ;
88 
89 	writel(cmd, priv->membase + MDIO_CMD_REG);
90 
91 	if (ipq4019_mdio_wait_busy(bus))
92 		return -ETIMEDOUT;
93 
94 	/* Read and return data */
95 	return readl(priv->membase + MDIO_DATA_READ_REG);
96 }
97 
ipq4019_mdio_read_c22(struct mii_bus * bus,int mii_id,int regnum)98 static int ipq4019_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum)
99 {
100 	struct ipq4019_mdio_data *priv = bus->priv;
101 	unsigned int data;
102 	unsigned int cmd;
103 
104 	if (ipq4019_mdio_wait_busy(bus))
105 		return -ETIMEDOUT;
106 
107 	data = readl(priv->membase + MDIO_MODE_REG);
108 
109 	data &= ~MDIO_MODE_C45;
110 
111 	writel(data, priv->membase + MDIO_MODE_REG);
112 
113 	/* issue the phy address and reg */
114 	writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
115 
116 	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_READ;
117 
118 	/* issue read command */
119 	writel(cmd, priv->membase + MDIO_CMD_REG);
120 
121 	/* Wait read complete */
122 	if (ipq4019_mdio_wait_busy(bus))
123 		return -ETIMEDOUT;
124 
125 	/* Read and return data */
126 	return readl(priv->membase + MDIO_DATA_READ_REG);
127 }
128 
ipq4019_mdio_write_c45(struct mii_bus * bus,int mii_id,int mmd,int reg,u16 value)129 static int ipq4019_mdio_write_c45(struct mii_bus *bus, int mii_id, int mmd,
130 				  int reg, u16 value)
131 {
132 	struct ipq4019_mdio_data *priv = bus->priv;
133 	unsigned int data;
134 	unsigned int cmd;
135 
136 	if (ipq4019_mdio_wait_busy(bus))
137 		return -ETIMEDOUT;
138 
139 	data = readl(priv->membase + MDIO_MODE_REG);
140 
141 	data |= MDIO_MODE_C45;
142 
143 	writel(data, priv->membase + MDIO_MODE_REG);
144 
145 	/* issue the phy address and mmd */
146 	writel((mii_id << 8) | mmd, priv->membase + MDIO_ADDR_REG);
147 
148 	/* issue reg */
149 	writel(reg, priv->membase + MDIO_DATA_WRITE_REG);
150 
151 	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_ADDR;
152 
153 	writel(cmd, priv->membase + MDIO_CMD_REG);
154 
155 	if (ipq4019_mdio_wait_busy(bus))
156 		return -ETIMEDOUT;
157 
158 	/* issue write data */
159 	writel(value, priv->membase + MDIO_DATA_WRITE_REG);
160 
161 	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_C45_WRITE;
162 	writel(cmd, priv->membase + MDIO_CMD_REG);
163 
164 	/* Wait write complete */
165 	if (ipq4019_mdio_wait_busy(bus))
166 		return -ETIMEDOUT;
167 
168 	return 0;
169 }
170 
ipq4019_mdio_write_c22(struct mii_bus * bus,int mii_id,int regnum,u16 value)171 static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum,
172 				  u16 value)
173 {
174 	struct ipq4019_mdio_data *priv = bus->priv;
175 	unsigned int data;
176 	unsigned int cmd;
177 
178 	if (ipq4019_mdio_wait_busy(bus))
179 		return -ETIMEDOUT;
180 
181 	/* Enter Clause 22 mode */
182 	data = readl(priv->membase + MDIO_MODE_REG);
183 
184 	data &= ~MDIO_MODE_C45;
185 
186 	writel(data, priv->membase + MDIO_MODE_REG);
187 
188 	/* issue the phy address and reg */
189 	writel((mii_id << 8) | regnum, priv->membase + MDIO_ADDR_REG);
190 
191 	/* issue write data */
192 	writel(value, priv->membase + MDIO_DATA_WRITE_REG);
193 
194 	/* issue write command */
195 	cmd = MDIO_CMD_ACCESS_START | MDIO_CMD_ACCESS_CODE_WRITE;
196 
197 	writel(cmd, priv->membase + MDIO_CMD_REG);
198 
199 	/* Wait write complete */
200 	if (ipq4019_mdio_wait_busy(bus))
201 		return -ETIMEDOUT;
202 
203 	return 0;
204 }
205 
ipq_mdio_reset(struct mii_bus * bus)206 static int ipq_mdio_reset(struct mii_bus *bus)
207 {
208 	struct ipq4019_mdio_data *priv = bus->priv;
209 	u32 val;
210 	int ret;
211 
212 	/* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1
213 	 * is specified in the device tree.
214 	 */
215 	if (priv->eth_ldo_rdy) {
216 		val = readl(priv->eth_ldo_rdy);
217 		val |= BIT(0);
218 		writel(val, priv->eth_ldo_rdy);
219 		fsleep(IPQ_PHY_SET_DELAY_US);
220 	}
221 
222 	/* Configure MDIO clock source frequency if clock is specified in the device tree */
223 	ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE);
224 	if (ret)
225 		return ret;
226 
227 	ret = clk_prepare_enable(priv->mdio_clk);
228 	if (ret == 0)
229 		mdelay(10);
230 
231 	return ret;
232 }
233 
ipq4019_mdio_probe(struct platform_device * pdev)234 static int ipq4019_mdio_probe(struct platform_device *pdev)
235 {
236 	struct ipq4019_mdio_data *priv;
237 	struct mii_bus *bus;
238 	struct resource *res;
239 	int ret;
240 
241 	bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(*priv));
242 	if (!bus)
243 		return -ENOMEM;
244 
245 	priv = bus->priv;
246 
247 	priv->membase = devm_platform_ioremap_resource(pdev, 0);
248 	if (IS_ERR(priv->membase))
249 		return PTR_ERR(priv->membase);
250 
251 	priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk");
252 	if (IS_ERR(priv->mdio_clk))
253 		return PTR_ERR(priv->mdio_clk);
254 
255 	/* The platform resource is provided on the chipset IPQ5018 */
256 	/* This resource is optional */
257 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
258 	if (res)
259 		priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res);
260 
261 	bus->name = "ipq4019_mdio";
262 	bus->read = ipq4019_mdio_read_c22;
263 	bus->write = ipq4019_mdio_write_c22;
264 	bus->read_c45 = ipq4019_mdio_read_c45;
265 	bus->write_c45 = ipq4019_mdio_write_c45;
266 	bus->reset = ipq_mdio_reset;
267 	bus->parent = &pdev->dev;
268 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s%d", pdev->name, pdev->id);
269 
270 	ret = of_mdiobus_register(bus, pdev->dev.of_node);
271 	if (ret) {
272 		dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
273 		return ret;
274 	}
275 
276 	platform_set_drvdata(pdev, bus);
277 
278 	return 0;
279 }
280 
ipq4019_mdio_remove(struct platform_device * pdev)281 static int ipq4019_mdio_remove(struct platform_device *pdev)
282 {
283 	struct mii_bus *bus = platform_get_drvdata(pdev);
284 
285 	mdiobus_unregister(bus);
286 
287 	return 0;
288 }
289 
290 static const struct of_device_id ipq4019_mdio_dt_ids[] = {
291 	{ .compatible = "qcom,ipq4019-mdio" },
292 	{ .compatible = "qcom,ipq5018-mdio" },
293 	{ }
294 };
295 MODULE_DEVICE_TABLE(of, ipq4019_mdio_dt_ids);
296 
297 static struct platform_driver ipq4019_mdio_driver = {
298 	.probe = ipq4019_mdio_probe,
299 	.remove = ipq4019_mdio_remove,
300 	.driver = {
301 		.name = "ipq4019-mdio",
302 		.of_match_table = ipq4019_mdio_dt_ids,
303 	},
304 };
305 
306 module_platform_driver(ipq4019_mdio_driver);
307 
308 MODULE_DESCRIPTION("ipq4019 MDIO interface driver");
309 MODULE_AUTHOR("Qualcomm Atheros");
310 MODULE_LICENSE("Dual BSD/GPL");
311