1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * (c) 2005-2016 Advanced Micro Devices, Inc.
4 *
5 * Written by Jacob Shin - AMD, Inc.
6 * Maintained by: Borislav Petkov <bp@alien8.de>
7 *
8 * All MC4_MISCi registers are shared between cores on a node.
9 */
10 #include <linux/interrupt.h>
11 #include <linux/notifier.h>
12 #include <linux/kobject.h>
13 #include <linux/percpu.h>
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/sysfs.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/cpu.h>
20 #include <linux/smp.h>
21 #include <linux/string.h>
22
23 #include <asm/amd_nb.h>
24 #include <asm/traps.h>
25 #include <asm/apic.h>
26 #include <asm/mce.h>
27 #include <asm/msr.h>
28 #include <asm/trace/irq_vectors.h>
29
30 #include "internal.h"
31
32 #define NR_BLOCKS 5
33 #define THRESHOLD_MAX 0xFFF
34 #define INT_TYPE_APIC 0x00020000
35 #define MASK_VALID_HI 0x80000000
36 #define MASK_CNTP_HI 0x40000000
37 #define MASK_LOCKED_HI 0x20000000
38 #define MASK_LVTOFF_HI 0x00F00000
39 #define MASK_COUNT_EN_HI 0x00080000
40 #define MASK_INT_TYPE_HI 0x00060000
41 #define MASK_OVERFLOW_HI 0x00010000
42 #define MASK_ERR_COUNT_HI 0x00000FFF
43 #define MASK_BLKPTR_LO 0xFF000000
44 #define MCG_XBLK_ADDR 0xC0000400
45
46 /* Deferred error settings */
47 #define MSR_CU_DEF_ERR 0xC0000410
48 #define MASK_DEF_LVTOFF 0x000000F0
49 #define MASK_DEF_INT_TYPE 0x00000006
50 #define DEF_LVT_OFF 0x2
51 #define DEF_INT_TYPE_APIC 0x2
52
53 /* Scalable MCA: */
54
55 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
56 #define SMCA_THR_LVT_OFF 0xF000
57
58 static bool thresholding_irq_en;
59
60 static const char * const th_names[] = {
61 "load_store",
62 "insn_fetch",
63 "combined_unit",
64 "decode_unit",
65 "northbridge",
66 "execution_unit",
67 };
68
69 static const char * const smca_umc_block_names[] = {
70 "dram_ecc",
71 "misc_umc"
72 };
73
74 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
75
76 struct smca_hwid {
77 unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
78 u32 hwid_mcatype; /* (hwid,mcatype) tuple */
79 };
80
81 struct smca_bank {
82 const struct smca_hwid *hwid;
83 u32 id; /* Value of MCA_IPID[InstanceId]. */
84 u8 sysfs_id; /* Value used for sysfs name. */
85 };
86
87 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
88 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
89
90 struct smca_bank_name {
91 const char *name; /* Short name for sysfs */
92 const char *long_name; /* Long name for pretty-printing */
93 };
94
95 static struct smca_bank_name smca_names[] = {
96 [SMCA_LS ... SMCA_LS_V2] = { "load_store", "Load Store Unit" },
97 [SMCA_IF] = { "insn_fetch", "Instruction Fetch Unit" },
98 [SMCA_L2_CACHE] = { "l2_cache", "L2 Cache" },
99 [SMCA_DE] = { "decode_unit", "Decode Unit" },
100 [SMCA_RESERVED] = { "reserved", "Reserved" },
101 [SMCA_EX] = { "execution_unit", "Execution Unit" },
102 [SMCA_FP] = { "floating_point", "Floating Point Unit" },
103 [SMCA_L3_CACHE] = { "l3_cache", "L3 Cache" },
104 [SMCA_CS ... SMCA_CS_V2] = { "coherent_slave", "Coherent Slave" },
105 [SMCA_PIE] = { "pie", "Power, Interrupts, etc." },
106
107 /* UMC v2 is separate because both of them can exist in a single system. */
108 [SMCA_UMC] = { "umc", "Unified Memory Controller" },
109 [SMCA_UMC_V2] = { "umc_v2", "Unified Memory Controller v2" },
110 [SMCA_PB] = { "param_block", "Parameter Block" },
111 [SMCA_PSP ... SMCA_PSP_V2] = { "psp", "Platform Security Processor" },
112 [SMCA_SMU ... SMCA_SMU_V2] = { "smu", "System Management Unit" },
113 [SMCA_MP5] = { "mp5", "Microprocessor 5 Unit" },
114 [SMCA_MPDMA] = { "mpdma", "MPDMA Unit" },
115 [SMCA_NBIO] = { "nbio", "Northbridge IO Unit" },
116 [SMCA_PCIE ... SMCA_PCIE_V2] = { "pcie", "PCI Express Unit" },
117 [SMCA_XGMI_PCS] = { "xgmi_pcs", "Ext Global Memory Interconnect PCS Unit" },
118 [SMCA_NBIF] = { "nbif", "NBIF Unit" },
119 [SMCA_SHUB] = { "shub", "System Hub Unit" },
120 [SMCA_SATA] = { "sata", "SATA Unit" },
121 [SMCA_USB] = { "usb", "USB Unit" },
122 [SMCA_GMI_PCS] = { "gmi_pcs", "Global Memory Interconnect PCS Unit" },
123 [SMCA_XGMI_PHY] = { "xgmi_phy", "Ext Global Memory Interconnect PHY Unit" },
124 [SMCA_WAFL_PHY] = { "wafl_phy", "WAFL PHY Unit" },
125 [SMCA_GMI_PHY] = { "gmi_phy", "Global Memory Interconnect PHY Unit" },
126 };
127
smca_get_name(enum smca_bank_types t)128 static const char *smca_get_name(enum smca_bank_types t)
129 {
130 if (t >= N_SMCA_BANK_TYPES)
131 return NULL;
132
133 return smca_names[t].name;
134 }
135
smca_get_long_name(enum smca_bank_types t)136 const char *smca_get_long_name(enum smca_bank_types t)
137 {
138 if (t >= N_SMCA_BANK_TYPES)
139 return NULL;
140
141 return smca_names[t].long_name;
142 }
143 EXPORT_SYMBOL_GPL(smca_get_long_name);
144
smca_get_bank_type(unsigned int cpu,unsigned int bank)145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
146 {
147 struct smca_bank *b;
148
149 if (bank >= MAX_NR_BANKS)
150 return N_SMCA_BANK_TYPES;
151
152 b = &per_cpu(smca_banks, cpu)[bank];
153 if (!b->hwid)
154 return N_SMCA_BANK_TYPES;
155
156 return b->hwid->bank_type;
157 }
158 EXPORT_SYMBOL_GPL(smca_get_bank_type);
159
160 static const struct smca_hwid smca_hwid_mcatypes[] = {
161 /* { bank_type, hwid_mcatype } */
162
163 /* Reserved type */
164 { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0) },
165
166 /* ZN Core (HWID=0xB0) MCA types */
167 { SMCA_LS, HWID_MCATYPE(0xB0, 0x0) },
168 { SMCA_LS_V2, HWID_MCATYPE(0xB0, 0x10) },
169 { SMCA_IF, HWID_MCATYPE(0xB0, 0x1) },
170 { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2) },
171 { SMCA_DE, HWID_MCATYPE(0xB0, 0x3) },
172 /* HWID 0xB0 MCATYPE 0x4 is Reserved */
173 { SMCA_EX, HWID_MCATYPE(0xB0, 0x5) },
174 { SMCA_FP, HWID_MCATYPE(0xB0, 0x6) },
175 { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7) },
176
177 /* Data Fabric MCA types */
178 { SMCA_CS, HWID_MCATYPE(0x2E, 0x0) },
179 { SMCA_PIE, HWID_MCATYPE(0x2E, 0x1) },
180 { SMCA_CS_V2, HWID_MCATYPE(0x2E, 0x2) },
181
182 /* Unified Memory Controller MCA type */
183 { SMCA_UMC, HWID_MCATYPE(0x96, 0x0) },
184 { SMCA_UMC_V2, HWID_MCATYPE(0x96, 0x1) },
185
186 /* Parameter Block MCA type */
187 { SMCA_PB, HWID_MCATYPE(0x05, 0x0) },
188
189 /* Platform Security Processor MCA type */
190 { SMCA_PSP, HWID_MCATYPE(0xFF, 0x0) },
191 { SMCA_PSP_V2, HWID_MCATYPE(0xFF, 0x1) },
192
193 /* System Management Unit MCA type */
194 { SMCA_SMU, HWID_MCATYPE(0x01, 0x0) },
195 { SMCA_SMU_V2, HWID_MCATYPE(0x01, 0x1) },
196
197 /* Microprocessor 5 Unit MCA type */
198 { SMCA_MP5, HWID_MCATYPE(0x01, 0x2) },
199
200 /* MPDMA MCA type */
201 { SMCA_MPDMA, HWID_MCATYPE(0x01, 0x3) },
202
203 /* Northbridge IO Unit MCA type */
204 { SMCA_NBIO, HWID_MCATYPE(0x18, 0x0) },
205
206 /* PCI Express Unit MCA type */
207 { SMCA_PCIE, HWID_MCATYPE(0x46, 0x0) },
208 { SMCA_PCIE_V2, HWID_MCATYPE(0x46, 0x1) },
209
210 { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0) },
211 { SMCA_NBIF, HWID_MCATYPE(0x6C, 0x0) },
212 { SMCA_SHUB, HWID_MCATYPE(0x80, 0x0) },
213 { SMCA_SATA, HWID_MCATYPE(0xA8, 0x0) },
214 { SMCA_USB, HWID_MCATYPE(0xAA, 0x0) },
215 { SMCA_GMI_PCS, HWID_MCATYPE(0x241, 0x0) },
216 { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0) },
217 { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0) },
218 { SMCA_GMI_PHY, HWID_MCATYPE(0x269, 0x0) },
219 };
220
221 /*
222 * In SMCA enabled processors, we can have multiple banks for a given IP type.
223 * So to define a unique name for each bank, we use a temp c-string to append
224 * the MCA_IPID[InstanceId] to type's name in get_name().
225 *
226 * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
227 * is greater than 8 plus 1 (for underscore) plus length of longest type name.
228 */
229 #define MAX_MCATYPE_NAME_LEN 30
230 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
231
232 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
233
234 /*
235 * A list of the banks enabled on each logical CPU. Controls which respective
236 * descriptors to initialize later in mce_threshold_create_device().
237 */
238 static DEFINE_PER_CPU(u64, bank_map);
239
240 /* Map of banks that have more than MCA_MISC0 available. */
241 static DEFINE_PER_CPU(u64, smca_misc_banks_map);
242
243 static void amd_threshold_interrupt(void);
244 static void amd_deferred_error_interrupt(void);
245
default_deferred_error_interrupt(void)246 static void default_deferred_error_interrupt(void)
247 {
248 pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
249 }
250 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
251
smca_set_misc_banks_map(unsigned int bank,unsigned int cpu)252 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)
253 {
254 u32 low, high;
255
256 /*
257 * For SMCA enabled processors, BLKPTR field of the first MISC register
258 * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
259 */
260 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
261 return;
262
263 if (!(low & MCI_CONFIG_MCAX))
264 return;
265
266 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high))
267 return;
268
269 if (low & MASK_BLKPTR_LO)
270 per_cpu(smca_misc_banks_map, cpu) |= BIT_ULL(bank);
271
272 }
273
smca_configure(unsigned int bank,unsigned int cpu)274 static void smca_configure(unsigned int bank, unsigned int cpu)
275 {
276 u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
277 const struct smca_hwid *s_hwid;
278 unsigned int i, hwid_mcatype;
279 u32 high, low;
280 u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
281
282 /* Set appropriate bits in MCA_CONFIG */
283 if (!rdmsr_safe(smca_config, &low, &high)) {
284 /*
285 * OS is required to set the MCAX bit to acknowledge that it is
286 * now using the new MSR ranges and new registers under each
287 * bank. It also means that the OS will configure deferred
288 * errors in the new MCx_CONFIG register. If the bit is not set,
289 * uncorrectable errors will cause a system panic.
290 *
291 * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
292 */
293 high |= BIT(0);
294
295 /*
296 * SMCA sets the Deferred Error Interrupt type per bank.
297 *
298 * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
299 * if the DeferredIntType bit field is available.
300 *
301 * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
302 * high portion of the MSR). OS should set this to 0x1 to enable
303 * APIC based interrupt. First, check that no interrupt has been
304 * set.
305 */
306 if ((low & BIT(5)) && !((high >> 5) & 0x3))
307 high |= BIT(5);
308
309 this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8));
310
311 wrmsr(smca_config, low, high);
312 }
313
314 smca_set_misc_banks_map(bank, cpu);
315
316 if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
317 pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
318 return;
319 }
320
321 hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
322 (high & MCI_IPID_MCATYPE) >> 16);
323
324 for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
325 s_hwid = &smca_hwid_mcatypes[i];
326
327 if (hwid_mcatype == s_hwid->hwid_mcatype) {
328 this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
329 this_cpu_ptr(smca_banks)[bank].id = low;
330 this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
331 break;
332 }
333 }
334 }
335
336 struct thresh_restart {
337 struct threshold_block *b;
338 int set_lvt_off;
339 int lvt_off;
340 u16 old_limit;
341 };
342
is_shared_bank(int bank)343 static inline bool is_shared_bank(int bank)
344 {
345 /*
346 * Scalable MCA provides for only one core to have access to the MSRs of
347 * a shared bank.
348 */
349 if (mce_flags.smca)
350 return false;
351
352 /* Bank 4 is for northbridge reporting and is thus shared */
353 return (bank == 4);
354 }
355
bank4_names(const struct threshold_block * b)356 static const char *bank4_names(const struct threshold_block *b)
357 {
358 switch (b->address) {
359 /* MSR4_MISC0 */
360 case 0x00000413:
361 return "dram";
362
363 case 0xc0000408:
364 return "ht_links";
365
366 case 0xc0000409:
367 return "l3_cache";
368
369 default:
370 WARN(1, "Funny MSR: 0x%08x\n", b->address);
371 return "";
372 }
373 };
374
375
lvt_interrupt_supported(unsigned int bank,u32 msr_high_bits)376 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
377 {
378 /*
379 * bank 4 supports APIC LVT interrupts implicitly since forever.
380 */
381 if (bank == 4)
382 return true;
383
384 /*
385 * IntP: interrupt present; if this bit is set, the thresholding
386 * bank can generate APIC LVT interrupts
387 */
388 return msr_high_bits & BIT(28);
389 }
390
lvt_off_valid(struct threshold_block * b,int apic,u32 lo,u32 hi)391 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
392 {
393 int msr = (hi & MASK_LVTOFF_HI) >> 20;
394
395 if (apic < 0) {
396 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
397 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
398 b->bank, b->block, b->address, hi, lo);
399 return 0;
400 }
401
402 if (apic != msr) {
403 /*
404 * On SMCA CPUs, LVT offset is programmed at a different MSR, and
405 * the BIOS provides the value. The original field where LVT offset
406 * was set is reserved. Return early here:
407 */
408 if (mce_flags.smca)
409 return 0;
410
411 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
412 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
413 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
414 return 0;
415 }
416
417 return 1;
418 };
419
420 /* Reprogram MCx_MISC MSR behind this threshold bank. */
threshold_restart_bank(void * _tr)421 static void threshold_restart_bank(void *_tr)
422 {
423 struct thresh_restart *tr = _tr;
424 u32 hi, lo;
425
426 /* sysfs write might race against an offline operation */
427 if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
428 return;
429
430 rdmsr(tr->b->address, lo, hi);
431
432 /*
433 * Reset error count and overflow bit.
434 * This is done during init or after handling an interrupt.
435 */
436 if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) {
437 hi &= ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI);
438 hi |= THRESHOLD_MAX - tr->b->threshold_limit;
439 } else if (tr->old_limit) { /* change limit w/o reset */
440 int new_count = (hi & THRESHOLD_MAX) +
441 (tr->old_limit - tr->b->threshold_limit);
442
443 hi = (hi & ~MASK_ERR_COUNT_HI) |
444 (new_count & THRESHOLD_MAX);
445 }
446
447 /* clear IntType */
448 hi &= ~MASK_INT_TYPE_HI;
449
450 if (!tr->b->interrupt_capable)
451 goto done;
452
453 if (tr->set_lvt_off) {
454 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
455 /* set new lvt offset */
456 hi &= ~MASK_LVTOFF_HI;
457 hi |= tr->lvt_off << 20;
458 }
459 }
460
461 if (tr->b->interrupt_enable)
462 hi |= INT_TYPE_APIC;
463
464 done:
465
466 hi |= MASK_COUNT_EN_HI;
467 wrmsr(tr->b->address, lo, hi);
468 }
469
mce_threshold_block_init(struct threshold_block * b,int offset)470 static void mce_threshold_block_init(struct threshold_block *b, int offset)
471 {
472 struct thresh_restart tr = {
473 .b = b,
474 .set_lvt_off = 1,
475 .lvt_off = offset,
476 };
477
478 b->threshold_limit = THRESHOLD_MAX;
479 threshold_restart_bank(&tr);
480 };
481
setup_APIC_mce_threshold(int reserved,int new)482 static int setup_APIC_mce_threshold(int reserved, int new)
483 {
484 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
485 APIC_EILVT_MSG_FIX, 0))
486 return new;
487
488 return reserved;
489 }
490
setup_APIC_deferred_error(int reserved,int new)491 static int setup_APIC_deferred_error(int reserved, int new)
492 {
493 if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
494 APIC_EILVT_MSG_FIX, 0))
495 return new;
496
497 return reserved;
498 }
499
deferred_error_interrupt_enable(struct cpuinfo_x86 * c)500 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
501 {
502 u32 low = 0, high = 0;
503 int def_offset = -1, def_new;
504
505 if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
506 return;
507
508 def_new = (low & MASK_DEF_LVTOFF) >> 4;
509 if (!(low & MASK_DEF_LVTOFF)) {
510 pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
511 def_new = DEF_LVT_OFF;
512 low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
513 }
514
515 def_offset = setup_APIC_deferred_error(def_offset, def_new);
516 if ((def_offset == def_new) &&
517 (deferred_error_int_vector != amd_deferred_error_interrupt))
518 deferred_error_int_vector = amd_deferred_error_interrupt;
519
520 if (!mce_flags.smca)
521 low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
522
523 wrmsr(MSR_CU_DEF_ERR, low, high);
524 }
525
smca_get_block_address(unsigned int bank,unsigned int block,unsigned int cpu)526 static u32 smca_get_block_address(unsigned int bank, unsigned int block,
527 unsigned int cpu)
528 {
529 if (!block)
530 return MSR_AMD64_SMCA_MCx_MISC(bank);
531
532 if (!(per_cpu(smca_misc_banks_map, cpu) & BIT_ULL(bank)))
533 return 0;
534
535 return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
536 }
537
get_block_address(u32 current_addr,u32 low,u32 high,unsigned int bank,unsigned int block,unsigned int cpu)538 static u32 get_block_address(u32 current_addr, u32 low, u32 high,
539 unsigned int bank, unsigned int block,
540 unsigned int cpu)
541 {
542 u32 addr = 0, offset = 0;
543
544 if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
545 return addr;
546
547 if (mce_flags.smca)
548 return smca_get_block_address(bank, block, cpu);
549
550 /* Fall back to method we used for older processors: */
551 switch (block) {
552 case 0:
553 addr = mca_msr_reg(bank, MCA_MISC);
554 break;
555 case 1:
556 offset = ((low & MASK_BLKPTR_LO) >> 21);
557 if (offset)
558 addr = MCG_XBLK_ADDR + offset;
559 break;
560 default:
561 addr = ++current_addr;
562 }
563 return addr;
564 }
565
566 static int
prepare_threshold_block(unsigned int bank,unsigned int block,u32 addr,int offset,u32 misc_high)567 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
568 int offset, u32 misc_high)
569 {
570 unsigned int cpu = smp_processor_id();
571 u32 smca_low, smca_high;
572 struct threshold_block b;
573 int new;
574
575 if (!block)
576 per_cpu(bank_map, cpu) |= BIT_ULL(bank);
577
578 memset(&b, 0, sizeof(b));
579 b.cpu = cpu;
580 b.bank = bank;
581 b.block = block;
582 b.address = addr;
583 b.interrupt_capable = lvt_interrupt_supported(bank, misc_high);
584
585 if (!b.interrupt_capable)
586 goto done;
587
588 b.interrupt_enable = 1;
589
590 if (!mce_flags.smca) {
591 new = (misc_high & MASK_LVTOFF_HI) >> 20;
592 goto set_offset;
593 }
594
595 /* Gather LVT offset for thresholding: */
596 if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
597 goto out;
598
599 new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
600
601 set_offset:
602 offset = setup_APIC_mce_threshold(offset, new);
603 if (offset == new)
604 thresholding_irq_en = true;
605
606 done:
607 mce_threshold_block_init(&b, offset);
608
609 out:
610 return offset;
611 }
612
amd_filter_mce(struct mce * m)613 bool amd_filter_mce(struct mce *m)
614 {
615 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);
616 struct cpuinfo_x86 *c = &boot_cpu_data;
617
618 /* See Family 17h Models 10h-2Fh Erratum #1114. */
619 if (c->x86 == 0x17 &&
620 c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
621 bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)
622 return true;
623
624 /* NB GART TLB error reporting is disabled by default. */
625 if (c->x86 < 0x17) {
626 if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)
627 return true;
628 }
629
630 return false;
631 }
632
633 /*
634 * Turn off thresholding banks for the following conditions:
635 * - MC4_MISC thresholding is not supported on Family 0x15.
636 * - Prevent possible spurious interrupts from the IF bank on Family 0x17
637 * Models 0x10-0x2F due to Erratum #1114.
638 */
disable_err_thresholding(struct cpuinfo_x86 * c,unsigned int bank)639 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
640 {
641 int i, num_msrs;
642 u64 hwcr;
643 bool need_toggle;
644 u32 msrs[NR_BLOCKS];
645
646 if (c->x86 == 0x15 && bank == 4) {
647 msrs[0] = 0x00000413; /* MC4_MISC0 */
648 msrs[1] = 0xc0000408; /* MC4_MISC1 */
649 num_msrs = 2;
650 } else if (c->x86 == 0x17 &&
651 (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
652
653 if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF)
654 return;
655
656 msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
657 num_msrs = 1;
658 } else {
659 return;
660 }
661
662 rdmsrl(MSR_K7_HWCR, hwcr);
663
664 /* McStatusWrEn has to be set */
665 need_toggle = !(hwcr & BIT(18));
666 if (need_toggle)
667 wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
668
669 /* Clear CntP bit safely */
670 for (i = 0; i < num_msrs; i++)
671 msr_clear_bit(msrs[i], 62);
672
673 /* restore old settings */
674 if (need_toggle)
675 wrmsrl(MSR_K7_HWCR, hwcr);
676 }
677
678 /* cpu init entry point, called from mce.c with preempt off */
mce_amd_feature_init(struct cpuinfo_x86 * c)679 void mce_amd_feature_init(struct cpuinfo_x86 *c)
680 {
681 unsigned int bank, block, cpu = smp_processor_id();
682 u32 low = 0, high = 0, address = 0;
683 int offset = -1;
684
685
686 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
687 if (mce_flags.smca)
688 smca_configure(bank, cpu);
689
690 disable_err_thresholding(c, bank);
691
692 for (block = 0; block < NR_BLOCKS; ++block) {
693 address = get_block_address(address, low, high, bank, block, cpu);
694 if (!address)
695 break;
696
697 if (rdmsr_safe(address, &low, &high))
698 break;
699
700 if (!(high & MASK_VALID_HI))
701 continue;
702
703 if (!(high & MASK_CNTP_HI) ||
704 (high & MASK_LOCKED_HI))
705 continue;
706
707 offset = prepare_threshold_block(bank, block, address, offset, high);
708 }
709 }
710
711 if (mce_flags.succor)
712 deferred_error_interrupt_enable(c);
713 }
714
amd_mce_is_memory_error(struct mce * m)715 bool amd_mce_is_memory_error(struct mce *m)
716 {
717 enum smca_bank_types bank_type;
718 /* ErrCodeExt[20:16] */
719 u8 xec = (m->status >> 16) & 0x1f;
720
721 bank_type = smca_get_bank_type(m->extcpu, m->bank);
722 if (mce_flags.smca)
723 return (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2) && xec == 0x0;
724
725 return m->bank == 4 && xec == 0x8;
726 }
727
__log_error(unsigned int bank,u64 status,u64 addr,u64 misc)728 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
729 {
730 struct mce m;
731
732 mce_setup(&m);
733
734 m.status = status;
735 m.misc = misc;
736 m.bank = bank;
737 m.tsc = rdtsc();
738
739 if (m.status & MCI_STATUS_ADDRV) {
740 m.addr = addr;
741
742 smca_extract_err_addr(&m);
743 }
744
745 if (mce_flags.smca) {
746 rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
747
748 if (m.status & MCI_STATUS_SYNDV)
749 rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
750 }
751
752 mce_log(&m);
753 }
754
DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)755 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)
756 {
757 trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
758 inc_irq_stat(irq_deferred_error_count);
759 deferred_error_int_vector();
760 trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
761 apic_eoi();
762 }
763
764 /*
765 * Returns true if the logged error is deferred. False, otherwise.
766 */
767 static inline bool
_log_error_bank(unsigned int bank,u32 msr_stat,u32 msr_addr,u64 misc)768 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
769 {
770 u64 status, addr = 0;
771
772 rdmsrl(msr_stat, status);
773 if (!(status & MCI_STATUS_VAL))
774 return false;
775
776 if (status & MCI_STATUS_ADDRV)
777 rdmsrl(msr_addr, addr);
778
779 __log_error(bank, status, addr, misc);
780
781 wrmsrl(msr_stat, 0);
782
783 return status & MCI_STATUS_DEFERRED;
784 }
785
_log_error_deferred(unsigned int bank,u32 misc)786 static bool _log_error_deferred(unsigned int bank, u32 misc)
787 {
788 if (!_log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
789 mca_msr_reg(bank, MCA_ADDR), misc))
790 return false;
791
792 /*
793 * Non-SMCA systems don't have MCA_DESTAT/MCA_DEADDR registers.
794 * Return true here to avoid accessing these registers.
795 */
796 if (!mce_flags.smca)
797 return true;
798
799 /* Clear MCA_DESTAT if the deferred error was logged from MCA_STATUS. */
800 wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
801 return true;
802 }
803
804 /*
805 * We have three scenarios for checking for Deferred errors:
806 *
807 * 1) Non-SMCA systems check MCA_STATUS and log error if found.
808 * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
809 * clear MCA_DESTAT.
810 * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
811 * log it.
812 */
log_error_deferred(unsigned int bank)813 static void log_error_deferred(unsigned int bank)
814 {
815 if (_log_error_deferred(bank, 0))
816 return;
817
818 /*
819 * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
820 * for a valid error.
821 */
822 _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
823 MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
824 }
825
826 /* APIC interrupt handler for deferred errors */
amd_deferred_error_interrupt(void)827 static void amd_deferred_error_interrupt(void)
828 {
829 unsigned int bank;
830
831 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)
832 log_error_deferred(bank);
833 }
834
log_error_thresholding(unsigned int bank,u64 misc)835 static void log_error_thresholding(unsigned int bank, u64 misc)
836 {
837 _log_error_deferred(bank, misc);
838 }
839
log_and_reset_block(struct threshold_block * block)840 static void log_and_reset_block(struct threshold_block *block)
841 {
842 struct thresh_restart tr;
843 u32 low = 0, high = 0;
844
845 if (!block)
846 return;
847
848 if (rdmsr_safe(block->address, &low, &high))
849 return;
850
851 if (!(high & MASK_OVERFLOW_HI))
852 return;
853
854 /* Log the MCE which caused the threshold event. */
855 log_error_thresholding(block->bank, ((u64)high << 32) | low);
856
857 /* Reset threshold block after logging error. */
858 memset(&tr, 0, sizeof(tr));
859 tr.b = block;
860 threshold_restart_bank(&tr);
861 }
862
863 /*
864 * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
865 * goes off when error_count reaches threshold_limit.
866 */
amd_threshold_interrupt(void)867 static void amd_threshold_interrupt(void)
868 {
869 struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
870 struct threshold_bank **bp = this_cpu_read(threshold_banks);
871 unsigned int bank, cpu = smp_processor_id();
872
873 /*
874 * Validate that the threshold bank has been initialized already. The
875 * handler is installed at boot time, but on a hotplug event the
876 * interrupt might fire before the data has been initialized.
877 */
878 if (!bp)
879 return;
880
881 for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
882 if (!(per_cpu(bank_map, cpu) & BIT_ULL(bank)))
883 continue;
884
885 first_block = bp[bank]->blocks;
886 if (!first_block)
887 continue;
888
889 /*
890 * The first block is also the head of the list. Check it first
891 * before iterating over the rest.
892 */
893 log_and_reset_block(first_block);
894 list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
895 log_and_reset_block(block);
896 }
897 }
898
899 /*
900 * Sysfs Interface
901 */
902
903 struct threshold_attr {
904 struct attribute attr;
905 ssize_t (*show) (struct threshold_block *, char *);
906 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
907 };
908
909 #define SHOW_FIELDS(name) \
910 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
911 { \
912 return sprintf(buf, "%lu\n", (unsigned long) b->name); \
913 }
914 SHOW_FIELDS(interrupt_enable)
SHOW_FIELDS(threshold_limit)915 SHOW_FIELDS(threshold_limit)
916
917 static ssize_t
918 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
919 {
920 struct thresh_restart tr;
921 unsigned long new;
922
923 if (!b->interrupt_capable)
924 return -EINVAL;
925
926 if (kstrtoul(buf, 0, &new) < 0)
927 return -EINVAL;
928
929 b->interrupt_enable = !!new;
930
931 memset(&tr, 0, sizeof(tr));
932 tr.b = b;
933
934 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
935 return -ENODEV;
936
937 return size;
938 }
939
940 static ssize_t
store_threshold_limit(struct threshold_block * b,const char * buf,size_t size)941 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
942 {
943 struct thresh_restart tr;
944 unsigned long new;
945
946 if (kstrtoul(buf, 0, &new) < 0)
947 return -EINVAL;
948
949 if (new > THRESHOLD_MAX)
950 new = THRESHOLD_MAX;
951 if (new < 1)
952 new = 1;
953
954 memset(&tr, 0, sizeof(tr));
955 tr.old_limit = b->threshold_limit;
956 b->threshold_limit = new;
957 tr.b = b;
958
959 if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
960 return -ENODEV;
961
962 return size;
963 }
964
show_error_count(struct threshold_block * b,char * buf)965 static ssize_t show_error_count(struct threshold_block *b, char *buf)
966 {
967 u32 lo, hi;
968
969 /* CPU might be offline by now */
970 if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi))
971 return -ENODEV;
972
973 return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
974 (THRESHOLD_MAX - b->threshold_limit)));
975 }
976
977 static struct threshold_attr error_count = {
978 .attr = {.name = __stringify(error_count), .mode = 0444 },
979 .show = show_error_count,
980 };
981
982 #define RW_ATTR(val) \
983 static struct threshold_attr val = { \
984 .attr = {.name = __stringify(val), .mode = 0644 }, \
985 .show = show_## val, \
986 .store = store_## val, \
987 };
988
989 RW_ATTR(interrupt_enable);
990 RW_ATTR(threshold_limit);
991
992 static struct attribute *default_attrs[] = {
993 &threshold_limit.attr,
994 &error_count.attr,
995 NULL, /* possibly interrupt_enable if supported, see below */
996 NULL,
997 };
998 ATTRIBUTE_GROUPS(default);
999
1000 #define to_block(k) container_of(k, struct threshold_block, kobj)
1001 #define to_attr(a) container_of(a, struct threshold_attr, attr)
1002
show(struct kobject * kobj,struct attribute * attr,char * buf)1003 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1004 {
1005 struct threshold_block *b = to_block(kobj);
1006 struct threshold_attr *a = to_attr(attr);
1007 ssize_t ret;
1008
1009 ret = a->show ? a->show(b, buf) : -EIO;
1010
1011 return ret;
1012 }
1013
store(struct kobject * kobj,struct attribute * attr,const char * buf,size_t count)1014 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1015 const char *buf, size_t count)
1016 {
1017 struct threshold_block *b = to_block(kobj);
1018 struct threshold_attr *a = to_attr(attr);
1019 ssize_t ret;
1020
1021 ret = a->store ? a->store(b, buf, count) : -EIO;
1022
1023 return ret;
1024 }
1025
1026 static const struct sysfs_ops threshold_ops = {
1027 .show = show,
1028 .store = store,
1029 };
1030
1031 static void threshold_block_release(struct kobject *kobj);
1032
1033 static const struct kobj_type threshold_ktype = {
1034 .sysfs_ops = &threshold_ops,
1035 .default_groups = default_groups,
1036 .release = threshold_block_release,
1037 };
1038
get_name(unsigned int cpu,unsigned int bank,struct threshold_block * b)1039 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b)
1040 {
1041 enum smca_bank_types bank_type;
1042
1043 if (!mce_flags.smca) {
1044 if (b && bank == 4)
1045 return bank4_names(b);
1046
1047 return th_names[bank];
1048 }
1049
1050 bank_type = smca_get_bank_type(cpu, bank);
1051
1052 if (b && (bank_type == SMCA_UMC || bank_type == SMCA_UMC_V2)) {
1053 if (b->block < ARRAY_SIZE(smca_umc_block_names))
1054 return smca_umc_block_names[b->block];
1055 }
1056
1057 if (b && b->block) {
1058 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_block_%u", b->block);
1059 return buf_mcatype;
1060 }
1061
1062 if (bank_type >= N_SMCA_BANK_TYPES) {
1063 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN, "th_bank_%u", bank);
1064 return buf_mcatype;
1065 }
1066
1067 if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1)
1068 return smca_get_name(bank_type);
1069
1070 snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1071 "%s_%u", smca_get_name(bank_type),
1072 per_cpu(smca_banks, cpu)[bank].sysfs_id);
1073 return buf_mcatype;
1074 }
1075
allocate_threshold_blocks(unsigned int cpu,struct threshold_bank * tb,unsigned int bank,unsigned int block,u32 address)1076 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb,
1077 unsigned int bank, unsigned int block,
1078 u32 address)
1079 {
1080 struct threshold_block *b = NULL;
1081 u32 low, high;
1082 int err;
1083
1084 if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
1085 return 0;
1086
1087 if (rdmsr_safe(address, &low, &high))
1088 return 0;
1089
1090 if (!(high & MASK_VALID_HI)) {
1091 if (block)
1092 goto recurse;
1093 else
1094 return 0;
1095 }
1096
1097 if (!(high & MASK_CNTP_HI) ||
1098 (high & MASK_LOCKED_HI))
1099 goto recurse;
1100
1101 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1102 if (!b)
1103 return -ENOMEM;
1104
1105 b->block = block;
1106 b->bank = bank;
1107 b->cpu = cpu;
1108 b->address = address;
1109 b->interrupt_enable = 0;
1110 b->interrupt_capable = lvt_interrupt_supported(bank, high);
1111 b->threshold_limit = THRESHOLD_MAX;
1112
1113 if (b->interrupt_capable) {
1114 default_attrs[2] = &interrupt_enable.attr;
1115 b->interrupt_enable = 1;
1116 } else {
1117 default_attrs[2] = NULL;
1118 }
1119
1120 INIT_LIST_HEAD(&b->miscj);
1121
1122 /* This is safe as @tb is not visible yet */
1123 if (tb->blocks)
1124 list_add(&b->miscj, &tb->blocks->miscj);
1125 else
1126 tb->blocks = b;
1127
1128 err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
1129 if (err)
1130 goto out_free;
1131 recurse:
1132 address = get_block_address(address, low, high, bank, ++block, cpu);
1133 if (!address)
1134 return 0;
1135
1136 err = allocate_threshold_blocks(cpu, tb, bank, block, address);
1137 if (err)
1138 goto out_free;
1139
1140 if (b)
1141 kobject_uevent(&b->kobj, KOBJ_ADD);
1142
1143 return 0;
1144
1145 out_free:
1146 if (b) {
1147 list_del(&b->miscj);
1148 kobject_put(&b->kobj);
1149 }
1150 return err;
1151 }
1152
__threshold_add_blocks(struct threshold_bank * b)1153 static int __threshold_add_blocks(struct threshold_bank *b)
1154 {
1155 struct list_head *head = &b->blocks->miscj;
1156 struct threshold_block *pos = NULL;
1157 struct threshold_block *tmp = NULL;
1158 int err = 0;
1159
1160 err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1161 if (err)
1162 return err;
1163
1164 list_for_each_entry_safe(pos, tmp, head, miscj) {
1165
1166 err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1167 if (err) {
1168 list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1169 kobject_del(&pos->kobj);
1170
1171 return err;
1172 }
1173 }
1174 return err;
1175 }
1176
threshold_create_bank(struct threshold_bank ** bp,unsigned int cpu,unsigned int bank)1177 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
1178 unsigned int bank)
1179 {
1180 struct device *dev = this_cpu_read(mce_device);
1181 struct amd_northbridge *nb = NULL;
1182 struct threshold_bank *b = NULL;
1183 const char *name = get_name(cpu, bank, NULL);
1184 int err = 0;
1185
1186 if (!dev)
1187 return -ENODEV;
1188
1189 if (is_shared_bank(bank)) {
1190 nb = node_to_amd_nb(topology_die_id(cpu));
1191
1192 /* threshold descriptor already initialized on this node? */
1193 if (nb && nb->bank4) {
1194 /* yes, use it */
1195 b = nb->bank4;
1196 err = kobject_add(b->kobj, &dev->kobj, name);
1197 if (err)
1198 goto out;
1199
1200 bp[bank] = b;
1201 refcount_inc(&b->cpus);
1202
1203 err = __threshold_add_blocks(b);
1204
1205 goto out;
1206 }
1207 }
1208
1209 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1210 if (!b) {
1211 err = -ENOMEM;
1212 goto out;
1213 }
1214
1215 /* Associate the bank with the per-CPU MCE device */
1216 b->kobj = kobject_create_and_add(name, &dev->kobj);
1217 if (!b->kobj) {
1218 err = -EINVAL;
1219 goto out_free;
1220 }
1221
1222 if (is_shared_bank(bank)) {
1223 b->shared = 1;
1224 refcount_set(&b->cpus, 1);
1225
1226 /* nb is already initialized, see above */
1227 if (nb) {
1228 WARN_ON(nb->bank4);
1229 nb->bank4 = b;
1230 }
1231 }
1232
1233 err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));
1234 if (err)
1235 goto out_kobj;
1236
1237 bp[bank] = b;
1238 return 0;
1239
1240 out_kobj:
1241 kobject_put(b->kobj);
1242 out_free:
1243 kfree(b);
1244 out:
1245 return err;
1246 }
1247
threshold_block_release(struct kobject * kobj)1248 static void threshold_block_release(struct kobject *kobj)
1249 {
1250 kfree(to_block(kobj));
1251 }
1252
deallocate_threshold_blocks(struct threshold_bank * bank)1253 static void deallocate_threshold_blocks(struct threshold_bank *bank)
1254 {
1255 struct threshold_block *pos, *tmp;
1256
1257 list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) {
1258 list_del(&pos->miscj);
1259 kobject_put(&pos->kobj);
1260 }
1261
1262 kobject_put(&bank->blocks->kobj);
1263 }
1264
__threshold_remove_blocks(struct threshold_bank * b)1265 static void __threshold_remove_blocks(struct threshold_bank *b)
1266 {
1267 struct threshold_block *pos = NULL;
1268 struct threshold_block *tmp = NULL;
1269
1270 kobject_put(b->kobj);
1271
1272 list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1273 kobject_put(b->kobj);
1274 }
1275
threshold_remove_bank(struct threshold_bank * bank)1276 static void threshold_remove_bank(struct threshold_bank *bank)
1277 {
1278 struct amd_northbridge *nb;
1279
1280 if (!bank->blocks)
1281 goto out_free;
1282
1283 if (!bank->shared)
1284 goto out_dealloc;
1285
1286 if (!refcount_dec_and_test(&bank->cpus)) {
1287 __threshold_remove_blocks(bank);
1288 return;
1289 } else {
1290 /*
1291 * The last CPU on this node using the shared bank is going
1292 * away, remove that bank now.
1293 */
1294 nb = node_to_amd_nb(topology_die_id(smp_processor_id()));
1295 nb->bank4 = NULL;
1296 }
1297
1298 out_dealloc:
1299 deallocate_threshold_blocks(bank);
1300
1301 out_free:
1302 kobject_put(bank->kobj);
1303 kfree(bank);
1304 }
1305
__threshold_remove_device(struct threshold_bank ** bp)1306 static void __threshold_remove_device(struct threshold_bank **bp)
1307 {
1308 unsigned int bank, numbanks = this_cpu_read(mce_num_banks);
1309
1310 for (bank = 0; bank < numbanks; bank++) {
1311 if (!bp[bank])
1312 continue;
1313
1314 threshold_remove_bank(bp[bank]);
1315 bp[bank] = NULL;
1316 }
1317 kfree(bp);
1318 }
1319
mce_threshold_remove_device(unsigned int cpu)1320 int mce_threshold_remove_device(unsigned int cpu)
1321 {
1322 struct threshold_bank **bp = this_cpu_read(threshold_banks);
1323
1324 if (!bp)
1325 return 0;
1326
1327 /*
1328 * Clear the pointer before cleaning up, so that the interrupt won't
1329 * touch anything of this.
1330 */
1331 this_cpu_write(threshold_banks, NULL);
1332
1333 __threshold_remove_device(bp);
1334 return 0;
1335 }
1336
1337 /**
1338 * mce_threshold_create_device - Create the per-CPU MCE threshold device
1339 * @cpu: The plugged in CPU
1340 *
1341 * Create directories and files for all valid threshold banks.
1342 *
1343 * This is invoked from the CPU hotplug callback which was installed in
1344 * mcheck_init_device(). The invocation happens in context of the hotplug
1345 * thread running on @cpu. The callback is invoked on all CPUs which are
1346 * online when the callback is installed or during a real hotplug event.
1347 */
mce_threshold_create_device(unsigned int cpu)1348 int mce_threshold_create_device(unsigned int cpu)
1349 {
1350 unsigned int numbanks, bank;
1351 struct threshold_bank **bp;
1352 int err;
1353
1354 if (!mce_flags.amd_threshold)
1355 return 0;
1356
1357 bp = this_cpu_read(threshold_banks);
1358 if (bp)
1359 return 0;
1360
1361 numbanks = this_cpu_read(mce_num_banks);
1362 bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL);
1363 if (!bp)
1364 return -ENOMEM;
1365
1366 for (bank = 0; bank < numbanks; ++bank) {
1367 if (!(this_cpu_read(bank_map) & BIT_ULL(bank)))
1368 continue;
1369 err = threshold_create_bank(bp, cpu, bank);
1370 if (err) {
1371 __threshold_remove_device(bp);
1372 return err;
1373 }
1374 }
1375 this_cpu_write(threshold_banks, bp);
1376
1377 if (thresholding_irq_en)
1378 mce_threshold_vector = amd_threshold_interrupt;
1379 return 0;
1380 }
1381