xref: /openbmc/linux/sound/soc/codecs/max98390.c (revision 9abcd240)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * max98390.c  --  MAX98390 ALSA Soc Audio driver
4  *
5  * Copyright (C) 2020 Maxim Integrated Products
6  *
7  */
8 
9 #include <linux/acpi.h>
10 #include <linux/cdev.h>
11 #include <linux/dmi.h>
12 #include <linux/firmware.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/of_gpio.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <linux/time.h>
20 #include <sound/pcm.h>
21 #include <sound/pcm_params.h>
22 #include <sound/soc.h>
23 #include <sound/tlv.h>
24 
25 #include "max98390.h"
26 
27 static struct reg_default max98390_reg_defaults[] = {
28 	{MAX98390_INT_EN1, 0xf0},
29 	{MAX98390_INT_EN2, 0x00},
30 	{MAX98390_INT_EN3, 0x00},
31 	{MAX98390_INT_FLAG_CLR1, 0x00},
32 	{MAX98390_INT_FLAG_CLR2, 0x00},
33 	{MAX98390_INT_FLAG_CLR3, 0x00},
34 	{MAX98390_IRQ_CTRL, 0x01},
35 	{MAX98390_CLK_MON, 0x6d},
36 	{MAX98390_DAT_MON, 0x03},
37 	{MAX98390_WDOG_CTRL, 0x00},
38 	{MAX98390_WDOG_RST, 0x00},
39 	{MAX98390_MEAS_ADC_THERM_WARN_THRESH, 0x75},
40 	{MAX98390_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
41 	{MAX98390_MEAS_ADC_THERM_HYSTERESIS, 0x08},
42 	{MAX98390_PIN_CFG, 0x55},
43 	{MAX98390_PCM_RX_EN_A, 0x00},
44 	{MAX98390_PCM_RX_EN_B, 0x00},
45 	{MAX98390_PCM_TX_EN_A, 0x00},
46 	{MAX98390_PCM_TX_EN_B, 0x00},
47 	{MAX98390_PCM_TX_HIZ_CTRL_A, 0xff},
48 	{MAX98390_PCM_TX_HIZ_CTRL_B, 0xff},
49 	{MAX98390_PCM_CH_SRC_1, 0x00},
50 	{MAX98390_PCM_CH_SRC_2, 0x00},
51 	{MAX98390_PCM_CH_SRC_3, 0x00},
52 	{MAX98390_PCM_MODE_CFG, 0xc0},
53 	{MAX98390_PCM_MASTER_MODE, 0x1c},
54 	{MAX98390_PCM_CLK_SETUP, 0x44},
55 	{MAX98390_PCM_SR_SETUP, 0x08},
56 	{MAX98390_ICC_RX_EN_A, 0x00},
57 	{MAX98390_ICC_RX_EN_B, 0x00},
58 	{MAX98390_ICC_TX_EN_A, 0x00},
59 	{MAX98390_ICC_TX_EN_B, 0x00},
60 	{MAX98390_ICC_HIZ_MANUAL_MODE, 0x00},
61 	{MAX98390_ICC_TX_HIZ_EN_A, 0x00},
62 	{MAX98390_ICC_TX_HIZ_EN_B, 0x00},
63 	{MAX98390_ICC_LNK_EN, 0x00},
64 	{MAX98390_R2039_AMP_DSP_CFG, 0x0f},
65 	{MAX98390_R203A_AMP_EN, 0x81},
66 	{MAX98390_TONE_GEN_DC_CFG, 0x00},
67 	{MAX98390_SPK_SRC_SEL, 0x00},
68 	{MAX98390_SSM_CFG, 0x85},
69 	{MAX98390_MEAS_EN, 0x03},
70 	{MAX98390_MEAS_DSP_CFG, 0x0f},
71 	{MAX98390_BOOST_CTRL0, 0x1c},
72 	{MAX98390_BOOST_CTRL3, 0x01},
73 	{MAX98390_BOOST_CTRL1, 0x40},
74 	{MAX98390_MEAS_ADC_CFG, 0x07},
75 	{MAX98390_MEAS_ADC_BASE_MSB, 0x00},
76 	{MAX98390_MEAS_ADC_BASE_LSB, 0x23},
77 	{MAX98390_ADC_CH0_DIVIDE, 0x00},
78 	{MAX98390_ADC_CH1_DIVIDE, 0x00},
79 	{MAX98390_ADC_CH2_DIVIDE, 0x00},
80 	{MAX98390_ADC_CH0_FILT_CFG, 0x00},
81 	{MAX98390_ADC_CH1_FILT_CFG, 0x00},
82 	{MAX98390_ADC_CH2_FILT_CFG, 0x00},
83 	{MAX98390_PWR_GATE_CTL, 0x2c},
84 	{MAX98390_BROWNOUT_EN, 0x00},
85 	{MAX98390_BROWNOUT_INFINITE_HOLD, 0x00},
86 	{MAX98390_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
87 	{MAX98390_BROWNOUT_LVL_HOLD, 0x00},
88 	{MAX98390_BROWNOUT_LVL1_THRESH, 0x00},
89 	{MAX98390_BROWNOUT_LVL2_THRESH, 0x00},
90 	{MAX98390_BROWNOUT_LVL3_THRESH, 0x00},
91 	{MAX98390_BROWNOUT_LVL4_THRESH, 0x00},
92 	{MAX98390_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
93 	{MAX98390_BROWNOUT_AMP_LIMITER_ATK_REL, 0x1f},
94 	{MAX98390_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
95 	{MAX98390_BROWNOUT_AMP1_CLIP_MODE, 0x00},
96 	{MAX98390_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
97 	{MAX98390_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
98 	{MAX98390_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
99 	{MAX98390_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
100 	{MAX98390_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
101 	{MAX98390_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
102 	{MAX98390_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
103 	{MAX98390_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
104 	{MAX98390_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
105 	{MAX98390_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
106 	{MAX98390_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
107 	{MAX98390_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
108 	{MAX98390_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
109 	{MAX98390_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
110 	{MAX98390_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
111 	{MAX98390_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
112 	{MAX98390_BROWNOUT_ILIM_HLD, 0x00},
113 	{MAX98390_BROWNOUT_LIM_HLD, 0x00},
114 	{MAX98390_BROWNOUT_CLIP_HLD, 0x00},
115 	{MAX98390_BROWNOUT_GAIN_HLD, 0x00},
116 	{MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0f},
117 	{MAX98390_ENV_TRACK_BOOST_VOUT_DELAY, 0x80},
118 	{MAX98390_ENV_TRACK_REL_RATE, 0x07},
119 	{MAX98390_ENV_TRACK_HOLD_RATE, 0x07},
120 	{MAX98390_ENV_TRACK_CTRL, 0x01},
121 	{MAX98390_BOOST_BYPASS1, 0x49},
122 	{MAX98390_BOOST_BYPASS2, 0x2b},
123 	{MAX98390_BOOST_BYPASS3, 0x08},
124 	{MAX98390_FET_SCALING1, 0x00},
125 	{MAX98390_FET_SCALING2, 0x03},
126 	{MAX98390_FET_SCALING3, 0x00},
127 	{MAX98390_FET_SCALING4, 0x07},
128 	{MAX98390_SPK_SPEEDUP, 0x00},
129 	{DSMIG_WB_DRC_RELEASE_TIME_1, 0x00},
130 	{DSMIG_WB_DRC_RELEASE_TIME_2, 0x00},
131 	{DSMIG_WB_DRC_ATTACK_TIME_1, 0x00},
132 	{DSMIG_WB_DRC_ATTACK_TIME_2, 0x00},
133 	{DSMIG_WB_DRC_COMPRESSION_RATIO, 0x00},
134 	{DSMIG_WB_DRC_COMPRESSION_THRESHOLD, 0x00},
135 	{DSMIG_WB_DRC_MAKEUPGAIN, 0x00},
136 	{DSMIG_WB_DRC_NOISE_GATE_THRESHOLD, 0x00},
137 	{DSMIG_WBDRC_HPF_ENABLE, 0x00},
138 	{DSMIG_WB_DRC_TEST_SMOOTHER_OUT_EN, 0x00},
139 	{DSMIG_PPR_THRESHOLD, 0x00},
140 	{DSM_STEREO_BASS_CHANNEL_SELECT, 0x00},
141 	{DSM_TPROT_THRESHOLD_BYTE0, 0x00},
142 	{DSM_TPROT_THRESHOLD_BYTE1, 0x00},
143 	{DSM_TPROT_ROOM_TEMPERATURE_BYTE0, 0x00},
144 	{DSM_TPROT_ROOM_TEMPERATURE_BYTE1, 0x00},
145 	{DSM_TPROT_RECIP_RDC_ROOM_BYTE0, 0x00},
146 	{DSM_TPROT_RECIP_RDC_ROOM_BYTE1, 0x00},
147 	{DSM_TPROT_RECIP_RDC_ROOM_BYTE2, 0x00},
148 	{DSM_TPROT_RECIP_TCONST_BYTE0, 0x00},
149 	{DSM_TPROT_RECIP_TCONST_BYTE1, 0x00},
150 	{DSM_TPROT_RECIP_TCONST_BYTE2, 0x00},
151 	{DSM_THERMAL_ATTENUATION_SETTINGS, 0x00},
152 	{DSM_THERMAL_PILOT_TONE_ATTENUATION, 0x00},
153 	{DSM_TPROT_PG_TEMP_THRESH_BYTE0, 0x00},
154 	{DSM_TPROT_PG_TEMP_THRESH_BYTE1, 0x00},
155 	{DSMIG_DEBUZZER_THRESHOLD, 0x00},
156 	{DSMIG_DEBUZZER_ALPHA_COEF_TEST_ONLY, 0x08},
157 	{DSM_VOL_ENA, 0x20},
158 	{DSM_VOL_CTRL, 0xa0},
159 	{DSMIG_EN, 0x00},
160 	{MAX98390_R23E1_DSP_GLOBAL_EN, 0x00},
161 	{MAX98390_R23FF_GLOBAL_EN, 0x00},
162 };
163 
max98390_dai_set_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)164 static int max98390_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
165 {
166 	struct snd_soc_component *component = codec_dai->component;
167 	struct max98390_priv *max98390 =
168 		snd_soc_component_get_drvdata(component);
169 	unsigned int mode;
170 	unsigned int format;
171 	unsigned int invert = 0;
172 
173 	dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
174 
175 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
176 	case SND_SOC_DAIFMT_CBC_CFC:
177 		mode = MAX98390_PCM_MASTER_MODE_SLAVE;
178 		break;
179 	case SND_SOC_DAIFMT_CBP_CFP:
180 		max98390->provider = true;
181 		mode = MAX98390_PCM_MASTER_MODE_MASTER;
182 		break;
183 	default:
184 		dev_err(component->dev, "DAI clock mode unsupported\n");
185 		return -EINVAL;
186 	}
187 
188 	regmap_update_bits(max98390->regmap,
189 		MAX98390_PCM_MASTER_MODE,
190 		MAX98390_PCM_MASTER_MODE_MASK,
191 		mode);
192 
193 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
194 	case SND_SOC_DAIFMT_NB_NF:
195 		break;
196 	case SND_SOC_DAIFMT_IB_NF:
197 		invert = MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE;
198 		break;
199 	default:
200 		dev_err(component->dev, "DAI invert mode unsupported\n");
201 		return -EINVAL;
202 	}
203 
204 	regmap_update_bits(max98390->regmap,
205 		MAX98390_PCM_MODE_CFG,
206 		MAX98390_PCM_MODE_CFG_PCM_BCLKEDGE,
207 		invert);
208 
209 	/* interface format */
210 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
211 	case SND_SOC_DAIFMT_I2S:
212 		format = MAX98390_PCM_FORMAT_I2S;
213 		break;
214 	case SND_SOC_DAIFMT_LEFT_J:
215 		format = MAX98390_PCM_FORMAT_LJ;
216 		break;
217 	case SND_SOC_DAIFMT_DSP_A:
218 		format = MAX98390_PCM_FORMAT_TDM_MODE1;
219 		break;
220 	case SND_SOC_DAIFMT_DSP_B:
221 		format = MAX98390_PCM_FORMAT_TDM_MODE0;
222 		break;
223 	default:
224 		return -EINVAL;
225 	}
226 
227 	regmap_update_bits(max98390->regmap,
228 		MAX98390_PCM_MODE_CFG,
229 		MAX98390_PCM_MODE_CFG_FORMAT_MASK,
230 		format << MAX98390_PCM_MODE_CFG_FORMAT_SHIFT);
231 
232 	return 0;
233 }
234 
max98390_get_bclk_sel(int bclk)235 static int max98390_get_bclk_sel(int bclk)
236 {
237 	int i;
238 	/* BCLKs per LRCLK */
239 	static int bclk_sel_table[] = {
240 		32, 48, 64, 96, 128, 192, 256, 320, 384, 512,
241 	};
242 	/* match BCLKs per LRCLK */
243 	for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
244 		if (bclk_sel_table[i] == bclk)
245 			return i + 2;
246 	}
247 	return 0;
248 }
249 
max98390_set_clock(struct snd_soc_component * component,struct snd_pcm_hw_params * params)250 static int max98390_set_clock(struct snd_soc_component *component,
251 		struct snd_pcm_hw_params *params)
252 {
253 	struct max98390_priv *max98390 =
254 		snd_soc_component_get_drvdata(component);
255 	/* codec MCLK rate in master mode */
256 	static int rate_table[] = {
257 		5644800, 6000000, 6144000, 6500000,
258 		9600000, 11289600, 12000000, 12288000,
259 		13000000, 19200000,
260 	};
261 	/* BCLK/LRCLK ratio calculation */
262 	int blr_clk_ratio = params_channels(params)
263 		* snd_pcm_format_width(params_format(params));
264 	int value;
265 
266 	if (max98390->provider) {
267 		int i;
268 		/* match rate to closest value */
269 		for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
270 			if (rate_table[i] >= max98390->sysclk)
271 				break;
272 		}
273 		if (i == ARRAY_SIZE(rate_table)) {
274 			dev_err(component->dev, "failed to find proper clock rate.\n");
275 			return -EINVAL;
276 		}
277 
278 		regmap_update_bits(max98390->regmap,
279 			MAX98390_PCM_MASTER_MODE,
280 			MAX98390_PCM_MASTER_MODE_MCLK_MASK,
281 			i << MAX98390_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
282 	}
283 
284 	if (!max98390->tdm_mode) {
285 		/* BCLK configuration */
286 		value = max98390_get_bclk_sel(blr_clk_ratio);
287 		if (!value) {
288 			dev_err(component->dev, "format unsupported %d\n",
289 				params_format(params));
290 			return -EINVAL;
291 		}
292 
293 		regmap_update_bits(max98390->regmap,
294 			MAX98390_PCM_CLK_SETUP,
295 			MAX98390_PCM_CLK_SETUP_BSEL_MASK,
296 			value);
297 	}
298 	return 0;
299 }
300 
max98390_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)301 static int max98390_dai_hw_params(struct snd_pcm_substream *substream,
302 		struct snd_pcm_hw_params *params,
303 		struct snd_soc_dai *dai)
304 {
305 	struct snd_soc_component *component =
306 		dai->component;
307 	struct max98390_priv *max98390 =
308 		snd_soc_component_get_drvdata(component);
309 
310 	unsigned int sampling_rate;
311 	unsigned int chan_sz;
312 
313 	/* pcm mode configuration */
314 	switch (snd_pcm_format_width(params_format(params))) {
315 	case 16:
316 		chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
317 		break;
318 	case 24:
319 		chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
320 		break;
321 	case 32:
322 		chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
323 		break;
324 	default:
325 		dev_err(component->dev, "format unsupported %d\n",
326 			params_format(params));
327 		goto err;
328 	}
329 
330 	regmap_update_bits(max98390->regmap,
331 		MAX98390_PCM_MODE_CFG,
332 		MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
333 
334 	dev_dbg(component->dev, "format supported %d",
335 		params_format(params));
336 
337 	/* sampling rate configuration */
338 	switch (params_rate(params)) {
339 	case 8000:
340 		sampling_rate = MAX98390_PCM_SR_SET1_SR_8000;
341 		break;
342 	case 11025:
343 		sampling_rate = MAX98390_PCM_SR_SET1_SR_11025;
344 		break;
345 	case 12000:
346 		sampling_rate = MAX98390_PCM_SR_SET1_SR_12000;
347 		break;
348 	case 16000:
349 		sampling_rate = MAX98390_PCM_SR_SET1_SR_16000;
350 		break;
351 	case 22050:
352 		sampling_rate = MAX98390_PCM_SR_SET1_SR_22050;
353 		break;
354 	case 24000:
355 		sampling_rate = MAX98390_PCM_SR_SET1_SR_24000;
356 		break;
357 	case 32000:
358 		sampling_rate = MAX98390_PCM_SR_SET1_SR_32000;
359 		break;
360 	case 44100:
361 		sampling_rate = MAX98390_PCM_SR_SET1_SR_44100;
362 		break;
363 	case 48000:
364 		sampling_rate = MAX98390_PCM_SR_SET1_SR_48000;
365 		break;
366 	default:
367 		dev_err(component->dev, "rate %d not supported\n",
368 			params_rate(params));
369 		goto err;
370 	}
371 
372 	/* set DAI_SR to correct LRCLK frequency */
373 	regmap_update_bits(max98390->regmap,
374 		MAX98390_PCM_SR_SETUP,
375 		MAX98390_PCM_SR_SET1_SR_MASK,
376 		sampling_rate);
377 
378 	return max98390_set_clock(component, params);
379 err:
380 	return -EINVAL;
381 }
382 
max98390_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)383 static int max98390_dai_tdm_slot(struct snd_soc_dai *dai,
384 		unsigned int tx_mask, unsigned int rx_mask,
385 		int slots, int slot_width)
386 {
387 	struct snd_soc_component *component = dai->component;
388 	struct max98390_priv *max98390 =
389 		snd_soc_component_get_drvdata(component);
390 
391 	int bsel;
392 	unsigned int chan_sz;
393 
394 	if (!tx_mask && !rx_mask && !slots && !slot_width)
395 		max98390->tdm_mode = false;
396 	else
397 		max98390->tdm_mode = true;
398 
399 	dev_dbg(component->dev,
400 		"Tdm mode : %d\n", max98390->tdm_mode);
401 
402 	/* BCLK configuration */
403 	bsel = max98390_get_bclk_sel(slots * slot_width);
404 	if (!bsel) {
405 		dev_err(component->dev, "BCLK %d not supported\n",
406 			slots * slot_width);
407 		return -EINVAL;
408 	}
409 
410 	regmap_update_bits(max98390->regmap,
411 		MAX98390_PCM_CLK_SETUP,
412 		MAX98390_PCM_CLK_SETUP_BSEL_MASK,
413 		bsel);
414 
415 	/* Channel size configuration */
416 	switch (slot_width) {
417 	case 16:
418 		chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_16;
419 		break;
420 	case 24:
421 		chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_24;
422 		break;
423 	case 32:
424 		chan_sz = MAX98390_PCM_MODE_CFG_CHANSZ_32;
425 		break;
426 	default:
427 		dev_err(component->dev, "format unsupported %d\n",
428 			slot_width);
429 		return -EINVAL;
430 	}
431 
432 	regmap_update_bits(max98390->regmap,
433 		MAX98390_PCM_MODE_CFG,
434 		MAX98390_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
435 
436 	/* Rx slot configuration */
437 	regmap_write(max98390->regmap,
438 		MAX98390_PCM_RX_EN_A,
439 		rx_mask & 0xFF);
440 	regmap_write(max98390->regmap,
441 		MAX98390_PCM_RX_EN_B,
442 		(rx_mask & 0xFF00) >> 8);
443 
444 	/* Tx slot Hi-Z configuration */
445 	regmap_write(max98390->regmap,
446 		MAX98390_PCM_TX_HIZ_CTRL_A,
447 		~tx_mask & 0xFF);
448 	regmap_write(max98390->regmap,
449 		MAX98390_PCM_TX_HIZ_CTRL_B,
450 		(~tx_mask & 0xFF00) >> 8);
451 
452 	return 0;
453 }
454 
max98390_dai_set_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)455 static int max98390_dai_set_sysclk(struct snd_soc_dai *dai,
456 		int clk_id, unsigned int freq, int dir)
457 {
458 	struct snd_soc_component *component = dai->component;
459 	struct max98390_priv *max98390 =
460 		snd_soc_component_get_drvdata(component);
461 
462 	max98390->sysclk = freq;
463 	return 0;
464 }
465 
466 static const struct snd_soc_dai_ops max98390_dai_ops = {
467 	.set_sysclk = max98390_dai_set_sysclk,
468 	.set_fmt = max98390_dai_set_fmt,
469 	.hw_params = max98390_dai_hw_params,
470 	.set_tdm_slot = max98390_dai_tdm_slot,
471 };
472 
max98390_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)473 static int max98390_dac_event(struct snd_soc_dapm_widget *w,
474 		struct snd_kcontrol *kcontrol, int event)
475 {
476 	struct snd_soc_component *component =
477 		snd_soc_dapm_to_component(w->dapm);
478 	struct max98390_priv *max98390 =
479 		snd_soc_component_get_drvdata(component);
480 
481 	switch (event) {
482 	case SND_SOC_DAPM_POST_PMU:
483 		regmap_update_bits(max98390->regmap,
484 			MAX98390_R203A_AMP_EN,
485 			MAX98390_AMP_EN_MASK, 1);
486 		regmap_update_bits(max98390->regmap,
487 			MAX98390_R23FF_GLOBAL_EN,
488 			MAX98390_GLOBAL_EN_MASK, 1);
489 		break;
490 	case SND_SOC_DAPM_POST_PMD:
491 		regmap_update_bits(max98390->regmap,
492 			MAX98390_R23FF_GLOBAL_EN,
493 			MAX98390_GLOBAL_EN_MASK, 0);
494 		regmap_update_bits(max98390->regmap,
495 			MAX98390_R203A_AMP_EN,
496 			MAX98390_AMP_EN_MASK, 0);
497 		break;
498 	}
499 	return 0;
500 }
501 
502 static const char * const max98390_switch_text[] = {
503 	"Left", "Right", "LeftRight"};
504 
505 static const char * const max98390_boost_voltage_text[] = {
506 	"6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
507 	"7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
508 	"8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
509 	"9.5V", "9.625V", "9.75V", "9.875V", "10V"
510 };
511 
512 static SOC_ENUM_SINGLE_DECL(max98390_boost_voltage,
513 		MAX98390_BOOST_CTRL0, 0,
514 		max98390_boost_voltage_text);
515 
516 static DECLARE_TLV_DB_SCALE(max98390_spk_tlv, 300, 300, 0);
517 static DECLARE_TLV_DB_SCALE(max98390_digital_tlv, -8000, 50, 0);
518 
519 static const char * const max98390_current_limit_text[] = {
520 	"0.00A", "0.50A", "1.00A", "1.05A", "1.10A", "1.15A", "1.20A", "1.25A",
521 	"1.30A", "1.35A", "1.40A", "1.45A", "1.50A", "1.55A", "1.60A", "1.65A",
522 	"1.70A", "1.75A", "1.80A", "1.85A", "1.90A", "1.95A", "2.00A", "2.05A",
523 	"2.10A", "2.15A", "2.20A", "2.25A", "2.30A", "2.35A", "2.40A", "2.45A",
524 	"2.50A", "2.55A", "2.60A", "2.65A", "2.70A", "2.75A", "2.80A", "2.85A",
525 	"2.90A", "2.95A", "3.00A", "3.05A", "3.10A", "3.15A", "3.20A", "3.25A",
526 	"3.30A", "3.35A", "3.40A", "3.45A", "3.50A", "3.55A", "3.60A", "3.65A",
527 	"3.70A", "3.75A", "3.80A", "3.85A", "3.90A", "3.95A", "4.00A", "4.05A",
528 	"4.10A"
529 };
530 
531 static SOC_ENUM_SINGLE_DECL(max98390_current_limit,
532 		MAX98390_BOOST_CTRL1, 0,
533 		max98390_current_limit_text);
534 
max98390_ref_rdc_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)535 static int max98390_ref_rdc_put(struct snd_kcontrol *kcontrol,
536 		struct snd_ctl_elem_value *ucontrol)
537 {
538 	struct snd_soc_component *component =
539 		snd_soc_kcontrol_component(kcontrol);
540 	struct max98390_priv *max98390 =
541 		snd_soc_component_get_drvdata(component);
542 
543 	max98390->ref_rdc_value = ucontrol->value.integer.value[0];
544 
545 	regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
546 		max98390->ref_rdc_value & 0x000000ff);
547 	regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
548 		(max98390->ref_rdc_value >> 8) & 0x000000ff);
549 	regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
550 		(max98390->ref_rdc_value >> 16) & 0x000000ff);
551 
552 	return 0;
553 }
554 
max98390_ref_rdc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)555 static int max98390_ref_rdc_get(struct snd_kcontrol *kcontrol,
556 		struct snd_ctl_elem_value *ucontrol)
557 {
558 	struct snd_soc_component *component =
559 		snd_soc_kcontrol_component(kcontrol);
560 	struct max98390_priv *max98390 =
561 		snd_soc_component_get_drvdata(component);
562 
563 	ucontrol->value.integer.value[0] = max98390->ref_rdc_value;
564 
565 	return 0;
566 }
567 
max98390_ambient_temp_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)568 static int max98390_ambient_temp_put(struct snd_kcontrol *kcontrol,
569 		struct snd_ctl_elem_value *ucontrol)
570 {
571 	struct snd_soc_component *component =
572 		snd_soc_kcontrol_component(kcontrol);
573 	struct max98390_priv *max98390 =
574 		snd_soc_component_get_drvdata(component);
575 
576 	max98390->ambient_temp_value = ucontrol->value.integer.value[0];
577 
578 	regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
579 		(max98390->ambient_temp_value >> 8) & 0x000000ff);
580 	regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
581 		(max98390->ambient_temp_value) & 0x000000ff);
582 
583 	return 0;
584 }
585 
max98390_ambient_temp_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)586 static int max98390_ambient_temp_get(struct snd_kcontrol *kcontrol,
587 		struct snd_ctl_elem_value *ucontrol)
588 {
589 	struct snd_soc_component *component =
590 		snd_soc_kcontrol_component(kcontrol);
591 	struct max98390_priv *max98390 =
592 		snd_soc_component_get_drvdata(component);
593 
594 	ucontrol->value.integer.value[0] = max98390->ambient_temp_value;
595 
596 	return 0;
597 }
598 
max98390_adaptive_rdc_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)599 static int max98390_adaptive_rdc_put(struct snd_kcontrol *kcontrol,
600 		struct snd_ctl_elem_value *ucontrol)
601 {
602 	struct snd_soc_component *component =
603 		snd_soc_kcontrol_component(kcontrol);
604 
605 	dev_warn(component->dev, "Put adaptive rdc not supported\n");
606 
607 	return 0;
608 }
609 
max98390_adaptive_rdc_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)610 static int max98390_adaptive_rdc_get(struct snd_kcontrol *kcontrol,
611 		struct snd_ctl_elem_value *ucontrol)
612 {
613 	int rdc, rdc0;
614 	struct snd_soc_component *component =
615 		snd_soc_kcontrol_component(kcontrol);
616 	struct max98390_priv *max98390 =
617 		snd_soc_component_get_drvdata(component);
618 
619 	regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE1, &rdc);
620 	regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE0, &rdc0);
621 	ucontrol->value.integer.value[0] = rdc0 | rdc << 8;
622 
623 	return 0;
624 }
625 
max98390_dsm_calib_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)626 static int max98390_dsm_calib_get(struct snd_kcontrol *kcontrol,
627 		struct snd_ctl_elem_value *ucontrol)
628 {
629 	/* Do nothing */
630 	return 0;
631 }
632 
max98390_dsm_calib_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)633 static int max98390_dsm_calib_put(struct snd_kcontrol *kcontrol,
634 		struct snd_ctl_elem_value *ucontrol)
635 {
636 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
637 	struct max98390_priv *max98390 = snd_soc_component_get_drvdata(component);
638 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
639 	unsigned int rdc, rdc_cal_result, rdc_integer, rdc_factor, temp, val;
640 
641 	snd_soc_dapm_mutex_lock(dapm);
642 
643 	regmap_read(max98390->regmap, MAX98390_R23FF_GLOBAL_EN, &val);
644 	if (!val) {
645 		/* Enable the codec for the duration of calibration readout */
646 		regmap_update_bits(max98390->regmap, MAX98390_R203A_AMP_EN,
647 				   MAX98390_AMP_EN_MASK, 1);
648 		regmap_update_bits(max98390->regmap, MAX98390_R23FF_GLOBAL_EN,
649 				   MAX98390_GLOBAL_EN_MASK, 1);
650 	}
651 
652 	regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE1, &rdc);
653 	regmap_read(max98390->regmap, THERMAL_RDC_RD_BACK_BYTE0, &rdc_cal_result);
654 	regmap_read(max98390->regmap, MAX98390_MEAS_ADC_CH2_READ, &temp);
655 
656 	if (!val) {
657 		/* Disable the codec if it was disabled */
658 		regmap_update_bits(max98390->regmap, MAX98390_R23FF_GLOBAL_EN,
659 				   MAX98390_GLOBAL_EN_MASK, 0);
660 		regmap_update_bits(max98390->regmap, MAX98390_R203A_AMP_EN,
661 				   MAX98390_AMP_EN_MASK, 0);
662 	}
663 
664 	snd_soc_dapm_mutex_unlock(dapm);
665 
666 	rdc_cal_result |= (rdc << 8) & 0x0000FFFF;
667 	if (rdc_cal_result)
668 		max98390->ref_rdc_value = 268435456U / rdc_cal_result;
669 
670 	max98390->ambient_temp_value = temp * 52 - 1188;
671 
672 	rdc_integer =  rdc_cal_result * 937  / 65536;
673 	rdc_factor = ((rdc_cal_result * 937 * 100) / 65536) - (rdc_integer * 100);
674 
675 	dev_info(component->dev,
676 		 "rdc resistance about %d.%02d ohm, reg=0x%X temp reg=0x%X\n",
677 		 rdc_integer, rdc_factor, rdc_cal_result, temp);
678 
679 	return 0;
680 }
681 
682 static const struct snd_kcontrol_new max98390_snd_controls[] = {
683 	SOC_SINGLE_TLV("Digital Volume", DSM_VOL_CTRL,
684 		0, 184, 0,
685 		max98390_digital_tlv),
686 	SOC_SINGLE_TLV("Speaker Volume", MAX98390_R203D_SPK_GAIN,
687 		0, 6, 0,
688 		max98390_spk_tlv),
689 	SOC_SINGLE("Ramp Up Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
690 		MAX98390_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
691 	SOC_SINGLE("Ramp Down Bypass Switch", MAX98390_R2039_AMP_DSP_CFG,
692 		MAX98390_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
693 	SOC_SINGLE("Boost Clock Phase", MAX98390_BOOST_CTRL3,
694 		MAX98390_BOOST_CLK_PHASE_CFG_SHIFT, 3, 0),
695 	SOC_ENUM("Boost Output Voltage", max98390_boost_voltage),
696 	SOC_ENUM("Current Limit", max98390_current_limit),
697 	SOC_SINGLE_EXT("DSM Rdc", SND_SOC_NOPM, 0, 0xffffff, 0,
698 		max98390_ref_rdc_get, max98390_ref_rdc_put),
699 	SOC_SINGLE_EXT("DSM Ambient Temp", SND_SOC_NOPM, 0, 0xffff, 0,
700 		max98390_ambient_temp_get, max98390_ambient_temp_put),
701 	SOC_SINGLE_EXT("DSM Adaptive Rdc", SND_SOC_NOPM, 0, 0xffff, 0,
702 		max98390_adaptive_rdc_get, max98390_adaptive_rdc_put),
703 	SOC_SINGLE_EXT("DSM Calibration", SND_SOC_NOPM, 0, 1, 0,
704 		max98390_dsm_calib_get, max98390_dsm_calib_put),
705 };
706 
707 static const struct soc_enum dai_sel_enum =
708 	SOC_ENUM_SINGLE(MAX98390_PCM_CH_SRC_1,
709 		MAX98390_PCM_RX_CH_SRC_SHIFT,
710 		3, max98390_switch_text);
711 
712 static const struct snd_kcontrol_new max98390_dai_controls =
713 	SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
714 
715 static const struct snd_soc_dapm_widget max98390_dapm_widgets[] = {
716 	SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
717 		SND_SOC_NOPM, 0, 0, max98390_dac_event,
718 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
719 	SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
720 		&max98390_dai_controls),
721 	SND_SOC_DAPM_OUTPUT("BE_OUT"),
722 };
723 
724 static const struct snd_soc_dapm_route max98390_audio_map[] = {
725 	/* Plabyack */
726 	{"DAI Sel Mux", "Left", "Amp Enable"},
727 	{"DAI Sel Mux", "Right", "Amp Enable"},
728 	{"DAI Sel Mux", "LeftRight", "Amp Enable"},
729 	{"BE_OUT", NULL, "DAI Sel Mux"},
730 };
731 
max98390_readable_register(struct device * dev,unsigned int reg)732 static bool max98390_readable_register(struct device *dev, unsigned int reg)
733 {
734 	switch (reg) {
735 	case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
736 	case MAX98390_IRQ_CTRL ... MAX98390_WDOG_CTRL:
737 	case MAX98390_MEAS_ADC_THERM_WARN_THRESH
738 		... MAX98390_BROWNOUT_INFINITE_HOLD:
739 	case MAX98390_BROWNOUT_LVL_HOLD ... DSMIG_DEBUZZER_THRESHOLD:
740 	case DSM_VOL_ENA ... MAX98390_R24FF_REV_ID:
741 		return true;
742 	default:
743 		return false;
744 	}
745 };
746 
max98390_volatile_reg(struct device * dev,unsigned int reg)747 static bool max98390_volatile_reg(struct device *dev, unsigned int reg)
748 {
749 	switch (reg) {
750 	case MAX98390_SOFTWARE_RESET ... MAX98390_INT_EN3:
751 	case MAX98390_MEAS_ADC_CH0_READ ... MAX98390_MEAS_ADC_CH2_READ:
752 	case MAX98390_PWR_GATE_STATUS ... MAX98390_BROWNOUT_STATUS:
753 	case MAX98390_BROWNOUT_LOWEST_STATUS:
754 	case MAX98390_ENV_TRACK_BOOST_VOUT_READ:
755 	case DSM_STBASS_HPF_B0_BYTE0 ... DSM_DEBUZZER_ATTACK_TIME_BYTE2:
756 	case THERMAL_RDC_RD_BACK_BYTE1 ... DSMIG_DEBUZZER_THRESHOLD:
757 	case DSM_THERMAL_GAIN ... DSM_WBDRC_GAIN:
758 		return true;
759 	default:
760 		return false;
761 	}
762 }
763 
764 #define MAX98390_RATES SNDRV_PCM_RATE_8000_48000
765 
766 #define MAX98390_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
767 	SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
768 
769 static struct snd_soc_dai_driver max98390_dai[] = {
770 	{
771 		.name = "max98390-aif1",
772 		.playback = {
773 			.stream_name = "HiFi Playback",
774 			.channels_min = 1,
775 			.channels_max = 2,
776 			.rates = MAX98390_RATES,
777 			.formats = MAX98390_FORMATS,
778 		},
779 		.capture = {
780 			.stream_name = "HiFi Capture",
781 			.channels_min = 1,
782 			.channels_max = 2,
783 			.rates = MAX98390_RATES,
784 			.formats = MAX98390_FORMATS,
785 		},
786 		.ops = &max98390_dai_ops,
787 	}
788 };
789 
max98390_dsm_init(struct snd_soc_component * component)790 static int max98390_dsm_init(struct snd_soc_component *component)
791 {
792 	int ret;
793 	int param_size, param_start_addr;
794 	char filename[128];
795 	const char *vendor, *product;
796 	struct max98390_priv *max98390 =
797 		snd_soc_component_get_drvdata(component);
798 	const struct firmware *fw;
799 	char *dsm_param;
800 
801 	vendor = dmi_get_system_info(DMI_SYS_VENDOR);
802 	product = dmi_get_system_info(DMI_PRODUCT_NAME);
803 
804 	if (!strcmp(max98390->dsm_param_name, "default")) {
805 		if (vendor && product) {
806 			snprintf(filename, sizeof(filename),
807 				"dsm_param_%s_%s.bin", vendor, product);
808 		} else {
809 			sprintf(filename, "dsm_param.bin");
810 		}
811 	} else {
812 		snprintf(filename, sizeof(filename), "%s",
813 			max98390->dsm_param_name);
814 	}
815 	ret = request_firmware(&fw, filename, component->dev);
816 	if (ret) {
817 		ret = request_firmware(&fw, "dsm_param.bin", component->dev);
818 		if (ret) {
819 			ret = request_firmware(&fw, "dsmparam.bin",
820 				component->dev);
821 			if (ret)
822 				goto err;
823 		}
824 	}
825 
826 	dev_dbg(component->dev,
827 		"max98390: param fw size %zd\n",
828 		fw->size);
829 	if (fw->size < MAX98390_DSM_PARAM_MIN_SIZE) {
830 		dev_err(component->dev,
831 			"param fw is invalid.\n");
832 		ret = -EINVAL;
833 		goto err_alloc;
834 	}
835 	dsm_param = (char *)fw->data;
836 	param_start_addr = (dsm_param[0] & 0xff) | (dsm_param[1] & 0xff) << 8;
837 	param_size = (dsm_param[2] & 0xff) | (dsm_param[3] & 0xff) << 8;
838 	if (param_size > MAX98390_DSM_PARAM_MAX_SIZE ||
839 		param_start_addr < MAX98390_IRQ_CTRL ||
840 		fw->size < param_size + MAX98390_DSM_PAYLOAD_OFFSET) {
841 		dev_err(component->dev,
842 			"param fw is invalid.\n");
843 		ret = -EINVAL;
844 		goto err_alloc;
845 	}
846 	regmap_write(max98390->regmap, MAX98390_R203A_AMP_EN, 0x80);
847 	dsm_param += MAX98390_DSM_PAYLOAD_OFFSET;
848 	regmap_bulk_write(max98390->regmap, param_start_addr,
849 		dsm_param, param_size);
850 	regmap_write(max98390->regmap, MAX98390_R23E1_DSP_GLOBAL_EN, 0x01);
851 
852 err_alloc:
853 	release_firmware(fw);
854 err:
855 	return ret;
856 }
857 
max98390_init_regs(struct snd_soc_component * component)858 static void max98390_init_regs(struct snd_soc_component *component)
859 {
860 	struct max98390_priv *max98390 =
861 		snd_soc_component_get_drvdata(component);
862 
863 	regmap_write(max98390->regmap, MAX98390_CLK_MON, 0x6f);
864 	regmap_write(max98390->regmap, MAX98390_DAT_MON, 0x00);
865 	regmap_write(max98390->regmap, MAX98390_PWR_GATE_CTL, 0x00);
866 	regmap_write(max98390->regmap, MAX98390_PCM_RX_EN_A, 0x03);
867 	regmap_write(max98390->regmap, MAX98390_ENV_TRACK_VOUT_HEADROOM, 0x0e);
868 	regmap_write(max98390->regmap, MAX98390_BOOST_BYPASS1, 0x46);
869 	regmap_write(max98390->regmap, MAX98390_FET_SCALING3, 0x03);
870 
871 	/* voltage, current slot configuration */
872 	regmap_write(max98390->regmap,
873 		MAX98390_PCM_CH_SRC_2,
874 		(max98390->i_l_slot << 4 |
875 		max98390->v_l_slot)&0xFF);
876 
877 	if (max98390->v_l_slot < 8) {
878 		regmap_update_bits(max98390->regmap,
879 			MAX98390_PCM_TX_HIZ_CTRL_A,
880 			1 << max98390->v_l_slot, 0);
881 		regmap_update_bits(max98390->regmap,
882 			MAX98390_PCM_TX_EN_A,
883 			1 << max98390->v_l_slot,
884 			1 << max98390->v_l_slot);
885 	} else {
886 		regmap_update_bits(max98390->regmap,
887 			MAX98390_PCM_TX_HIZ_CTRL_B,
888 			1 << (max98390->v_l_slot - 8), 0);
889 		regmap_update_bits(max98390->regmap,
890 			MAX98390_PCM_TX_EN_B,
891 			1 << (max98390->v_l_slot - 8),
892 			1 << (max98390->v_l_slot - 8));
893 	}
894 
895 	if (max98390->i_l_slot < 8) {
896 		regmap_update_bits(max98390->regmap,
897 			MAX98390_PCM_TX_HIZ_CTRL_A,
898 			1 << max98390->i_l_slot, 0);
899 		regmap_update_bits(max98390->regmap,
900 			MAX98390_PCM_TX_EN_A,
901 			1 << max98390->i_l_slot,
902 			1 << max98390->i_l_slot);
903 	} else {
904 		regmap_update_bits(max98390->regmap,
905 			MAX98390_PCM_TX_HIZ_CTRL_B,
906 			1 << (max98390->i_l_slot - 8), 0);
907 		regmap_update_bits(max98390->regmap,
908 			MAX98390_PCM_TX_EN_B,
909 			1 << (max98390->i_l_slot - 8),
910 			1 << (max98390->i_l_slot - 8));
911 	}
912 }
913 
max98390_probe(struct snd_soc_component * component)914 static int max98390_probe(struct snd_soc_component *component)
915 {
916 	struct max98390_priv *max98390 =
917 		snd_soc_component_get_drvdata(component);
918 
919 	regmap_write(max98390->regmap, MAX98390_SOFTWARE_RESET, 0x01);
920 	/* Sleep reset settle time */
921 	msleep(20);
922 
923 	/* Amp init setting */
924 	max98390_init_regs(component);
925 	/* Update dsm bin param */
926 	max98390_dsm_init(component);
927 
928 	/* Dsm Setting */
929 	if (max98390->ref_rdc_value) {
930 		regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE0,
931 			max98390->ref_rdc_value & 0x000000ff);
932 		regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE1,
933 			(max98390->ref_rdc_value >> 8) & 0x000000ff);
934 		regmap_write(max98390->regmap, DSM_TPROT_RECIP_RDC_ROOM_BYTE2,
935 			(max98390->ref_rdc_value >> 16) & 0x000000ff);
936 	}
937 	if (max98390->ambient_temp_value) {
938 		regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE1,
939 			(max98390->ambient_temp_value >> 8) & 0x000000ff);
940 		regmap_write(max98390->regmap, DSM_TPROT_ROOM_TEMPERATURE_BYTE0,
941 			(max98390->ambient_temp_value) & 0x000000ff);
942 	}
943 
944 	return 0;
945 }
946 
947 #ifdef CONFIG_PM_SLEEP
max98390_suspend(struct device * dev)948 static int max98390_suspend(struct device *dev)
949 {
950 	struct max98390_priv *max98390 = dev_get_drvdata(dev);
951 
952 	dev_dbg(dev, "%s:Enter\n", __func__);
953 
954 	regcache_cache_only(max98390->regmap, true);
955 	regcache_mark_dirty(max98390->regmap);
956 
957 	return 0;
958 }
959 
max98390_resume(struct device * dev)960 static int max98390_resume(struct device *dev)
961 {
962 	struct max98390_priv *max98390 = dev_get_drvdata(dev);
963 
964 	dev_dbg(dev, "%s:Enter\n", __func__);
965 
966 	regcache_cache_only(max98390->regmap, false);
967 	regcache_sync(max98390->regmap);
968 
969 	return 0;
970 }
971 #endif
972 
973 static const struct dev_pm_ops max98390_pm = {
974 	SET_SYSTEM_SLEEP_PM_OPS(max98390_suspend, max98390_resume)
975 };
976 
977 static const struct snd_soc_component_driver soc_codec_dev_max98390 = {
978 	.probe			= max98390_probe,
979 	.controls		= max98390_snd_controls,
980 	.num_controls		= ARRAY_SIZE(max98390_snd_controls),
981 	.dapm_widgets		= max98390_dapm_widgets,
982 	.num_dapm_widgets	= ARRAY_SIZE(max98390_dapm_widgets),
983 	.dapm_routes		= max98390_audio_map,
984 	.num_dapm_routes	= ARRAY_SIZE(max98390_audio_map),
985 	.idle_bias_on		= 1,
986 	.use_pmdown_time	= 1,
987 	.endianness		= 1,
988 };
989 
990 static const struct regmap_config max98390_regmap = {
991 	.reg_bits         = 16,
992 	.val_bits         = 8,
993 	.max_register     = MAX98390_R24FF_REV_ID,
994 	.reg_defaults     = max98390_reg_defaults,
995 	.num_reg_defaults = ARRAY_SIZE(max98390_reg_defaults),
996 	.readable_reg	  = max98390_readable_register,
997 	.volatile_reg	  = max98390_volatile_reg,
998 	.cache_type       = REGCACHE_RBTREE,
999 };
1000 
max98390_slot_config(struct i2c_client * i2c,struct max98390_priv * max98390)1001 static void max98390_slot_config(struct i2c_client *i2c,
1002 	struct max98390_priv *max98390)
1003 {
1004 	int value;
1005 	struct device *dev = &i2c->dev;
1006 
1007 	if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
1008 		max98390->v_l_slot = value & 0xF;
1009 	else
1010 		max98390->v_l_slot = 0;
1011 
1012 	if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
1013 		max98390->i_l_slot = value & 0xF;
1014 	else
1015 		max98390->i_l_slot = 1;
1016 }
1017 
max98390_i2c_probe(struct i2c_client * i2c)1018 static int max98390_i2c_probe(struct i2c_client *i2c)
1019 {
1020 	int ret = 0;
1021 	int reg = 0;
1022 
1023 	struct max98390_priv *max98390 = NULL;
1024 	struct i2c_adapter *adapter = i2c->adapter;
1025 	struct gpio_desc *reset_gpio;
1026 
1027 	ret = i2c_check_functionality(adapter,
1028 		I2C_FUNC_SMBUS_BYTE
1029 		| I2C_FUNC_SMBUS_BYTE_DATA);
1030 	if (!ret) {
1031 		dev_err(&i2c->dev, "I2C check functionality failed\n");
1032 		return -ENXIO;
1033 	}
1034 
1035 	max98390 = devm_kzalloc(&i2c->dev, sizeof(*max98390), GFP_KERNEL);
1036 	if (!max98390) {
1037 		ret = -ENOMEM;
1038 		return ret;
1039 	}
1040 	i2c_set_clientdata(i2c, max98390);
1041 
1042 	ret = device_property_read_u32(&i2c->dev, "maxim,temperature_calib",
1043 				       &max98390->ambient_temp_value);
1044 	if (ret) {
1045 		dev_info(&i2c->dev,
1046 			 "no optional property 'temperature_calib' found, default:\n");
1047 	}
1048 	ret = device_property_read_u32(&i2c->dev, "maxim,r0_calib",
1049 				       &max98390->ref_rdc_value);
1050 	if (ret) {
1051 		dev_info(&i2c->dev,
1052 			 "no optional property 'r0_calib' found, default:\n");
1053 	}
1054 
1055 	dev_info(&i2c->dev,
1056 		"%s: r0_calib: 0x%x,temperature_calib: 0x%x",
1057 		__func__, max98390->ref_rdc_value,
1058 		max98390->ambient_temp_value);
1059 
1060 	ret = device_property_read_string(&i2c->dev, "maxim,dsm_param_name",
1061 				       &max98390->dsm_param_name);
1062 	if (ret)
1063 		max98390->dsm_param_name = "default";
1064 
1065 	/* voltage/current slot configuration */
1066 	max98390_slot_config(i2c, max98390);
1067 
1068 	/* regmap initialization */
1069 	max98390->regmap = devm_regmap_init_i2c(i2c, &max98390_regmap);
1070 	if (IS_ERR(max98390->regmap)) {
1071 		ret = PTR_ERR(max98390->regmap);
1072 		dev_err(&i2c->dev,
1073 			"Failed to allocate regmap: %d\n", ret);
1074 		return ret;
1075 	}
1076 
1077 	reset_gpio = devm_gpiod_get_optional(&i2c->dev,
1078 					     "reset", GPIOD_OUT_HIGH);
1079 
1080 	/* Power on device */
1081 	if (reset_gpio) {
1082 		usleep_range(1000, 2000);
1083 		/* bring out of reset */
1084 		gpiod_set_value_cansleep(reset_gpio, 0);
1085 		usleep_range(1000, 2000);
1086 	}
1087 
1088 	/* Check Revision ID */
1089 	ret = regmap_read(max98390->regmap,
1090 		MAX98390_R24FF_REV_ID, &reg);
1091 	if (ret) {
1092 		dev_err(&i2c->dev,
1093 			"ret=%d, Failed to read: 0x%02X\n",
1094 			ret, MAX98390_R24FF_REV_ID);
1095 		return ret;
1096 	}
1097 	dev_info(&i2c->dev, "MAX98390 revisionID: 0x%02X\n", reg);
1098 
1099 	ret = devm_snd_soc_register_component(&i2c->dev,
1100 			&soc_codec_dev_max98390,
1101 			max98390_dai, ARRAY_SIZE(max98390_dai));
1102 
1103 	return ret;
1104 }
1105 
1106 static const struct i2c_device_id max98390_i2c_id[] = {
1107 	{ "max98390", 0},
1108 	{},
1109 };
1110 
1111 MODULE_DEVICE_TABLE(i2c, max98390_i2c_id);
1112 
1113 #if defined(CONFIG_OF)
1114 static const struct of_device_id max98390_of_match[] = {
1115 	{ .compatible = "maxim,max98390", },
1116 	{}
1117 };
1118 MODULE_DEVICE_TABLE(of, max98390_of_match);
1119 #endif
1120 
1121 #ifdef CONFIG_ACPI
1122 static const struct acpi_device_id max98390_acpi_match[] = {
1123 	{ "MX98390", 0 },
1124 	{},
1125 };
1126 MODULE_DEVICE_TABLE(acpi, max98390_acpi_match);
1127 #endif
1128 
1129 static struct i2c_driver max98390_i2c_driver = {
1130 	.driver = {
1131 		.name = "max98390",
1132 		.of_match_table = of_match_ptr(max98390_of_match),
1133 		.acpi_match_table = ACPI_PTR(max98390_acpi_match),
1134 		.pm = &max98390_pm,
1135 	},
1136 	.probe = max98390_i2c_probe,
1137 	.id_table = max98390_i2c_id,
1138 };
1139 
1140 module_i2c_driver(max98390_i2c_driver)
1141 
1142 MODULE_DESCRIPTION("ALSA SoC MAX98390 driver");
1143 MODULE_AUTHOR("Steve Lee <steves.lee@maximintegrated.com>");
1144 MODULE_LICENSE("GPL");
1145