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Searched defs:MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h7670 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x00000010 macro
H A Ddce_8_0_sh_mask.h8150 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 macro
H A Ddce_10_0_sh_mask.h7214 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 macro
H A Ddce_11_0_sh_mask.h7104 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 macro
H A Ddce_11_2_sh_mask.h8216 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT 0x10 macro
H A Ddce_12_0_sh_mask.h5112 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h1743 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h2637 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_1_0_sh_mask.h4131 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h2838 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h2322 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h1679 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h2889 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h10952 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h2798 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h2905 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h2895 #define MASTER_COMM_CMD_REG__MASTER_COMM_CMD_REG_BYTE2__SHIFT … macro