xref: /openbmc/u-boot/include/fsl_dtsec.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2009-2011 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __DTSEC_H__
7 #define __DTSEC_H__
8 
9 #include <asm/types.h>
10 
11 struct dtsec {
12 	u32	tsec_id;	/* controller ID and version */
13 	u32	tsec_id2;	/* controller ID and configuration */
14 	u32	ievent;		/* interrupt event */
15 	u32	imask;		/* interrupt mask */
16 	u32	res0;
17 	u32	ecntrl;		/* ethernet control and configuration */
18 	u32	ptv;		/* pause time value */
19 	u32	tbipa;		/* TBI PHY address */
20 	u32	res1[8];
21 	u32	tctrl;		/* Transmit control register */
22 	u32	res2[3];
23 	u32	rctrl;		/* Receive control register */
24 	u32	res3[11];
25 	u32	igaddr[8];	/* Individual group address */
26 	u32	gaddr[8];	/* group address */
27 	u32	res4[16];
28 	u32	maccfg1;	/* MAC configuration register 1 */
29 	u32	maccfg2;	/* MAC configuration register 2 */
30 	u32	ipgifg;		/* inter-packet/inter-frame gap */
31 	u32	hafdup;		/* half-duplex control */
32 	u32	maxfrm;		/* Maximum frame size */
33 	u32	res5[3];
34 	u32	miimcfg;	/* MII management configuration */
35 	u32	miimcom;	/* MII management command */
36 	u32	miimadd;	/* MII management address */
37 	u32	miimcon;	/* MII management control */
38 	u32	miimstat;	/* MII management status */
39 	u32	miimind;	/* MII management indicator */
40 	u32	res6;
41 	u32	ifstat;		/* Interface status */
42 	u32	macstnaddr1;	/* MAC station address 1 */
43 	u32	macstnaddr2;	/* MAC station address 2 */
44 	u32	res7[46];
45 	/* transmit and receive counter */
46 	u32	tr64;		/* Tx and Rx 64 bytes frame */
47 	u32	tr127;		/* Tx and Rx 65 to 127 bytes frame */
48 	u32	tr255;		/* Tx and Rx 128 to 255 bytes frame */
49 	u32	tr511;		/* Tx and Rx 256 to 511 bytes frame */
50 	u32	tr1k;		/* Tx and Rx 512 to 1023 bytes frame */
51 	u32	trmax;		/* Tx and Rx 1024 to 1518 bytes frame */
52 	u32	trmgv;		/* Tx and Rx 1519 to 1522 good VLAN frame */
53 	/* receive counters */
54 	u32	rbyt;		/* Receive byte counter */
55 	u32	rpkt;		/* Receive packet counter */
56 	u32	rfcs;		/* Receive FCS error */
57 	u32	rmca;		/* Receive multicast packet */
58 	u32	rbca;		/* Receive broadcast packet */
59 	u32	rxcf;		/* Receive control frame */
60 	u32	rxpf;		/* Receive pause frame */
61 	u32	rxuo;		/* Receive unknown OP code */
62 	u32	raln;		/* Receive alignment error */
63 	u32	rflr;		/* Receive frame length error */
64 	u32	rcde;		/* Receive code error */
65 	u32	rcse;		/* Receive carrier sense error */
66 	u32	rund;		/* Receive undersize packet */
67 	u32	rovr;		/* Receive oversize packet */
68 	u32	rfrg;		/* Receive fragments counter */
69 	u32	rjbr;		/* Receive jabber counter */
70 	u32	rdrp;		/* Receive drop counter */
71 	/* transmit counters */
72 	u32	tbyt;		/* Transmit byte counter */
73 	u32	tpkt;		/* Transmit packet */
74 	u32	tmca;		/* Transmit multicast packet */
75 	u32	tbca;		/* Transmit broadcast packet */
76 	u32	txpf;		/* Transmit pause control frame */
77 	u32	tdfr;		/* Transmit deferral packet */
78 	u32	tedf;		/* Transmit excessive deferral pkt */
79 	u32	tscl;		/* Transmit single collision pkt */
80 	u32	tmcl;		/* Transmit multiple collision pkt */
81 	u32	tlcl;		/* Transmit late collision pkt */
82 	u32	txcl;		/* Transmit excessive collision */
83 	u32	tncl;		/* Transmit total collision */
84 	u32	res8;
85 	u32	tdrp;		/* Transmit drop frame */
86 	u32	tjbr;		/* Transmit jabber frame */
87 	u32	tfcs;		/* Transmit FCS error */
88 	u32	txcf;		/* Transmit control frame */
89 	u32	tovr;		/* Transmit oversize frame */
90 	u32	tund;		/* Transmit undersize frame */
91 	u32	tfrg;		/* Transmit fragments frame */
92 	/* counter controls */
93 	u32	car1;		/* carry register 1 */
94 	u32	car2;		/* carry register 2 */
95 	u32	cam1;		/* carry register 1 mask */
96 	u32	cam2;		/* carry register 2 mask */
97 	u32	res9[80];
98 };
99 
100 
101 /* TBI register addresses */
102 #define TBI_CR			0x00
103 #define TBI_SR			0x01
104 #define TBI_ANA			0x04
105 #define TBI_ANLPBPA		0x05
106 #define TBI_ANEX		0x06
107 #define TBI_TBICON		0x11
108 
109 /* TBI MDIO register bit fields*/
110 #define TBICON_CLK_SELECT	0x0020
111 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
112 #define TBIANA_SYMMETRIC_PAUSE  0x0080
113 #define TBIANA_HALF_DUPLEX	0x0040
114 #define TBIANA_FULL_DUPLEX	0x0020
115 #define TBICR_PHY_RESET		0x8000
116 #define TBICR_ANEG_ENABLE	0x1000
117 #define TBICR_RESTART_ANEG	0x0200
118 #define TBICR_FULL_DUPLEX	0x0100
119 #define TBICR_SPEED1_SET	0x0040
120 
121 /* IEVENT - interrupt events register */
122 #define IEVENT_BABR	0x80000000 /* Babbling receive error */
123 #define IEVENT_RXC	0x40000000 /* pause control frame received */
124 #define IEVENT_MSRO	0x04000000 /* MIB counter overflow */
125 #define IEVENT_GTSC	0x02000000 /* Graceful transmit stop complete */
126 #define IEVENT_BABT	0x01000000 /* Babbling transmit error */
127 #define IEVENT_TXC	0x00800000 /* control frame transmitted */
128 #define IEVENT_TXE	0x00400000 /* Transmit channel error */
129 #define IEVENT_LC	0x00040000 /* Late collision occurred */
130 #define IEVENT_CRL	0x00020000 /* Collision retry exceed limit */
131 #define IEVENT_XFUN	0x00010000 /* Transmit FIFO underrun */
132 #define IEVENT_ABRT	0x00008000 /* Transmit packet abort */
133 #define IEVENT_MMRD	0x00000400 /* MII management read complete */
134 #define IEVENT_MMWR	0x00000200 /* MII management write complete */
135 #define IEVENT_GRSC	0x00000100 /* Graceful stop complete */
136 #define IEVENT_TDPE	0x00000002 /* Internal data parity error on Tx */
137 #define IEVENT_RDPE	0x00000001 /* Internal data parity error on Rx */
138 
139 #define IEVENT_CLEAR_ALL	0xffffffff
140 
141 /* IMASK - interrupt mask register */
142 #define IMASK_BREN	0x80000000 /* Babbling receive enable */
143 #define IMASK_RXCEN	0x40000000 /* receive control enable */
144 #define IMASK_MSROEN	0x04000000 /* MIB counter overflow enable */
145 #define IMASK_GTSCEN	0x02000000 /* Graceful Tx stop complete enable */
146 #define IMASK_BTEN	0x01000000 /* Babbling transmit error enable */
147 #define IMASK_TXCEN	0x00800000 /* control frame transmitted enable */
148 #define IMASK_TXEEN	0x00400000 /* Transmit channel error enable */
149 #define IMASK_LCEN	0x00040000 /* Late collision interrupt enable */
150 #define IMASK_CRLEN	0x00020000 /* Collision retry exceed limit */
151 #define IMASK_XFUNEN	0x00010000 /* Transmit FIFO underrun enable */
152 #define IMASK_ABRTEN	0x00008000 /* Transmit packet abort enable */
153 #define IMASK_MMRDEN	0x00000400 /* MII management read complete enable */
154 #define IMASK_MMWREN	0x00000200 /* MII management write complete enable */
155 #define IMASK_GRSCEN	0x00000100 /* Graceful stop complete interrupt enable */
156 #define IMASK_TDPEEN	0x00000002 /* Internal data parity error on Tx enable */
157 #define IMASK_RDPEEN	0x00000001 /* Internal data parity error on Rx enable */
158 
159 #define IMASK_MASK_ALL	0x00000000
160 
161 /* ECNTRL - ethernet control register */
162 #define ECNTRL_CFG_RO	0x80000000 /* GMIIM, RPM, R100M, SGMIIM bits are RO */
163 #define ECNTRL_CLRCNT	0x00004000 /* clear all statistics */
164 #define ECNTRL_AUTOZ	0x00002000 /* auto zero MIB counter */
165 #define ECNTRL_STEN	0x00001000 /* enable internal counters to update */
166 #define ECNTRL_GMIIM	0x00000040 /* 1- GMII or RGMII interface mode */
167 #define ECNTRL_TBIM	0x00000020 /* 1- Ten-bit interface mode */
168 #define ECNTRL_RPM	0x00000010 /* 1- RGMII reduced-pin mode */
169 #define ECNTRL_R100M	0x00000008 /* 1- RGMII 100 Mbps, SGMII 100 Mbps
170 				      0- RGMII 10 Mbps, SGMII 10 Mbps */
171 #define ECNTRL_SGMIIM	0x00000002 /* 1- SGMII interface mode */
172 #define ECNTRL_TBIM	0x00000020 /* 1- TBI Interface mode (for SGMII) */
173 
174 #define ECNTRL_DEFAULT	(ECNTRL_TBIM | ECNTRL_R100M | ECNTRL_SGMIIM)
175 
176 /* TCTRL - Transmit control register */
177 #define TCTRL_THDF	0x00000800 /* Transmit half-duplex flow control */
178 #define TCTRL_TTSE	0x00000040 /* Transmit time-stamp enable */
179 #define TCTRL_GTS	0x00000020 /* Graceful transmit stop */
180 #define TCTRL_RFC_PAUSE	0x00000010 /* Receive flow control pause frame */
181 
182 /* RCTRL - Receive control register */
183 #define RCTRL_PAL_MASK	0x001f0000 /* packet alignment padding length */
184 #define RCTRL_PAL_SHIFT	16
185 #define RCTRL_CFA	0x00008000 /* control frame accept enable */
186 #define RCTRL_GHTX	0x00000800 /* group address hash table extend */
187 #define RCTRL_RTSE	0x00000040 /* receive 1588 time-stamp enable */
188 #define RCTRL_GRS	0x00000020 /* graceful receive stop */
189 #define RCTRL_BC_REJ	0x00000010 /* broadcast frame reject */
190 #define RCTRL_BC_MPROM	0x00000008 /* all multicast/broadcast frames received */
191 #define RCTRL_RSF	0x00000004 /* receive short frame(17~63 bytes) enable */
192 #define RCTRL_EMEN	0x00000002 /* Exact match MAC address enable */
193 #define RCTRL_UPROM	0x00000001 /* all unicast frame received */
194 
195 /* MACCFG1 - MAC configuration 1 register */
196 #define MACCFG1_SOFT_RST	0x80000000 /* place the MAC in reset */
197 #define MACCFG1_RST_RXMAC	0x00080000 /* reset receive MAC control block */
198 #define MACCFG1_RST_TXMAC	0x00040000 /* reet transmit MAC control block */
199 #define MACCFG1_RST_RXFUN	0x00020000 /* reset receive function block */
200 #define MACCFG1_RST_TXFUN	0x00010000 /* reset transmit function block */
201 #define MACCFG1_LOOPBACK	0x00000100 /* MAC loopback */
202 #define MACCFG1_RX_FLOW		0x00000020 /* Receive flow */
203 #define MACCFG1_TX_FLOW		0x00000010 /* Transmit flow */
204 #define MACCFG1_SYNC_RXEN	0x00000008 /* Frame reception enabled */
205 #define MACCFG1_RX_EN		0x00000004 /* Rx enable */
206 #define MACCFG1_SYNC_TXEN	0x00000002 /* Frame transmission is enabled */
207 #define MACCFG1_TX_EN		0x00000001 /* Tx enable */
208 #define MACCFG1_RXTX_EN		(MACCFG1_RX_EN | MACCFG1_TX_EN)
209 
210 /* MACCFG2 - MAC configuration 2 register */
211 #define MACCFG2_PRE_LEN_MASK	0x0000f000 /* preamble length */
212 #define MACCFG2_PRE_LEN(x)	((x << 12) & MACCFG2_PRE_LEN_MASK)
213 #define MACCFG2_IF_MODE_MASK	0x00000300
214 #define MACCFG2_IF_MODE_NIBBLE	0x00000100 /* MII, 10/100 Mbps MII/RMII */
215 #define MACCFG2_IF_MODE_BYTE	0x00000200 /* GMII/TBI, 1000 GMII/TBI */
216 #define MACCFG2_PRE_RX_EN	0x00000080 /* receive preamble enable */
217 #define MACCFG2_PRE_TX_EN	0x00000040 /* tx preable enable */
218 #define MACCFG2_HUGE_FRAME	0x00000020 /* >= max frame len enable */
219 #define MACCFG2_LEN_CHECK	0x00000010 /* MAC check frame's length Rx */
220 #define MACCFG2_MAG_EN		0x00000008 /* magic packet enable */
221 #define MACCFG2_PAD_CRC		0x00000004 /* pad and append CRC */
222 #define MACCFG2_CRC_EN		0x00000002 /* MAC appends a CRC on all frames */
223 #define MACCFG2_FULL_DUPLEX	0x00000001 /* Full deplex mode */
224 
225 struct fsl_enet_mac;
226 
227 void init_dtsec(struct fsl_enet_mac *mac, void *base, void *phyregs,
228 		int max_rx_len);
229 
230 #endif
231