xref: /openbmc/linux/drivers/watchdog/lantiq_wdt.c (revision cc85f87a)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  *
4  *  Copyright (C) 2010 John Crispin <john@phrozen.org>
5  *  Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
6  *  Based on EP93xx wdt driver
7  */
8 
9 #include <linux/module.h>
10 #include <linux/bitops.h>
11 #include <linux/watchdog.h>
12 #include <linux/of.h>
13 #include <linux/platform_device.h>
14 #include <linux/uaccess.h>
15 #include <linux/clk.h>
16 #include <linux/io.h>
17 #include <linux/regmap.h>
18 #include <linux/mfd/syscon.h>
19 
20 #include <lantiq_soc.h>
21 
22 #define LTQ_XRX_RCU_RST_STAT		0x0014
23 #define LTQ_XRX_RCU_RST_STAT_WDT	BIT(31)
24 
25 /* CPU0 Reset Source Register */
26 #define LTQ_FALCON_SYS1_CPU0RS		0x0060
27 /* reset cause mask */
28 #define LTQ_FALCON_SYS1_CPU0RS_MASK	0x0007
29 #define LTQ_FALCON_SYS1_CPU0RS_WDT	0x02
30 
31 /*
32  * Section 3.4 of the datasheet
33  * The password sequence protects the WDT control register from unintended
34  * write actions, which might cause malfunction of the WDT.
35  *
36  * essentially the following two magic passwords need to be written to allow
37  * IO access to the WDT core
38  */
39 #define LTQ_WDT_CR_PW1		0x00BE0000
40 #define LTQ_WDT_CR_PW2		0x00DC0000
41 
42 #define LTQ_WDT_CR		0x0		/* watchdog control register */
43 #define  LTQ_WDT_CR_GEN		BIT(31)		/* enable bit */
44 /* Pre-warning limit set to 1/16 of max WDT period */
45 #define  LTQ_WDT_CR_PWL		(0x3 << 26)
46 /* set clock divider to 0x40000 */
47 #define  LTQ_WDT_CR_CLKDIV	(0x3 << 24)
48 #define  LTQ_WDT_CR_PW_MASK	GENMASK(23, 16)	/* Password field */
49 #define  LTQ_WDT_CR_MAX_TIMEOUT	((1 << 16) - 1)	/* The reload field is 16 bit */
50 #define LTQ_WDT_SR		0x8		/* watchdog status register */
51 #define  LTQ_WDT_SR_EN		BIT(31)		/* Enable */
52 #define  LTQ_WDT_SR_VALUE_MASK	GENMASK(15, 0)	/* Timer value */
53 
54 #define LTQ_WDT_DIVIDER		0x40000
55 
56 static bool nowayout = WATCHDOG_NOWAYOUT;
57 
58 struct ltq_wdt_hw {
59 	int (*bootstatus_get)(struct device *dev);
60 };
61 
62 struct ltq_wdt_priv {
63 	struct watchdog_device wdt;
64 	void __iomem *membase;
65 	unsigned long clk_rate;
66 };
67 
ltq_wdt_r32(struct ltq_wdt_priv * priv,u32 offset)68 static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
69 {
70 	return __raw_readl(priv->membase + offset);
71 }
72 
ltq_wdt_w32(struct ltq_wdt_priv * priv,u32 val,u32 offset)73 static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
74 {
75 	__raw_writel(val, priv->membase + offset);
76 }
77 
ltq_wdt_mask(struct ltq_wdt_priv * priv,u32 clear,u32 set,u32 offset)78 static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
79 			 u32 offset)
80 {
81 	u32 val = ltq_wdt_r32(priv, offset);
82 
83 	val &= ~(clear);
84 	val |= set;
85 	ltq_wdt_w32(priv, val, offset);
86 }
87 
ltq_wdt_get_priv(struct watchdog_device * wdt)88 static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
89 {
90 	return container_of(wdt, struct ltq_wdt_priv, wdt);
91 }
92 
93 static struct watchdog_info ltq_wdt_info = {
94 	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
95 		   WDIOF_CARDRESET,
96 	.identity = "ltq_wdt",
97 };
98 
ltq_wdt_start(struct watchdog_device * wdt)99 static int ltq_wdt_start(struct watchdog_device *wdt)
100 {
101 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
102 	u32 timeout;
103 
104 	timeout = wdt->timeout * priv->clk_rate;
105 
106 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
107 	/* write the second magic plus the configuration and new timeout */
108 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
109 		     LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
110 		     LTQ_WDT_CR_PW2 | timeout,
111 		     LTQ_WDT_CR);
112 
113 	return 0;
114 }
115 
ltq_wdt_stop(struct watchdog_device * wdt)116 static int ltq_wdt_stop(struct watchdog_device *wdt)
117 {
118 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
119 
120 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
121 	ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
122 		     LTQ_WDT_CR_PW2, LTQ_WDT_CR);
123 
124 	return 0;
125 }
126 
ltq_wdt_ping(struct watchdog_device * wdt)127 static int ltq_wdt_ping(struct watchdog_device *wdt)
128 {
129 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
130 	u32 timeout;
131 
132 	timeout = wdt->timeout * priv->clk_rate;
133 
134 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
135 	/* write the second magic plus the configuration and new timeout */
136 	ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
137 		     LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);
138 
139 	return 0;
140 }
141 
ltq_wdt_get_timeleft(struct watchdog_device * wdt)142 static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
143 {
144 	struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
145 	u64 timeout;
146 
147 	timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
148 	return do_div(timeout, priv->clk_rate);
149 }
150 
151 static const struct watchdog_ops ltq_wdt_ops = {
152 	.owner		= THIS_MODULE,
153 	.start		= ltq_wdt_start,
154 	.stop		= ltq_wdt_stop,
155 	.ping		= ltq_wdt_ping,
156 	.get_timeleft	= ltq_wdt_get_timeleft,
157 };
158 
ltq_wdt_xrx_bootstatus_get(struct device * dev)159 static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
160 {
161 	struct regmap *rcu_regmap;
162 	u32 val;
163 	int err;
164 
165 	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
166 	if (IS_ERR(rcu_regmap))
167 		return PTR_ERR(rcu_regmap);
168 
169 	err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
170 	if (err)
171 		return err;
172 
173 	if (val & LTQ_XRX_RCU_RST_STAT_WDT)
174 		return WDIOF_CARDRESET;
175 
176 	return 0;
177 }
178 
ltq_wdt_falcon_bootstatus_get(struct device * dev)179 static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
180 {
181 	struct regmap *rcu_regmap;
182 	u32 val;
183 	int err;
184 
185 	rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
186 						     "lantiq,rcu");
187 	if (IS_ERR(rcu_regmap))
188 		return PTR_ERR(rcu_regmap);
189 
190 	err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
191 	if (err)
192 		return err;
193 
194 	if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
195 		return WDIOF_CARDRESET;
196 
197 	return 0;
198 }
199 
ltq_wdt_probe(struct platform_device * pdev)200 static int ltq_wdt_probe(struct platform_device *pdev)
201 {
202 	struct device *dev = &pdev->dev;
203 	struct ltq_wdt_priv *priv;
204 	struct watchdog_device *wdt;
205 	struct clk *clk;
206 	const struct ltq_wdt_hw *ltq_wdt_hw;
207 	int ret;
208 	u32 status;
209 
210 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
211 	if (!priv)
212 		return -ENOMEM;
213 
214 	priv->membase = devm_platform_ioremap_resource(pdev, 0);
215 	if (IS_ERR(priv->membase))
216 		return PTR_ERR(priv->membase);
217 
218 	/* we do not need to enable the clock as it is always running */
219 	clk = clk_get_io();
220 	priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
221 	if (!priv->clk_rate) {
222 		dev_err(dev, "clock rate less than divider %i\n",
223 			LTQ_WDT_DIVIDER);
224 		return -EINVAL;
225 	}
226 
227 	wdt = &priv->wdt;
228 	wdt->info		= &ltq_wdt_info;
229 	wdt->ops		= &ltq_wdt_ops;
230 	wdt->min_timeout	= 1;
231 	wdt->max_timeout	= LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
232 	wdt->timeout		= wdt->max_timeout;
233 	wdt->parent		= dev;
234 
235 	ltq_wdt_hw = of_device_get_match_data(dev);
236 	if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
237 		ret = ltq_wdt_hw->bootstatus_get(dev);
238 		if (ret >= 0)
239 			wdt->bootstatus = ret;
240 	}
241 
242 	watchdog_set_nowayout(wdt, nowayout);
243 	watchdog_init_timeout(wdt, 0, dev);
244 
245 	status = ltq_wdt_r32(priv, LTQ_WDT_SR);
246 	if (status & LTQ_WDT_SR_EN) {
247 		/*
248 		 * If the watchdog is already running overwrite it with our
249 		 * new settings. Stop is not needed as the start call will
250 		 * replace all settings anyway.
251 		 */
252 		ltq_wdt_start(wdt);
253 		set_bit(WDOG_HW_RUNNING, &wdt->status);
254 	}
255 
256 	return devm_watchdog_register_device(dev, wdt);
257 }
258 
259 static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
260 	.bootstatus_get = ltq_wdt_xrx_bootstatus_get,
261 };
262 
263 static const struct ltq_wdt_hw ltq_wdt_falcon = {
264 	.bootstatus_get = ltq_wdt_falcon_bootstatus_get,
265 };
266 
267 static const struct of_device_id ltq_wdt_match[] = {
268 	{ .compatible = "lantiq,wdt", .data = NULL },
269 	{ .compatible = "lantiq,xrx100-wdt", .data = &ltq_wdt_xrx100 },
270 	{ .compatible = "lantiq,falcon-wdt", .data = &ltq_wdt_falcon },
271 	{},
272 };
273 MODULE_DEVICE_TABLE(of, ltq_wdt_match);
274 
275 static struct platform_driver ltq_wdt_driver = {
276 	.probe = ltq_wdt_probe,
277 	.driver = {
278 		.name = "wdt",
279 		.of_match_table = ltq_wdt_match,
280 	},
281 };
282 
283 module_platform_driver(ltq_wdt_driver);
284 
285 module_param(nowayout, bool, 0);
286 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
287 MODULE_AUTHOR("John Crispin <john@phrozen.org>");
288 MODULE_DESCRIPTION("Lantiq SoC Watchdog");
289 MODULE_LICENSE("GPL");
290