xref: /openbmc/linux/sound/soc/qcom/lpass-lpaif-reg.h (revision dc8d9766)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef __LPASS_LPAIF_REG_H__
7 #define __LPASS_LPAIF_REG_H__
8 
9 /* LPAIF I2S */
10 
11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \
12 	(v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port))
13 
14 #define LPAIF_I2SCTL_REG(v, port)	LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port))
15 
16 #define LPAIF_I2SCTL_LOOPBACK_DISABLE	0
17 #define LPAIF_I2SCTL_LOOPBACK_ENABLE	1
18 
19 #define LPAIF_I2SCTL_SPKEN_DISABLE	0
20 #define LPAIF_I2SCTL_SPKEN_ENABLE	1
21 
22 #define LPAIF_I2SCTL_MODE_NONE		0
23 #define LPAIF_I2SCTL_MODE_SD0		1
24 #define LPAIF_I2SCTL_MODE_SD1		2
25 #define LPAIF_I2SCTL_MODE_SD2		3
26 #define LPAIF_I2SCTL_MODE_SD3		4
27 #define LPAIF_I2SCTL_MODE_QUAD01	5
28 #define LPAIF_I2SCTL_MODE_QUAD23	6
29 #define LPAIF_I2SCTL_MODE_6CH		7
30 #define LPAIF_I2SCTL_MODE_8CH		8
31 #define LPAIF_I2SCTL_MODE_10CH		9
32 #define LPAIF_I2SCTL_MODE_12CH		10
33 #define LPAIF_I2SCTL_MODE_14CH		11
34 #define LPAIF_I2SCTL_MODE_16CH		12
35 #define LPAIF_I2SCTL_MODE_SD4		13
36 #define LPAIF_I2SCTL_MODE_SD5		14
37 #define LPAIF_I2SCTL_MODE_SD6		15
38 #define LPAIF_I2SCTL_MODE_SD7		16
39 #define LPAIF_I2SCTL_MODE_QUAD45	17
40 #define LPAIF_I2SCTL_MODE_QUAD47	18
41 #define LPAIF_I2SCTL_MODE_8CH_2		19
42 
43 #define LPAIF_I2SCTL_SPKMODE(mode)	mode
44 
45 #define LPAIF_I2SCTL_SPKMONO_STEREO	0
46 #define LPAIF_I2SCTL_SPKMONO_MONO	1
47 
48 #define LPAIF_I2SCTL_MICEN_DISABLE	0
49 #define LPAIF_I2SCTL_MICEN_ENABLE	1
50 
51 #define LPAIF_I2SCTL_MICMODE(mode)	mode
52 
53 #define LPAIF_I2SCTL_MICMONO_STEREO	0
54 #define LPAIF_I2SCTL_MICMONO_MONO	1
55 
56 #define LPAIF_I2SCTL_WSSRC_INTERNAL	0
57 #define LPAIF_I2SCTL_WSSRC_EXTERNAL	1
58 
59 #define LPAIF_I2SCTL_BITWIDTH_16	0
60 #define LPAIF_I2SCTL_BITWIDTH_24	1
61 #define LPAIF_I2SCTL_BITWIDTH_32	2
62 
63 #define LPAIF_I2SCTL_RESET_STATE	0x003C0004
64 #define LPAIF_DMACTL_RESET_STATE	0x00200000
65 
66 
67 /* LPAIF IRQ */
68 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \
69 	(v->irq_reg_base + (addr) + v->irq_reg_stride * (port))
70 
71 #define LPAIF_IRQ_PORT_HOST		0
72 
73 #define LPAIF_IRQEN_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x0, (port))
74 #define LPAIF_IRQSTAT_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0x4, (port))
75 #define LPAIF_IRQCLEAR_REG(v, port)	LPAIF_IRQ_REG_ADDR(v, 0xC, (port))
76 
77 /* LPAIF RXTX IRQ */
78 #define LPAIF_RXTX_IRQ_REG_ADDR(v, addr, port) \
79 		(v->rxtx_irq_reg_base + (addr) + v->rxtx_irq_reg_stride * (port))
80 
81 #define LPAIF_RXTX_IRQEN_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x0, port)
82 #define LPAIF_RXTX_IRQSTAT_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0x4, port)
83 #define LPAIF_RXTX_IRQCLEAR_REG(v, port) LPAIF_RXTX_IRQ_REG_ADDR(v, 0xC, port)
84 
85 /* LPAIF VA IRQ */
86 #define LPAIF_VA_IRQ_REG_ADDR(v, addr, port) \
87 		(v->va_irq_reg_base + (addr) + v->va_irq_reg_stride * (port))
88 
89 #define LPAIF_VA_IRQEN_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x0, port)
90 #define LPAIF_VA_IRQSTAT_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0x4, port)
91 #define LPAIF_VA_IRQCLEAR_REG(v, port) LPAIF_VA_IRQ_REG_ADDR(v, 0xC, port)
92 
93 #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr)  \
94 	((v->hdmi_irq_reg_base) + (addr))
95 
96 #define LPASS_HDMITX_APP_IRQEN_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4)
97 #define LPASS_HDMITX_APP_IRQSTAT_REG(v)			LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8)
98 #define LPASS_HDMITX_APP_IRQCLEAR_REG(v)		LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC)
99 
100 #define LPAIF_IRQ_BITSTRIDE		3
101 
102 #define LPAIF_IRQ_PER(chan)		(1 << (LPAIF_IRQ_BITSTRIDE * (chan)))
103 #define LPAIF_IRQ_XRUN(chan)		(2 << (LPAIF_IRQ_BITSTRIDE * (chan)))
104 #define LPAIF_IRQ_ERR(chan)		(4 << (LPAIF_IRQ_BITSTRIDE * (chan)))
105 
106 #define LPAIF_IRQ_ALL(chan)		(7 << (LPAIF_IRQ_BITSTRIDE * (chan)))
107 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan)	(1 << (14 + chan))
108 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan)	(1 << (24 + chan))
109 #define LPAIF_IRQ_HDMI_METADONE		BIT(23)
110 
111 /* LPAIF DMA */
112 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \
113 	(v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan))
114 
115 #define LPAIF_HDMI_RDMACTL_AUDINTF(id)	(id << LPAIF_RDMACTL_AUDINTF_SHIFT)
116 
117 #define LPAIF_HDMI_RDMACTL_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan))
118 #define LPAIF_HDMI_RDMABASE_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan))
119 #define	LPAIF_HDMI_RDMABUFF_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan))
120 #define LPAIF_HDMI_RDMACURR_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan))
121 #define	LPAIF_HDMI_RDMAPER_REG(v, chan)		LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan))
122 #define	LPAIF_HDMI_RDMAPERCNT_REG(v, chan)	LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan))
123 
124 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \
125 	(v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan))
126 
127 #define LPAIF_RDMACTL_AUDINTF(id)	(id << LPAIF_RDMACTL_AUDINTF_SHIFT)
128 
129 #define LPAIF_RDMACTL_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x00, (chan))
130 #define LPAIF_RDMABASE_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x04, (chan))
131 #define	LPAIF_RDMABUFF_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x08, (chan))
132 #define LPAIF_RDMACURR_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan))
133 #define	LPAIF_RDMAPER_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x10, (chan))
134 #define	LPAIF_RDMAPERCNT_REG(v, chan)	LPAIF_RDMA_REG_ADDR(v, 0x14, (chan))
135 
136 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \
137 	(v->wrdma_reg_base + (addr) + \
138 	 v->wrdma_reg_stride * (chan - v->wrdma_channel_start))
139 
140 #define LPAIF_WRDMACTL_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan))
141 #define LPAIF_WRDMABASE_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan))
142 #define	LPAIF_WRDMABUFF_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan))
143 #define LPAIF_WRDMACURR_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan))
144 #define	LPAIF_WRDMAPER_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan))
145 #define	LPAIF_WRDMAPERCNT_REG(v, chan)	LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan))
146 
147 #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id)  \
148 	((dai_id ==  LPASS_DP_RX) ? \
149 		LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \
150 		 LPAIF_RDMA##reg##_REG(v, chan))
151 
152 #define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id)  \
153 	((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
154 		(LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \
155 		LPAIF_WRDMA##reg##_REG(v, chan))
156 
157 #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) \
158 	(is_cdc_dma_port(dai_id) ? \
159 	__LPAIF_CDC_DMA_REG(v, chan, dir, CTL, dai_id) : \
160 	__LPAIF_DMA_REG(v, chan, dir, CTL, dai_id))
161 #define LPAIF_DMABASE_REG(v, chan, dir, dai_id) \
162 	(is_cdc_dma_port(dai_id) ? \
163 	__LPAIF_CDC_DMA_REG(v, chan, dir, BASE, dai_id) : \
164 	__LPAIF_DMA_REG(v, chan, dir, BASE, dai_id))
165 #define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) \
166 	(is_cdc_dma_port(dai_id) ? \
167 	__LPAIF_CDC_DMA_REG(v, chan, dir, BUFF, dai_id) : \
168 	__LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id))
169 #define LPAIF_DMACURR_REG(v, chan, dir, dai_id) \
170 	(is_cdc_dma_port(dai_id) ? \
171 	__LPAIF_CDC_DMA_REG(v, chan, dir, CURR, dai_id) : \
172 	__LPAIF_DMA_REG(v, chan, dir, CURR, dai_id))
173 #define LPAIF_DMAPER_REG(v, chan, dir, dai_id)  \
174 	(is_cdc_dma_port(dai_id) ? \
175 	__LPAIF_CDC_DMA_REG(v, chan, dir, PER, dai_id) : \
176 	__LPAIF_DMA_REG(v, chan, dir, PER, dai_id))
177 #define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) \
178 	(is_cdc_dma_port(dai_id) ? \
179 	__LPAIF_CDC_DMA_REG(v, chan, dir, PERCNT, dai_id) : \
180 	__LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id))
181 
182 #define LPAIF_CDC_RDMA_REG_ADDR(v, addr, chan, dai_id) \
183 	(is_rxtx_cdc_dma_port(dai_id) ? \
184 	(v->rxtx_rdma_reg_base + (addr) + v->rxtx_rdma_reg_stride * (chan)) : \
185 	(v->va_rdma_reg_base + (addr) + v->va_rdma_reg_stride * (chan)))
186 
187 #define LPAIF_CDC_RXTX_RDMACTL_REG(v, chan, dai_id) \
188 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
189 #define LPAIF_CDC_RXTX_RDMABASE_REG(v, chan, dai_id) \
190 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
191 #define LPAIF_CDC_RXTX_RDMABUFF_REG(v, chan, dai_id) \
192 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
193 #define LPAIF_CDC_RXTX_RDMACURR_REG(v, chan, dai_id) \
194 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
195 #define LPAIF_CDC_RXTX_RDMAPER_REG(v, chan, dai_id) \
196 		LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
197 #define LPAIF_CDC_RXTX_RDMA_INTF_REG(v, chan, dai_id) \
198 	LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
199 
200 #define LPAIF_CDC_VA_RDMACTL_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x00, (chan), dai_id)
201 #define LPAIF_CDC_VA_RDMABASE_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x04, (chan), dai_id)
202 #define LPAIF_CDC_VA_RDMABUFF_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x08, (chan), dai_id)
203 #define LPAIF_CDC_VA_RDMACURR_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
204 #define LPAIF_CDC_VA_RDMAPER_REG(v, chan, dai_id) LPAIF_CDC_RDMA_REG_ADDR(v, 0x10, (chan), dai_id)
205 #define LPAIF_CDC_VA_RDMA_INTF_REG(v, chan, dai_id) \
206 	LPAIF_CDC_RDMA_REG_ADDR(v, 0x50, (chan), dai_id)
207 
208 #define LPAIF_CDC_WRDMA_REG_ADDR(v, addr, chan, dai_id) \
209 	(is_rxtx_cdc_dma_port(dai_id) ? \
210 	(v->rxtx_wrdma_reg_base + (addr) + \
211 		v->rxtx_wrdma_reg_stride * (chan - v->rxtx_wrdma_channel_start)) : \
212 	(v->va_wrdma_reg_base + (addr) + \
213 		v->va_wrdma_reg_stride * (chan - v->va_wrdma_channel_start)))
214 
215 #define LPAIF_CDC_RXTX_WRDMACTL_REG(v, chan, dai_id) \
216 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
217 #define LPAIF_CDC_RXTX_WRDMABASE_REG(v, chan, dai_id) \
218 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
219 #define LPAIF_CDC_RXTX_WRDMABUFF_REG(v, chan, dai_id) \
220 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
221 #define LPAIF_CDC_RXTX_WRDMACURR_REG(v, chan, dai_id) \
222 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
223 #define LPAIF_CDC_RXTX_WRDMAPER_REG(v, chan, dai_id) \
224 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
225 #define LPAIF_CDC_RXTX_WRDMA_INTF_REG(v, chan, dai_id) \
226 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
227 
228 #define LPAIF_CDC_VA_WRDMACTL_REG(v, chan, dai_id) \
229 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x00, (chan), dai_id)
230 #define LPAIF_CDC_VA_WRDMABASE_REG(v, chan, dai_id) \
231 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x04, (chan), dai_id)
232 #define LPAIF_CDC_VA_WRDMABUFF_REG(v, chan, dai_id) \
233 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x08, (chan), dai_id)
234 #define LPAIF_CDC_VA_WRDMACURR_REG(v, chan, dai_id) \
235 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x0C, (chan), dai_id)
236 #define LPAIF_CDC_VA_WRDMAPER_REG(v, chan, dai_id) \
237 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x10, (chan), dai_id)
238 #define LPAIF_CDC_VA_WRDMA_INTF_REG(v, chan, dai_id) \
239 	LPAIF_CDC_WRDMA_REG_ADDR(v, 0x50, (chan), dai_id)
240 
241 #define __LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) \
242 		(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_RDMA##reg##_REG(v, chan, dai_id) : \
243 			LPAIF_CDC_VA_RDMA##reg##_REG(v, chan, dai_id))
244 
245 #define __LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id) \
246 		(is_rxtx_cdc_dma_port(dai_id) ? LPAIF_CDC_RXTX_WRDMA##reg##_REG(v, chan, dai_id) : \
247 			LPAIF_CDC_VA_WRDMA##reg##_REG(v, chan, dai_id))
248 
249 #define __LPAIF_CDC_DMA_REG(v, chan, dir, reg, dai_id) \
250 		((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
251 			__LPAIF_CDC_RDDMA_REG(v, chan, dir, reg, dai_id) : \
252 			__LPAIF_CDC_WRDMA_REG(v, chan, dir, reg, dai_id))
253 
254 #define LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) \
255 		((dir ==  SNDRV_PCM_STREAM_PLAYBACK) ? \
256 		LPAIF_CDC_RDMA_INTF_REG(v, chan, dai_id) : \
257 		LPAIF_CDC_WRDMA_INTF_REG(v, chan, dai_id))
258 
259 #define LPAIF_INTF_REG(v, chan, dir, dai_id) \
260 		(is_cdc_dma_port(dai_id) ? \
261 		LPAIF_CDC_INTF_REG(v, chan, dir, dai_id) : \
262 		LPAIF_DMACTL_REG(v, chan, dir, dai_id))
263 
264 #define LPAIF_DMACTL_BURSTEN_SINGLE	0
265 #define LPAIF_DMACTL_BURSTEN_INCR4	1
266 
267 #define LPAIF_DMACTL_WPSCNT_ONE		0
268 #define LPAIF_DMACTL_WPSCNT_TWO		1
269 #define LPAIF_DMACTL_WPSCNT_THREE	2
270 #define LPAIF_DMACTL_WPSCNT_FOUR	3
271 #define LPAIF_DMACTL_WPSCNT_SIX		5
272 #define LPAIF_DMACTL_WPSCNT_EIGHT	7
273 #define LPAIF_DMACTL_WPSCNT_TEN		9
274 #define LPAIF_DMACTL_WPSCNT_TWELVE	11
275 #define LPAIF_DMACTL_WPSCNT_FOURTEEN	13
276 #define LPAIF_DMACTL_WPSCNT_SIXTEEN	15
277 
278 #define LPAIF_DMACTL_AUDINTF(id)	id
279 
280 #define LPAIF_DMACTL_FIFOWM_1		0
281 #define LPAIF_DMACTL_FIFOWM_2		1
282 #define LPAIF_DMACTL_FIFOWM_3		2
283 #define LPAIF_DMACTL_FIFOWM_4		3
284 #define LPAIF_DMACTL_FIFOWM_5		4
285 #define LPAIF_DMACTL_FIFOWM_6		5
286 #define LPAIF_DMACTL_FIFOWM_7		6
287 #define LPAIF_DMACTL_FIFOWM_8		7
288 #define LPAIF_DMACTL_FIFOWM_9		8
289 #define LPAIF_DMACTL_FIFOWM_10		9
290 #define LPAIF_DMACTL_FIFOWM_11		10
291 #define LPAIF_DMACTL_FIFOWM_12		11
292 #define LPAIF_DMACTL_FIFOWM_13		12
293 #define LPAIF_DMACTL_FIFOWM_14		13
294 #define LPAIF_DMACTL_FIFOWM_15		14
295 #define LPAIF_DMACTL_FIFOWM_16		15
296 #define LPAIF_DMACTL_FIFOWM_17		16
297 #define LPAIF_DMACTL_FIFOWM_18		17
298 #define LPAIF_DMACTL_FIFOWM_19		18
299 #define LPAIF_DMACTL_FIFOWM_20		19
300 #define LPAIF_DMACTL_FIFOWM_21		20
301 #define LPAIF_DMACTL_FIFOWM_22		21
302 #define LPAIF_DMACTL_FIFOWM_23		22
303 #define LPAIF_DMACTL_FIFOWM_24		23
304 #define LPAIF_DMACTL_FIFOWM_25		24
305 #define LPAIF_DMACTL_FIFOWM_26		25
306 #define LPAIF_DMACTL_FIFOWM_27		26
307 #define LPAIF_DMACTL_FIFOWM_28		27
308 #define LPAIF_DMACTL_FIFOWM_29		28
309 #define LPAIF_DMACTL_FIFOWM_30		29
310 #define LPAIF_DMACTL_FIFOWM_31		30
311 #define LPAIF_DMACTL_FIFOWM_32		31
312 
313 #define LPAIF_DMACTL_ENABLE_OFF		0
314 #define LPAIF_DMACTL_ENABLE_ON		1
315 
316 #define LPAIF_DMACTL_DYNCLK_OFF		0
317 #define LPAIF_DMACTL_DYNCLK_ON		1
318 
319 #endif /* __LPASS_LPAIF_REG_H__ */
320