1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
4 */
5 #include <linux/kernel.h>
6 #include <linux/module.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/regmap.h>
9 #include <linux/mutex.h>
10 #include <linux/mii.h>
11 #include <linux/of.h>
12 #include <linux/phy.h>
13 #include <linux/if_bridge.h>
14 #include <linux/if_vlan.h>
15 #include <linux/etherdevice.h>
16
17 #include "lan9303.h"
18
19 /* For the LAN9303 and LAN9354, only port 0 is an XMII port. */
20 #define IS_PORT_XMII(port) ((port) == 0)
21
22 #define LAN9303_NUM_PORTS 3
23
24 /* 13.2 System Control and Status Registers
25 * Multiply register number by 4 to get address offset.
26 */
27 #define LAN9303_CHIP_REV 0x14
28 # define LAN9303_CHIP_ID 0x9303
29 # define LAN9352_CHIP_ID 0x9352
30 # define LAN9353_CHIP_ID 0x9353
31 # define LAN9354_CHIP_ID 0x9354
32 # define LAN9355_CHIP_ID 0x9355
33 #define LAN9303_IRQ_CFG 0x15
34 # define LAN9303_IRQ_CFG_IRQ_ENABLE BIT(8)
35 # define LAN9303_IRQ_CFG_IRQ_POL BIT(4)
36 # define LAN9303_IRQ_CFG_IRQ_TYPE BIT(0)
37 #define LAN9303_INT_STS 0x16
38 # define LAN9303_INT_STS_PHY_INT2 BIT(27)
39 # define LAN9303_INT_STS_PHY_INT1 BIT(26)
40 #define LAN9303_INT_EN 0x17
41 # define LAN9303_INT_EN_PHY_INT2_EN BIT(27)
42 # define LAN9303_INT_EN_PHY_INT1_EN BIT(26)
43 #define LAN9303_BYTE_ORDER 0x19
44 #define LAN9303_HW_CFG 0x1D
45 # define LAN9303_HW_CFG_READY BIT(27)
46 # define LAN9303_HW_CFG_AMDX_EN_PORT2 BIT(26)
47 # define LAN9303_HW_CFG_AMDX_EN_PORT1 BIT(25)
48 #define LAN9303_PMI_DATA 0x29
49 #define LAN9303_PMI_ACCESS 0x2A
50 # define LAN9303_PMI_ACCESS_PHY_ADDR(x) (((x) & 0x1f) << 11)
51 # define LAN9303_PMI_ACCESS_MIIRINDA(x) (((x) & 0x1f) << 6)
52 # define LAN9303_PMI_ACCESS_MII_BUSY BIT(0)
53 # define LAN9303_PMI_ACCESS_MII_WRITE BIT(1)
54 #define LAN9303_MANUAL_FC_1 0x68
55 #define LAN9303_MANUAL_FC_2 0x69
56 #define LAN9303_MANUAL_FC_0 0x6a
57 # define LAN9303_BP_EN BIT(6)
58 # define LAN9303_RX_FC_EN BIT(2)
59 # define LAN9303_TX_FC_EN BIT(1)
60 #define LAN9303_SWITCH_CSR_DATA 0x6b
61 #define LAN9303_SWITCH_CSR_CMD 0x6c
62 #define LAN9303_SWITCH_CSR_CMD_BUSY BIT(31)
63 #define LAN9303_SWITCH_CSR_CMD_RW BIT(30)
64 #define LAN9303_SWITCH_CSR_CMD_LANES (BIT(19) | BIT(18) | BIT(17) | BIT(16))
65 #define LAN9303_VIRT_PHY_BASE 0x70
66 #define LAN9303_VIRT_SPECIAL_CTRL 0x77
67 #define LAN9303_VIRT_SPECIAL_TURBO BIT(10) /*Turbo MII Enable*/
68
69 /*13.4 Switch Fabric Control and Status Registers
70 * Accessed indirectly via SWITCH_CSR_CMD, SWITCH_CSR_DATA.
71 */
72 #define LAN9303_SW_DEV_ID 0x0000
73 #define LAN9303_SW_RESET 0x0001
74 #define LAN9303_SW_RESET_RESET BIT(0)
75 #define LAN9303_SW_IMR 0x0004
76 #define LAN9303_SW_IPR 0x0005
77 #define LAN9303_MAC_VER_ID_0 0x0400
78 #define LAN9303_MAC_RX_CFG_0 0x0401
79 # define LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES BIT(1)
80 # define LAN9303_MAC_RX_CFG_X_RX_ENABLE BIT(0)
81 #define LAN9303_MAC_RX_UNDSZE_CNT_0 0x0410
82 #define LAN9303_MAC_RX_64_CNT_0 0x0411
83 #define LAN9303_MAC_RX_127_CNT_0 0x0412
84 #define LAN9303_MAC_RX_255_CNT_0 0x413
85 #define LAN9303_MAC_RX_511_CNT_0 0x0414
86 #define LAN9303_MAC_RX_1023_CNT_0 0x0415
87 #define LAN9303_MAC_RX_MAX_CNT_0 0x0416
88 #define LAN9303_MAC_RX_OVRSZE_CNT_0 0x0417
89 #define LAN9303_MAC_RX_PKTOK_CNT_0 0x0418
90 #define LAN9303_MAC_RX_CRCERR_CNT_0 0x0419
91 #define LAN9303_MAC_RX_MULCST_CNT_0 0x041a
92 #define LAN9303_MAC_RX_BRDCST_CNT_0 0x041b
93 #define LAN9303_MAC_RX_PAUSE_CNT_0 0x041c
94 #define LAN9303_MAC_RX_FRAG_CNT_0 0x041d
95 #define LAN9303_MAC_RX_JABB_CNT_0 0x041e
96 #define LAN9303_MAC_RX_ALIGN_CNT_0 0x041f
97 #define LAN9303_MAC_RX_PKTLEN_CNT_0 0x0420
98 #define LAN9303_MAC_RX_GOODPKTLEN_CNT_0 0x0421
99 #define LAN9303_MAC_RX_SYMBL_CNT_0 0x0422
100 #define LAN9303_MAC_RX_CTLFRM_CNT_0 0x0423
101
102 #define LAN9303_MAC_TX_CFG_0 0x0440
103 # define LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT (21 << 2)
104 # define LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE BIT(1)
105 # define LAN9303_MAC_TX_CFG_X_TX_ENABLE BIT(0)
106 #define LAN9303_MAC_TX_DEFER_CNT_0 0x0451
107 #define LAN9303_MAC_TX_PAUSE_CNT_0 0x0452
108 #define LAN9303_MAC_TX_PKTOK_CNT_0 0x0453
109 #define LAN9303_MAC_TX_64_CNT_0 0x0454
110 #define LAN9303_MAC_TX_127_CNT_0 0x0455
111 #define LAN9303_MAC_TX_255_CNT_0 0x0456
112 #define LAN9303_MAC_TX_511_CNT_0 0x0457
113 #define LAN9303_MAC_TX_1023_CNT_0 0x0458
114 #define LAN9303_MAC_TX_MAX_CNT_0 0x0459
115 #define LAN9303_MAC_TX_UNDSZE_CNT_0 0x045a
116 #define LAN9303_MAC_TX_PKTLEN_CNT_0 0x045c
117 #define LAN9303_MAC_TX_BRDCST_CNT_0 0x045d
118 #define LAN9303_MAC_TX_MULCST_CNT_0 0x045e
119 #define LAN9303_MAC_TX_LATECOL_0 0x045f
120 #define LAN9303_MAC_TX_EXCOL_CNT_0 0x0460
121 #define LAN9303_MAC_TX_SNGLECOL_CNT_0 0x0461
122 #define LAN9303_MAC_TX_MULTICOL_CNT_0 0x0462
123 #define LAN9303_MAC_TX_TOTALCOL_CNT_0 0x0463
124
125 #define LAN9303_MAC_VER_ID_1 0x0800
126 #define LAN9303_MAC_RX_CFG_1 0x0801
127 #define LAN9303_MAC_TX_CFG_1 0x0840
128 #define LAN9303_MAC_VER_ID_2 0x0c00
129 #define LAN9303_MAC_RX_CFG_2 0x0c01
130 #define LAN9303_MAC_TX_CFG_2 0x0c40
131 #define LAN9303_SWE_ALR_CMD 0x1800
132 # define LAN9303_ALR_CMD_MAKE_ENTRY BIT(2)
133 # define LAN9303_ALR_CMD_GET_FIRST BIT(1)
134 # define LAN9303_ALR_CMD_GET_NEXT BIT(0)
135 #define LAN9303_SWE_ALR_WR_DAT_0 0x1801
136 #define LAN9303_SWE_ALR_WR_DAT_1 0x1802
137 # define LAN9303_ALR_DAT1_VALID BIT(26)
138 # define LAN9303_ALR_DAT1_END_OF_TABL BIT(25)
139 # define LAN9303_ALR_DAT1_AGE_OVERRID BIT(25)
140 # define LAN9303_ALR_DAT1_STATIC BIT(24)
141 # define LAN9303_ALR_DAT1_PORT_BITOFFS 16
142 # define LAN9303_ALR_DAT1_PORT_MASK (7 << LAN9303_ALR_DAT1_PORT_BITOFFS)
143 #define LAN9303_SWE_ALR_RD_DAT_0 0x1805
144 #define LAN9303_SWE_ALR_RD_DAT_1 0x1806
145 #define LAN9303_SWE_ALR_CMD_STS 0x1808
146 # define ALR_STS_MAKE_PEND BIT(0)
147 #define LAN9303_SWE_VLAN_CMD 0x180b
148 # define LAN9303_SWE_VLAN_CMD_RNW BIT(5)
149 # define LAN9303_SWE_VLAN_CMD_PVIDNVLAN BIT(4)
150 #define LAN9303_SWE_VLAN_WR_DATA 0x180c
151 #define LAN9303_SWE_VLAN_RD_DATA 0x180e
152 # define LAN9303_SWE_VLAN_MEMBER_PORT2 BIT(17)
153 # define LAN9303_SWE_VLAN_UNTAG_PORT2 BIT(16)
154 # define LAN9303_SWE_VLAN_MEMBER_PORT1 BIT(15)
155 # define LAN9303_SWE_VLAN_UNTAG_PORT1 BIT(14)
156 # define LAN9303_SWE_VLAN_MEMBER_PORT0 BIT(13)
157 # define LAN9303_SWE_VLAN_UNTAG_PORT0 BIT(12)
158 #define LAN9303_SWE_VLAN_CMD_STS 0x1810
159 #define LAN9303_SWE_GLB_INGRESS_CFG 0x1840
160 # define LAN9303_SWE_GLB_INGR_IGMP_TRAP BIT(7)
161 # define LAN9303_SWE_GLB_INGR_IGMP_PORT(p) BIT(10 + p)
162 #define LAN9303_SWE_PORT_STATE 0x1843
163 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT2 (0)
164 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT2 BIT(5)
165 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT2 BIT(4)
166 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT1 (0)
167 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT1 BIT(3)
168 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 BIT(2)
169 # define LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 (0)
170 # define LAN9303_SWE_PORT_STATE_LEARNING_PORT0 BIT(1)
171 # define LAN9303_SWE_PORT_STATE_BLOCKING_PORT0 BIT(0)
172 # define LAN9303_SWE_PORT_STATE_DISABLED_PORT0 (3)
173 #define LAN9303_SWE_PORT_MIRROR 0x1846
174 # define LAN9303_SWE_PORT_MIRROR_SNIFF_ALL BIT(8)
175 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT2 BIT(7)
176 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT1 BIT(6)
177 # define LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 BIT(5)
178 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 BIT(4)
179 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 BIT(3)
180 # define LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT0 BIT(2)
181 # define LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING BIT(1)
182 # define LAN9303_SWE_PORT_MIRROR_ENABLE_TX_MIRRORING BIT(0)
183 # define LAN9303_SWE_PORT_MIRROR_DISABLED 0
184 #define LAN9303_SWE_INGRESS_PORT_TYPE 0x1847
185 #define LAN9303_SWE_INGRESS_PORT_TYPE_VLAN 3
186 #define LAN9303_BM_CFG 0x1c00
187 #define LAN9303_BM_EGRSS_PORT_TYPE 0x1c0c
188 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT2 (BIT(17) | BIT(16))
189 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT1 (BIT(9) | BIT(8))
190 # define LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0 (BIT(1) | BIT(0))
191
192 #define LAN9303_SWITCH_PORT_REG(port, reg0) (0x400 * (port) + (reg0))
193
194 /* the built-in PHYs are of type LAN911X */
195 #define MII_LAN911X_SPECIAL_MODES 0x12
196 #define MII_LAN911X_SPECIAL_CONTROL_STATUS 0x1f
197
198 static const struct regmap_range lan9303_valid_regs[] = {
199 regmap_reg_range(0x14, 0x17), /* misc, interrupt */
200 regmap_reg_range(0x19, 0x19), /* endian test */
201 regmap_reg_range(0x1d, 0x1d), /* hardware config */
202 regmap_reg_range(0x23, 0x24), /* general purpose timer */
203 regmap_reg_range(0x27, 0x27), /* counter */
204 regmap_reg_range(0x29, 0x2a), /* PMI index regs */
205 regmap_reg_range(0x68, 0x6a), /* flow control */
206 regmap_reg_range(0x6b, 0x6c), /* switch fabric indirect regs */
207 regmap_reg_range(0x6d, 0x6f), /* misc */
208 regmap_reg_range(0x70, 0x77), /* virtual phy */
209 regmap_reg_range(0x78, 0x7a), /* GPIO */
210 regmap_reg_range(0x7c, 0x7e), /* MAC & reset */
211 regmap_reg_range(0x80, 0xb7), /* switch fabric direct regs (wr only) */
212 };
213
214 static const struct regmap_range lan9303_reserved_ranges[] = {
215 regmap_reg_range(0x00, 0x13),
216 regmap_reg_range(0x18, 0x18),
217 regmap_reg_range(0x1a, 0x1c),
218 regmap_reg_range(0x1e, 0x22),
219 regmap_reg_range(0x25, 0x26),
220 regmap_reg_range(0x28, 0x28),
221 regmap_reg_range(0x2b, 0x67),
222 regmap_reg_range(0x7b, 0x7b),
223 regmap_reg_range(0x7f, 0x7f),
224 regmap_reg_range(0xb8, 0xff),
225 };
226
227 const struct regmap_access_table lan9303_register_set = {
228 .yes_ranges = lan9303_valid_regs,
229 .n_yes_ranges = ARRAY_SIZE(lan9303_valid_regs),
230 .no_ranges = lan9303_reserved_ranges,
231 .n_no_ranges = ARRAY_SIZE(lan9303_reserved_ranges),
232 };
233 EXPORT_SYMBOL(lan9303_register_set);
234
235 /* Flow Control registers indexed by port number */
236 static unsigned int flow_ctl_reg[] = {
237 LAN9303_MANUAL_FC_0,
238 LAN9303_MANUAL_FC_1,
239 LAN9303_MANUAL_FC_2
240 };
241
lan9303_read(struct regmap * regmap,unsigned int offset,u32 * reg)242 static int lan9303_read(struct regmap *regmap, unsigned int offset, u32 *reg)
243 {
244 int ret, i;
245
246 /* we can lose arbitration for the I2C case, because the device
247 * tries to detect and read an external EEPROM after reset and acts as
248 * a master on the shared I2C bus itself. This conflicts with our
249 * attempts to access the device as a slave at the same moment.
250 */
251 for (i = 0; i < 5; i++) {
252 ret = regmap_read(regmap, offset, reg);
253 if (!ret)
254 return 0;
255 if (ret != -EAGAIN)
256 break;
257 msleep(500);
258 }
259
260 return -EIO;
261 }
262
lan9303_read_wait(struct lan9303 * chip,int offset,u32 mask)263 static int lan9303_read_wait(struct lan9303 *chip, int offset, u32 mask)
264 {
265 int i;
266
267 for (i = 0; i < 25; i++) {
268 u32 reg;
269 int ret;
270
271 ret = lan9303_read(chip->regmap, offset, ®);
272 if (ret) {
273 dev_err(chip->dev, "%s failed to read offset %d: %d\n",
274 __func__, offset, ret);
275 return ret;
276 }
277 if (!(reg & mask))
278 return 0;
279 usleep_range(1000, 2000);
280 }
281
282 return -ETIMEDOUT;
283 }
284
lan9303_virt_phy_reg_read(struct lan9303 * chip,int regnum)285 static int lan9303_virt_phy_reg_read(struct lan9303 *chip, int regnum)
286 {
287 int ret;
288 u32 val;
289
290 if (regnum > MII_EXPANSION)
291 return -EINVAL;
292
293 ret = lan9303_read(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, &val);
294 if (ret)
295 return ret;
296
297 return val & 0xffff;
298 }
299
lan9303_virt_phy_reg_write(struct lan9303 * chip,int regnum,u16 val)300 static int lan9303_virt_phy_reg_write(struct lan9303 *chip, int regnum, u16 val)
301 {
302 if (regnum > MII_EXPANSION)
303 return -EINVAL;
304
305 return regmap_write(chip->regmap, LAN9303_VIRT_PHY_BASE + regnum, val);
306 }
307
lan9303_indirect_phy_wait_for_completion(struct lan9303 * chip)308 static int lan9303_indirect_phy_wait_for_completion(struct lan9303 *chip)
309 {
310 return lan9303_read_wait(chip, LAN9303_PMI_ACCESS,
311 LAN9303_PMI_ACCESS_MII_BUSY);
312 }
313
lan9303_indirect_phy_read(struct lan9303 * chip,int addr,int regnum)314 static int lan9303_indirect_phy_read(struct lan9303 *chip, int addr, int regnum)
315 {
316 int ret;
317 u32 val;
318
319 val = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
320 val |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
321
322 mutex_lock(&chip->indirect_mutex);
323
324 ret = lan9303_indirect_phy_wait_for_completion(chip);
325 if (ret)
326 goto on_error;
327
328 /* start the MII read cycle */
329 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, val);
330 if (ret)
331 goto on_error;
332
333 ret = lan9303_indirect_phy_wait_for_completion(chip);
334 if (ret)
335 goto on_error;
336
337 /* read the result of this operation */
338 ret = lan9303_read(chip->regmap, LAN9303_PMI_DATA, &val);
339 if (ret)
340 goto on_error;
341
342 mutex_unlock(&chip->indirect_mutex);
343
344 return val & 0xffff;
345
346 on_error:
347 mutex_unlock(&chip->indirect_mutex);
348 return ret;
349 }
350
lan9303_indirect_phy_write(struct lan9303 * chip,int addr,int regnum,u16 val)351 static int lan9303_indirect_phy_write(struct lan9303 *chip, int addr,
352 int regnum, u16 val)
353 {
354 int ret;
355 u32 reg;
356
357 reg = LAN9303_PMI_ACCESS_PHY_ADDR(addr);
358 reg |= LAN9303_PMI_ACCESS_MIIRINDA(regnum);
359 reg |= LAN9303_PMI_ACCESS_MII_WRITE;
360
361 mutex_lock(&chip->indirect_mutex);
362
363 ret = lan9303_indirect_phy_wait_for_completion(chip);
364 if (ret)
365 goto on_error;
366
367 /* write the data first... */
368 ret = regmap_write(chip->regmap, LAN9303_PMI_DATA, val);
369 if (ret)
370 goto on_error;
371
372 /* ...then start the MII write cycle */
373 ret = regmap_write(chip->regmap, LAN9303_PMI_ACCESS, reg);
374
375 on_error:
376 mutex_unlock(&chip->indirect_mutex);
377 return ret;
378 }
379
380 const struct lan9303_phy_ops lan9303_indirect_phy_ops = {
381 .phy_read = lan9303_indirect_phy_read,
382 .phy_write = lan9303_indirect_phy_write,
383 };
384 EXPORT_SYMBOL_GPL(lan9303_indirect_phy_ops);
385
lan9303_switch_wait_for_completion(struct lan9303 * chip)386 static int lan9303_switch_wait_for_completion(struct lan9303 *chip)
387 {
388 return lan9303_read_wait(chip, LAN9303_SWITCH_CSR_CMD,
389 LAN9303_SWITCH_CSR_CMD_BUSY);
390 }
391
lan9303_write_switch_reg(struct lan9303 * chip,u16 regnum,u32 val)392 static int lan9303_write_switch_reg(struct lan9303 *chip, u16 regnum, u32 val)
393 {
394 u32 reg;
395 int ret;
396
397 reg = regnum;
398 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
399 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
400
401 mutex_lock(&chip->indirect_mutex);
402
403 ret = lan9303_switch_wait_for_completion(chip);
404 if (ret)
405 goto on_error;
406
407 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
408 if (ret) {
409 dev_err(chip->dev, "Failed to write csr data reg: %d\n", ret);
410 goto on_error;
411 }
412
413 /* trigger write */
414 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
415 if (ret)
416 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
417 ret);
418
419 on_error:
420 mutex_unlock(&chip->indirect_mutex);
421 return ret;
422 }
423
lan9303_read_switch_reg(struct lan9303 * chip,u16 regnum,u32 * val)424 static int lan9303_read_switch_reg(struct lan9303 *chip, u16 regnum, u32 *val)
425 {
426 u32 reg;
427 int ret;
428
429 reg = regnum;
430 reg |= LAN9303_SWITCH_CSR_CMD_LANES;
431 reg |= LAN9303_SWITCH_CSR_CMD_RW;
432 reg |= LAN9303_SWITCH_CSR_CMD_BUSY;
433
434 mutex_lock(&chip->indirect_mutex);
435
436 ret = lan9303_switch_wait_for_completion(chip);
437 if (ret)
438 goto on_error;
439
440 /* trigger read */
441 ret = regmap_write(chip->regmap, LAN9303_SWITCH_CSR_CMD, reg);
442 if (ret) {
443 dev_err(chip->dev, "Failed to write csr command reg: %d\n",
444 ret);
445 goto on_error;
446 }
447
448 ret = lan9303_switch_wait_for_completion(chip);
449 if (ret)
450 goto on_error;
451
452 ret = lan9303_read(chip->regmap, LAN9303_SWITCH_CSR_DATA, val);
453 if (ret)
454 dev_err(chip->dev, "Failed to read csr data reg: %d\n", ret);
455 on_error:
456 mutex_unlock(&chip->indirect_mutex);
457 return ret;
458 }
459
lan9303_write_switch_reg_mask(struct lan9303 * chip,u16 regnum,u32 val,u32 mask)460 static int lan9303_write_switch_reg_mask(struct lan9303 *chip, u16 regnum,
461 u32 val, u32 mask)
462 {
463 int ret;
464 u32 reg;
465
466 ret = lan9303_read_switch_reg(chip, regnum, ®);
467 if (ret)
468 return ret;
469
470 reg = (reg & ~mask) | val;
471
472 return lan9303_write_switch_reg(chip, regnum, reg);
473 }
474
lan9303_write_switch_port(struct lan9303 * chip,int port,u16 regnum,u32 val)475 static int lan9303_write_switch_port(struct lan9303 *chip, int port,
476 u16 regnum, u32 val)
477 {
478 return lan9303_write_switch_reg(
479 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
480 }
481
lan9303_read_switch_port(struct lan9303 * chip,int port,u16 regnum,u32 * val)482 static int lan9303_read_switch_port(struct lan9303 *chip, int port,
483 u16 regnum, u32 *val)
484 {
485 return lan9303_read_switch_reg(
486 chip, LAN9303_SWITCH_PORT_REG(port, regnum), val);
487 }
488
lan9303_detect_phy_setup(struct lan9303 * chip)489 static int lan9303_detect_phy_setup(struct lan9303 *chip)
490 {
491 int reg;
492
493 /* Calculate chip->phy_addr_base:
494 * Depending on the 'phy_addr_sel_strap' setting, the three phys are
495 * using IDs 0-1-2 or IDs 1-2-3. We cannot read back the
496 * 'phy_addr_sel_strap' setting directly, so we need a test, which
497 * configuration is active:
498 * Special reg 18 of phy 3 reads as 0x0000, if 'phy_addr_sel_strap' is 0
499 * and the IDs are 0-1-2, else it contains something different from
500 * 0x0000, which means 'phy_addr_sel_strap' is 1 and the IDs are 1-2-3.
501 * 0xffff is returned on MDIO read with no response.
502 */
503 reg = chip->ops->phy_read(chip, 3, MII_LAN911X_SPECIAL_MODES);
504 if (reg < 0) {
505 dev_err(chip->dev, "Failed to detect phy config: %d\n", reg);
506 return reg;
507 }
508
509 chip->phy_addr_base = reg != 0 && reg != 0xffff;
510
511 dev_dbg(chip->dev, "Phy setup '%s' detected\n",
512 chip->phy_addr_base ? "1-2-3" : "0-1-2");
513
514 return 0;
515 }
516
517 /* Map ALR-port bits to port bitmap, and back */
518 static const int alrport_2_portmap[] = {1, 2, 4, 0, 3, 5, 6, 7 };
519 static const int portmap_2_alrport[] = {3, 0, 1, 4, 2, 5, 6, 7 };
520
521 /* Return pointer to first free ALR cache entry, return NULL if none */
522 static struct lan9303_alr_cache_entry *
lan9303_alr_cache_find_free(struct lan9303 * chip)523 lan9303_alr_cache_find_free(struct lan9303 *chip)
524 {
525 int i;
526 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
527
528 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
529 if (entr->port_map == 0)
530 return entr;
531
532 return NULL;
533 }
534
535 /* Return pointer to ALR cache entry matching MAC address */
536 static struct lan9303_alr_cache_entry *
lan9303_alr_cache_find_mac(struct lan9303 * chip,const u8 * mac_addr)537 lan9303_alr_cache_find_mac(struct lan9303 *chip, const u8 *mac_addr)
538 {
539 int i;
540 struct lan9303_alr_cache_entry *entr = chip->alr_cache;
541
542 BUILD_BUG_ON_MSG(sizeof(struct lan9303_alr_cache_entry) & 1,
543 "ether_addr_equal require u16 alignment");
544
545 for (i = 0; i < LAN9303_NUM_ALR_RECORDS; i++, entr++)
546 if (ether_addr_equal(entr->mac_addr, mac_addr))
547 return entr;
548
549 return NULL;
550 }
551
lan9303_csr_reg_wait(struct lan9303 * chip,int regno,u32 mask)552 static int lan9303_csr_reg_wait(struct lan9303 *chip, int regno, u32 mask)
553 {
554 int i;
555
556 for (i = 0; i < 25; i++) {
557 u32 reg;
558
559 lan9303_read_switch_reg(chip, regno, ®);
560 if (!(reg & mask))
561 return 0;
562 usleep_range(1000, 2000);
563 }
564
565 return -ETIMEDOUT;
566 }
567
lan9303_alr_make_entry_raw(struct lan9303 * chip,u32 dat0,u32 dat1)568 static int lan9303_alr_make_entry_raw(struct lan9303 *chip, u32 dat0, u32 dat1)
569 {
570 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_0, dat0);
571 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_WR_DAT_1, dat1);
572 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
573 LAN9303_ALR_CMD_MAKE_ENTRY);
574 lan9303_csr_reg_wait(chip, LAN9303_SWE_ALR_CMD_STS, ALR_STS_MAKE_PEND);
575 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
576
577 return 0;
578 }
579
580 typedef int alr_loop_cb_t(struct lan9303 *chip, u32 dat0, u32 dat1,
581 int portmap, void *ctx);
582
lan9303_alr_loop(struct lan9303 * chip,alr_loop_cb_t * cb,void * ctx)583 static int lan9303_alr_loop(struct lan9303 *chip, alr_loop_cb_t *cb, void *ctx)
584 {
585 int ret = 0, i;
586
587 mutex_lock(&chip->alr_mutex);
588 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
589 LAN9303_ALR_CMD_GET_FIRST);
590 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
591
592 for (i = 1; i < LAN9303_NUM_ALR_RECORDS; i++) {
593 u32 dat0, dat1;
594 int alrport, portmap;
595
596 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_0, &dat0);
597 lan9303_read_switch_reg(chip, LAN9303_SWE_ALR_RD_DAT_1, &dat1);
598 if (dat1 & LAN9303_ALR_DAT1_END_OF_TABL)
599 break;
600
601 alrport = (dat1 & LAN9303_ALR_DAT1_PORT_MASK) >>
602 LAN9303_ALR_DAT1_PORT_BITOFFS;
603 portmap = alrport_2_portmap[alrport];
604
605 ret = cb(chip, dat0, dat1, portmap, ctx);
606 if (ret)
607 break;
608
609 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD,
610 LAN9303_ALR_CMD_GET_NEXT);
611 lan9303_write_switch_reg(chip, LAN9303_SWE_ALR_CMD, 0);
612 }
613 mutex_unlock(&chip->alr_mutex);
614
615 return ret;
616 }
617
alr_reg_to_mac(u32 dat0,u32 dat1,u8 mac[6])618 static void alr_reg_to_mac(u32 dat0, u32 dat1, u8 mac[6])
619 {
620 mac[0] = (dat0 >> 0) & 0xff;
621 mac[1] = (dat0 >> 8) & 0xff;
622 mac[2] = (dat0 >> 16) & 0xff;
623 mac[3] = (dat0 >> 24) & 0xff;
624 mac[4] = (dat1 >> 0) & 0xff;
625 mac[5] = (dat1 >> 8) & 0xff;
626 }
627
628 struct del_port_learned_ctx {
629 int port;
630 };
631
632 /* Clear learned (non-static) entry on given port */
alr_loop_cb_del_port_learned(struct lan9303 * chip,u32 dat0,u32 dat1,int portmap,void * ctx)633 static int alr_loop_cb_del_port_learned(struct lan9303 *chip, u32 dat0,
634 u32 dat1, int portmap, void *ctx)
635 {
636 struct del_port_learned_ctx *del_ctx = ctx;
637 int port = del_ctx->port;
638
639 if (((BIT(port) & portmap) == 0) || (dat1 & LAN9303_ALR_DAT1_STATIC))
640 return 0;
641
642 /* learned entries has only one port, we can just delete */
643 dat1 &= ~LAN9303_ALR_DAT1_VALID; /* delete entry */
644 lan9303_alr_make_entry_raw(chip, dat0, dat1);
645
646 return 0;
647 }
648
649 struct port_fdb_dump_ctx {
650 int port;
651 void *data;
652 dsa_fdb_dump_cb_t *cb;
653 };
654
alr_loop_cb_fdb_port_dump(struct lan9303 * chip,u32 dat0,u32 dat1,int portmap,void * ctx)655 static int alr_loop_cb_fdb_port_dump(struct lan9303 *chip, u32 dat0,
656 u32 dat1, int portmap, void *ctx)
657 {
658 struct port_fdb_dump_ctx *dump_ctx = ctx;
659 u8 mac[ETH_ALEN];
660 bool is_static;
661
662 if ((BIT(dump_ctx->port) & portmap) == 0)
663 return 0;
664
665 alr_reg_to_mac(dat0, dat1, mac);
666 is_static = !!(dat1 & LAN9303_ALR_DAT1_STATIC);
667 return dump_ctx->cb(mac, 0, is_static, dump_ctx->data);
668 }
669
670 /* Set a static ALR entry. Delete entry if port_map is zero */
lan9303_alr_set_entry(struct lan9303 * chip,const u8 * mac,u8 port_map,bool stp_override)671 static void lan9303_alr_set_entry(struct lan9303 *chip, const u8 *mac,
672 u8 port_map, bool stp_override)
673 {
674 u32 dat0, dat1, alr_port;
675
676 dev_dbg(chip->dev, "%s(%pM, %d)\n", __func__, mac, port_map);
677 dat1 = LAN9303_ALR_DAT1_STATIC;
678 if (port_map)
679 dat1 |= LAN9303_ALR_DAT1_VALID;
680 /* otherwise no ports: delete entry */
681 if (stp_override)
682 dat1 |= LAN9303_ALR_DAT1_AGE_OVERRID;
683
684 alr_port = portmap_2_alrport[port_map & 7];
685 dat1 &= ~LAN9303_ALR_DAT1_PORT_MASK;
686 dat1 |= alr_port << LAN9303_ALR_DAT1_PORT_BITOFFS;
687
688 dat0 = 0;
689 dat0 |= (mac[0] << 0);
690 dat0 |= (mac[1] << 8);
691 dat0 |= (mac[2] << 16);
692 dat0 |= (mac[3] << 24);
693
694 dat1 |= (mac[4] << 0);
695 dat1 |= (mac[5] << 8);
696
697 lan9303_alr_make_entry_raw(chip, dat0, dat1);
698 }
699
700 /* Add port to static ALR entry, create new static entry if needed */
lan9303_alr_add_port(struct lan9303 * chip,const u8 * mac,int port,bool stp_override)701 static int lan9303_alr_add_port(struct lan9303 *chip, const u8 *mac, int port,
702 bool stp_override)
703 {
704 struct lan9303_alr_cache_entry *entr;
705
706 mutex_lock(&chip->alr_mutex);
707 entr = lan9303_alr_cache_find_mac(chip, mac);
708 if (!entr) { /*New entry */
709 entr = lan9303_alr_cache_find_free(chip);
710 if (!entr) {
711 mutex_unlock(&chip->alr_mutex);
712 return -ENOSPC;
713 }
714 ether_addr_copy(entr->mac_addr, mac);
715 }
716 entr->port_map |= BIT(port);
717 entr->stp_override = stp_override;
718 lan9303_alr_set_entry(chip, mac, entr->port_map, stp_override);
719 mutex_unlock(&chip->alr_mutex);
720
721 return 0;
722 }
723
724 /* Delete static port from ALR entry, delete entry if last port */
lan9303_alr_del_port(struct lan9303 * chip,const u8 * mac,int port)725 static int lan9303_alr_del_port(struct lan9303 *chip, const u8 *mac, int port)
726 {
727 struct lan9303_alr_cache_entry *entr;
728
729 mutex_lock(&chip->alr_mutex);
730 entr = lan9303_alr_cache_find_mac(chip, mac);
731 if (!entr)
732 goto out; /* no static entry found */
733
734 entr->port_map &= ~BIT(port);
735 if (entr->port_map == 0) /* zero means its free again */
736 eth_zero_addr(entr->mac_addr);
737 lan9303_alr_set_entry(chip, mac, entr->port_map, entr->stp_override);
738
739 out:
740 mutex_unlock(&chip->alr_mutex);
741 return 0;
742 }
743
lan9303_disable_processing_port(struct lan9303 * chip,unsigned int port)744 static int lan9303_disable_processing_port(struct lan9303 *chip,
745 unsigned int port)
746 {
747 int ret;
748
749 /* disable RX, but keep register reset default values else */
750 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
751 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES);
752 if (ret)
753 return ret;
754
755 /* disable TX, but keep register reset default values else */
756 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
757 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
758 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE);
759 }
760
lan9303_enable_processing_port(struct lan9303 * chip,unsigned int port)761 static int lan9303_enable_processing_port(struct lan9303 *chip,
762 unsigned int port)
763 {
764 int ret;
765
766 /* enable RX and keep register reset default values else */
767 ret = lan9303_write_switch_port(chip, port, LAN9303_MAC_RX_CFG_0,
768 LAN9303_MAC_RX_CFG_X_REJECT_MAC_TYPES |
769 LAN9303_MAC_RX_CFG_X_RX_ENABLE);
770 if (ret)
771 return ret;
772
773 /* enable TX and keep register reset default values else */
774 return lan9303_write_switch_port(chip, port, LAN9303_MAC_TX_CFG_0,
775 LAN9303_MAC_TX_CFG_X_TX_IFG_CONFIG_DEFAULT |
776 LAN9303_MAC_TX_CFG_X_TX_PAD_ENABLE |
777 LAN9303_MAC_TX_CFG_X_TX_ENABLE);
778 }
779
780 /* forward special tagged packets from port 0 to port 1 *or* port 2 */
lan9303_setup_tagging(struct lan9303 * chip)781 static int lan9303_setup_tagging(struct lan9303 *chip)
782 {
783 int ret;
784 u32 val;
785 /* enable defining the destination port via special VLAN tagging
786 * for port 0
787 */
788 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_INGRESS_PORT_TYPE,
789 LAN9303_SWE_INGRESS_PORT_TYPE_VLAN);
790 if (ret)
791 return ret;
792
793 /* tag incoming packets at port 1 and 2 on their way to port 0 to be
794 * able to discover their source port
795 */
796 val = LAN9303_BM_EGRSS_PORT_TYPE_SPECIAL_TAG_PORT0;
797 return lan9303_write_switch_reg(chip, LAN9303_BM_EGRSS_PORT_TYPE, val);
798 }
799
800 /* We want a special working switch:
801 * - do not forward packets between port 1 and 2
802 * - forward everything from port 1 to port 0
803 * - forward everything from port 2 to port 0
804 */
lan9303_separate_ports(struct lan9303 * chip)805 static int lan9303_separate_ports(struct lan9303 *chip)
806 {
807 int ret;
808
809 lan9303_alr_del_port(chip, eth_stp_addr, 0);
810 ret = lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
811 LAN9303_SWE_PORT_MIRROR_SNIFFER_PORT0 |
812 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT1 |
813 LAN9303_SWE_PORT_MIRROR_MIRRORED_PORT2 |
814 LAN9303_SWE_PORT_MIRROR_ENABLE_RX_MIRRORING |
815 LAN9303_SWE_PORT_MIRROR_SNIFF_ALL);
816 if (ret)
817 return ret;
818
819 /* prevent port 1 and 2 from forwarding packets by their own */
820 return lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
821 LAN9303_SWE_PORT_STATE_FORWARDING_PORT0 |
822 LAN9303_SWE_PORT_STATE_BLOCKING_PORT1 |
823 LAN9303_SWE_PORT_STATE_BLOCKING_PORT2);
824 }
825
lan9303_bridge_ports(struct lan9303 * chip)826 static void lan9303_bridge_ports(struct lan9303 *chip)
827 {
828 /* ports bridged: remove mirroring */
829 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_MIRROR,
830 LAN9303_SWE_PORT_MIRROR_DISABLED);
831
832 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
833 chip->swe_port_state);
834 lan9303_alr_add_port(chip, eth_stp_addr, 0, true);
835 }
836
lan9303_handle_reset(struct lan9303 * chip)837 static void lan9303_handle_reset(struct lan9303 *chip)
838 {
839 if (!chip->reset_gpio)
840 return;
841
842 if (chip->reset_duration != 0)
843 msleep(chip->reset_duration);
844
845 /* release (deassert) reset and activate the device */
846 gpiod_set_value_cansleep(chip->reset_gpio, 0);
847 }
848
849 /* stop processing packets for all ports */
lan9303_disable_processing(struct lan9303 * chip)850 static int lan9303_disable_processing(struct lan9303 *chip)
851 {
852 int p;
853
854 for (p = 1; p < LAN9303_NUM_PORTS; p++) {
855 int ret = lan9303_disable_processing_port(chip, p);
856
857 if (ret)
858 return ret;
859 }
860
861 return 0;
862 }
863
lan9303_check_device(struct lan9303 * chip)864 static int lan9303_check_device(struct lan9303 *chip)
865 {
866 int ret;
867 u32 reg;
868
869 ret = lan9303_read(chip->regmap, LAN9303_CHIP_REV, ®);
870 if (ret) {
871 dev_err(chip->dev, "failed to read chip revision register: %d\n",
872 ret);
873 return ret;
874 }
875
876 if (((reg >> 16) != LAN9303_CHIP_ID) &&
877 ((reg >> 16) != LAN9354_CHIP_ID)) {
878 dev_err(chip->dev, "unexpected device found: LAN%4.4X\n",
879 reg >> 16);
880 return -ENODEV;
881 }
882
883 /* The default state of the LAN9303 device is to forward packets between
884 * all ports (if not configured differently by an external EEPROM).
885 * The initial state of a DSA device must be forwarding packets only
886 * between the external and the internal ports and no forwarding
887 * between the external ports. In preparation we stop packet handling
888 * at all for now until the LAN9303 device is re-programmed accordingly.
889 */
890 ret = lan9303_disable_processing(chip);
891 if (ret)
892 dev_warn(chip->dev, "failed to disable switching %d\n", ret);
893
894 dev_info(chip->dev, "Found LAN%4.4X rev. %u\n", (reg >> 16), reg & 0xffff);
895
896 ret = lan9303_detect_phy_setup(chip);
897 if (ret) {
898 dev_err(chip->dev,
899 "failed to discover phy bootstrap setup: %d\n", ret);
900 return ret;
901 }
902
903 return 0;
904 }
905
906 /* ---------------------------- DSA -----------------------------------*/
907
lan9303_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)908 static enum dsa_tag_protocol lan9303_get_tag_protocol(struct dsa_switch *ds,
909 int port,
910 enum dsa_tag_protocol mp)
911 {
912 return DSA_TAG_PROTO_LAN9303;
913 }
914
lan9303_setup(struct dsa_switch * ds)915 static int lan9303_setup(struct dsa_switch *ds)
916 {
917 struct lan9303 *chip = ds->priv;
918 int ret;
919 u32 reg;
920
921 /* Make sure that port 0 is the cpu port */
922 if (!dsa_is_cpu_port(ds, 0)) {
923 dev_err(chip->dev, "port 0 is not the CPU port\n");
924 return -EINVAL;
925 }
926
927 /* Virtual Phy: Remove Turbo 200Mbit mode */
928 ret = lan9303_read(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, ®);
929 if (ret)
930 return (ret);
931
932 /* Clear the TURBO Mode bit if it was set. */
933 if (reg & LAN9303_VIRT_SPECIAL_TURBO) {
934 reg &= ~LAN9303_VIRT_SPECIAL_TURBO;
935 regmap_write(chip->regmap, LAN9303_VIRT_SPECIAL_CTRL, reg);
936 }
937
938 ret = lan9303_setup_tagging(chip);
939 if (ret)
940 dev_err(chip->dev, "failed to setup port tagging %d\n", ret);
941
942 ret = lan9303_separate_ports(chip);
943 if (ret)
944 dev_err(chip->dev, "failed to separate ports %d\n", ret);
945
946 ret = lan9303_enable_processing_port(chip, 0);
947 if (ret)
948 dev_err(chip->dev, "failed to re-enable switching %d\n", ret);
949
950 /* Trap IGMP to port 0 */
951 ret = lan9303_write_switch_reg_mask(chip, LAN9303_SWE_GLB_INGRESS_CFG,
952 LAN9303_SWE_GLB_INGR_IGMP_TRAP |
953 LAN9303_SWE_GLB_INGR_IGMP_PORT(0),
954 LAN9303_SWE_GLB_INGR_IGMP_PORT(1) |
955 LAN9303_SWE_GLB_INGR_IGMP_PORT(2));
956 if (ret)
957 dev_err(chip->dev, "failed to setup IGMP trap %d\n", ret);
958
959 return 0;
960 }
961
962 struct lan9303_mib_desc {
963 unsigned int offset; /* offset of first MAC */
964 const char *name;
965 };
966
967 static const struct lan9303_mib_desc lan9303_mib[] = {
968 { .offset = LAN9303_MAC_RX_BRDCST_CNT_0, .name = "RxBroad", },
969 { .offset = LAN9303_MAC_RX_PAUSE_CNT_0, .name = "RxPause", },
970 { .offset = LAN9303_MAC_RX_MULCST_CNT_0, .name = "RxMulti", },
971 { .offset = LAN9303_MAC_RX_PKTOK_CNT_0, .name = "RxOk", },
972 { .offset = LAN9303_MAC_RX_CRCERR_CNT_0, .name = "RxCrcErr", },
973 { .offset = LAN9303_MAC_RX_ALIGN_CNT_0, .name = "RxAlignErr", },
974 { .offset = LAN9303_MAC_RX_JABB_CNT_0, .name = "RxJabber", },
975 { .offset = LAN9303_MAC_RX_FRAG_CNT_0, .name = "RxFragment", },
976 { .offset = LAN9303_MAC_RX_64_CNT_0, .name = "Rx64Byte", },
977 { .offset = LAN9303_MAC_RX_127_CNT_0, .name = "Rx128Byte", },
978 { .offset = LAN9303_MAC_RX_255_CNT_0, .name = "Rx256Byte", },
979 { .offset = LAN9303_MAC_RX_511_CNT_0, .name = "Rx512Byte", },
980 { .offset = LAN9303_MAC_RX_1023_CNT_0, .name = "Rx1024Byte", },
981 { .offset = LAN9303_MAC_RX_MAX_CNT_0, .name = "RxMaxByte", },
982 { .offset = LAN9303_MAC_RX_PKTLEN_CNT_0, .name = "RxByteCnt", },
983 { .offset = LAN9303_MAC_RX_SYMBL_CNT_0, .name = "RxSymbolCnt", },
984 { .offset = LAN9303_MAC_RX_CTLFRM_CNT_0, .name = "RxCfs", },
985 { .offset = LAN9303_MAC_RX_OVRSZE_CNT_0, .name = "RxOverFlow", },
986 { .offset = LAN9303_MAC_TX_UNDSZE_CNT_0, .name = "TxShort", },
987 { .offset = LAN9303_MAC_TX_BRDCST_CNT_0, .name = "TxBroad", },
988 { .offset = LAN9303_MAC_TX_PAUSE_CNT_0, .name = "TxPause", },
989 { .offset = LAN9303_MAC_TX_MULCST_CNT_0, .name = "TxMulti", },
990 { .offset = LAN9303_MAC_RX_UNDSZE_CNT_0, .name = "RxShort", },
991 { .offset = LAN9303_MAC_TX_64_CNT_0, .name = "Tx64Byte", },
992 { .offset = LAN9303_MAC_TX_127_CNT_0, .name = "Tx128Byte", },
993 { .offset = LAN9303_MAC_TX_255_CNT_0, .name = "Tx256Byte", },
994 { .offset = LAN9303_MAC_TX_511_CNT_0, .name = "Tx512Byte", },
995 { .offset = LAN9303_MAC_TX_1023_CNT_0, .name = "Tx1024Byte", },
996 { .offset = LAN9303_MAC_TX_MAX_CNT_0, .name = "TxMaxByte", },
997 { .offset = LAN9303_MAC_TX_PKTLEN_CNT_0, .name = "TxByteCnt", },
998 { .offset = LAN9303_MAC_TX_PKTOK_CNT_0, .name = "TxOk", },
999 { .offset = LAN9303_MAC_TX_TOTALCOL_CNT_0, .name = "TxCollision", },
1000 { .offset = LAN9303_MAC_TX_MULTICOL_CNT_0, .name = "TxMultiCol", },
1001 { .offset = LAN9303_MAC_TX_SNGLECOL_CNT_0, .name = "TxSingleCol", },
1002 { .offset = LAN9303_MAC_TX_EXCOL_CNT_0, .name = "TxExcCol", },
1003 { .offset = LAN9303_MAC_TX_DEFER_CNT_0, .name = "TxDefer", },
1004 { .offset = LAN9303_MAC_TX_LATECOL_0, .name = "TxLateCol", },
1005 };
1006
lan9303_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)1007 static void lan9303_get_strings(struct dsa_switch *ds, int port,
1008 u32 stringset, uint8_t *data)
1009 {
1010 unsigned int u;
1011
1012 if (stringset != ETH_SS_STATS)
1013 return;
1014
1015 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
1016 strncpy(data + u * ETH_GSTRING_LEN, lan9303_mib[u].name,
1017 ETH_GSTRING_LEN);
1018 }
1019 }
1020
lan9303_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1021 static void lan9303_get_ethtool_stats(struct dsa_switch *ds, int port,
1022 uint64_t *data)
1023 {
1024 struct lan9303 *chip = ds->priv;
1025 unsigned int u;
1026
1027 for (u = 0; u < ARRAY_SIZE(lan9303_mib); u++) {
1028 u32 reg;
1029 int ret;
1030
1031 ret = lan9303_read_switch_port(
1032 chip, port, lan9303_mib[u].offset, ®);
1033
1034 if (ret) {
1035 dev_warn(chip->dev, "Reading status port %d reg %u failed\n",
1036 port, lan9303_mib[u].offset);
1037 reg = 0;
1038 }
1039 data[u] = reg;
1040 }
1041 }
1042
lan9303_get_sset_count(struct dsa_switch * ds,int port,int sset)1043 static int lan9303_get_sset_count(struct dsa_switch *ds, int port, int sset)
1044 {
1045 if (sset != ETH_SS_STATS)
1046 return 0;
1047
1048 return ARRAY_SIZE(lan9303_mib);
1049 }
1050
lan9303_phy_read(struct dsa_switch * ds,int port,int regnum)1051 static int lan9303_phy_read(struct dsa_switch *ds, int port, int regnum)
1052 {
1053 struct lan9303 *chip = ds->priv;
1054 int phy_base = chip->phy_addr_base;
1055
1056 if (port == 0)
1057 return lan9303_virt_phy_reg_read(chip, regnum);
1058 if (port > 2)
1059 return -ENODEV;
1060
1061 return chip->ops->phy_read(chip, phy_base + port, regnum);
1062 }
1063
lan9303_phy_write(struct dsa_switch * ds,int port,int regnum,u16 val)1064 static int lan9303_phy_write(struct dsa_switch *ds, int port, int regnum,
1065 u16 val)
1066 {
1067 struct lan9303 *chip = ds->priv;
1068 int phy_base = chip->phy_addr_base;
1069
1070 if (port == 0)
1071 return lan9303_virt_phy_reg_write(chip, regnum, val);
1072 if (port > 2)
1073 return -ENODEV;
1074
1075 return chip->ops->phy_write(chip, phy_base + port, regnum, val);
1076 }
1077
lan9303_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)1078 static int lan9303_port_enable(struct dsa_switch *ds, int port,
1079 struct phy_device *phy)
1080 {
1081 struct dsa_port *dp = dsa_to_port(ds, port);
1082 struct lan9303 *chip = ds->priv;
1083
1084 if (!dsa_port_is_user(dp))
1085 return 0;
1086
1087 vlan_vid_add(dsa_port_to_master(dp), htons(ETH_P_8021Q), port);
1088
1089 return lan9303_enable_processing_port(chip, port);
1090 }
1091
lan9303_port_disable(struct dsa_switch * ds,int port)1092 static void lan9303_port_disable(struct dsa_switch *ds, int port)
1093 {
1094 struct dsa_port *dp = dsa_to_port(ds, port);
1095 struct lan9303 *chip = ds->priv;
1096
1097 if (!dsa_port_is_user(dp))
1098 return;
1099
1100 vlan_vid_del(dsa_port_to_master(dp), htons(ETH_P_8021Q), port);
1101
1102 lan9303_disable_processing_port(chip, port);
1103 lan9303_phy_write(ds, port, MII_BMCR, BMCR_PDOWN);
1104 }
1105
lan9303_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)1106 static int lan9303_port_bridge_join(struct dsa_switch *ds, int port,
1107 struct dsa_bridge bridge,
1108 bool *tx_fwd_offload,
1109 struct netlink_ext_ack *extack)
1110 {
1111 struct lan9303 *chip = ds->priv;
1112
1113 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1114 if (dsa_port_bridge_same(dsa_to_port(ds, 1), dsa_to_port(ds, 2))) {
1115 lan9303_bridge_ports(chip);
1116 chip->is_bridged = true; /* unleash stp_state_set() */
1117 }
1118
1119 return 0;
1120 }
1121
lan9303_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)1122 static void lan9303_port_bridge_leave(struct dsa_switch *ds, int port,
1123 struct dsa_bridge bridge)
1124 {
1125 struct lan9303 *chip = ds->priv;
1126
1127 dev_dbg(chip->dev, "%s(port %d)\n", __func__, port);
1128 if (chip->is_bridged) {
1129 lan9303_separate_ports(chip);
1130 chip->is_bridged = false;
1131 }
1132 }
1133
lan9303_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)1134 static void lan9303_port_stp_state_set(struct dsa_switch *ds, int port,
1135 u8 state)
1136 {
1137 int portmask, portstate;
1138 struct lan9303 *chip = ds->priv;
1139
1140 dev_dbg(chip->dev, "%s(port %d, state %d)\n",
1141 __func__, port, state);
1142
1143 switch (state) {
1144 case BR_STATE_DISABLED:
1145 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1146 break;
1147 case BR_STATE_BLOCKING:
1148 case BR_STATE_LISTENING:
1149 portstate = LAN9303_SWE_PORT_STATE_BLOCKING_PORT0;
1150 break;
1151 case BR_STATE_LEARNING:
1152 portstate = LAN9303_SWE_PORT_STATE_LEARNING_PORT0;
1153 break;
1154 case BR_STATE_FORWARDING:
1155 portstate = LAN9303_SWE_PORT_STATE_FORWARDING_PORT0;
1156 break;
1157 default:
1158 portstate = LAN9303_SWE_PORT_STATE_DISABLED_PORT0;
1159 dev_err(chip->dev, "unknown stp state: port %d, state %d\n",
1160 port, state);
1161 }
1162
1163 portmask = 0x3 << (port * 2);
1164 portstate <<= (port * 2);
1165
1166 chip->swe_port_state = (chip->swe_port_state & ~portmask) | portstate;
1167
1168 if (chip->is_bridged)
1169 lan9303_write_switch_reg(chip, LAN9303_SWE_PORT_STATE,
1170 chip->swe_port_state);
1171 /* else: touching SWE_PORT_STATE would break port separation */
1172 }
1173
lan9303_port_fast_age(struct dsa_switch * ds,int port)1174 static void lan9303_port_fast_age(struct dsa_switch *ds, int port)
1175 {
1176 struct lan9303 *chip = ds->priv;
1177 struct del_port_learned_ctx del_ctx = {
1178 .port = port,
1179 };
1180
1181 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1182 lan9303_alr_loop(chip, alr_loop_cb_del_port_learned, &del_ctx);
1183 }
1184
lan9303_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1185 static int lan9303_port_fdb_add(struct dsa_switch *ds, int port,
1186 const unsigned char *addr, u16 vid,
1187 struct dsa_db db)
1188 {
1189 struct lan9303 *chip = ds->priv;
1190
1191 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1192
1193 return lan9303_alr_add_port(chip, addr, port, false);
1194 }
1195
lan9303_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)1196 static int lan9303_port_fdb_del(struct dsa_switch *ds, int port,
1197 const unsigned char *addr, u16 vid,
1198 struct dsa_db db)
1199 {
1200 struct lan9303 *chip = ds->priv;
1201
1202 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, addr, vid);
1203 lan9303_alr_del_port(chip, addr, port);
1204
1205 return 0;
1206 }
1207
lan9303_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)1208 static int lan9303_port_fdb_dump(struct dsa_switch *ds, int port,
1209 dsa_fdb_dump_cb_t *cb, void *data)
1210 {
1211 struct lan9303 *chip = ds->priv;
1212 struct port_fdb_dump_ctx dump_ctx = {
1213 .port = port,
1214 .data = data,
1215 .cb = cb,
1216 };
1217
1218 dev_dbg(chip->dev, "%s(%d)\n", __func__, port);
1219 return lan9303_alr_loop(chip, alr_loop_cb_fdb_port_dump, &dump_ctx);
1220 }
1221
lan9303_port_mdb_prepare(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb)1222 static int lan9303_port_mdb_prepare(struct dsa_switch *ds, int port,
1223 const struct switchdev_obj_port_mdb *mdb)
1224 {
1225 struct lan9303 *chip = ds->priv;
1226
1227 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1228 mdb->vid);
1229 if (mdb->vid)
1230 return -EOPNOTSUPP;
1231 if (lan9303_alr_cache_find_mac(chip, mdb->addr))
1232 return 0;
1233 if (!lan9303_alr_cache_find_free(chip))
1234 return -ENOSPC;
1235
1236 return 0;
1237 }
1238
lan9303_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1239 static int lan9303_port_mdb_add(struct dsa_switch *ds, int port,
1240 const struct switchdev_obj_port_mdb *mdb,
1241 struct dsa_db db)
1242 {
1243 struct lan9303 *chip = ds->priv;
1244 int err;
1245
1246 err = lan9303_port_mdb_prepare(ds, port, mdb);
1247 if (err)
1248 return err;
1249
1250 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1251 mdb->vid);
1252 return lan9303_alr_add_port(chip, mdb->addr, port, false);
1253 }
1254
lan9303_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)1255 static int lan9303_port_mdb_del(struct dsa_switch *ds, int port,
1256 const struct switchdev_obj_port_mdb *mdb,
1257 struct dsa_db db)
1258 {
1259 struct lan9303 *chip = ds->priv;
1260
1261 dev_dbg(chip->dev, "%s(%d, %pM, %d)\n", __func__, port, mdb->addr,
1262 mdb->vid);
1263 if (mdb->vid)
1264 return -EOPNOTSUPP;
1265 lan9303_alr_del_port(chip, mdb->addr, port);
1266
1267 return 0;
1268 }
1269
lan9303_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1270 static void lan9303_phylink_get_caps(struct dsa_switch *ds, int port,
1271 struct phylink_config *config)
1272 {
1273 struct lan9303 *chip = ds->priv;
1274
1275 dev_dbg(chip->dev, "%s(%d) entered.", __func__, port);
1276
1277 config->mac_capabilities = MAC_10 | MAC_100 | MAC_ASYM_PAUSE |
1278 MAC_SYM_PAUSE;
1279
1280 if (port == 0) {
1281 __set_bit(PHY_INTERFACE_MODE_RMII,
1282 config->supported_interfaces);
1283 __set_bit(PHY_INTERFACE_MODE_MII,
1284 config->supported_interfaces);
1285 } else {
1286 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1287 config->supported_interfaces);
1288 /* Compatibility for phylib's default interface type when the
1289 * phy-mode property is absent
1290 */
1291 __set_bit(PHY_INTERFACE_MODE_GMII,
1292 config->supported_interfaces);
1293 }
1294 }
1295
lan9303_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)1296 static void lan9303_phylink_mac_link_up(struct dsa_switch *ds, int port,
1297 unsigned int mode,
1298 phy_interface_t interface,
1299 struct phy_device *phydev, int speed,
1300 int duplex, bool tx_pause,
1301 bool rx_pause)
1302 {
1303 struct lan9303 *chip = ds->priv;
1304 u32 ctl;
1305 u32 reg;
1306
1307 /* On this device, we are only interested in doing something here if
1308 * this is the xMII port. All other ports are 10/100 phys using MDIO
1309 * to control there link settings.
1310 */
1311 if (!IS_PORT_XMII(port))
1312 return;
1313
1314 /* Disable auto-negotiation and force the speed/duplex settings. */
1315 ctl = lan9303_phy_read(ds, port, MII_BMCR);
1316 ctl &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX);
1317 if (speed == SPEED_100)
1318 ctl |= BMCR_SPEED100;
1319 if (duplex == DUPLEX_FULL)
1320 ctl |= BMCR_FULLDPLX;
1321 lan9303_phy_write(ds, port, MII_BMCR, ctl);
1322
1323 /* Force the flow control settings. */
1324 lan9303_read(chip->regmap, flow_ctl_reg[port], ®);
1325 reg &= ~(LAN9303_BP_EN | LAN9303_RX_FC_EN | LAN9303_TX_FC_EN);
1326 if (rx_pause)
1327 reg |= (LAN9303_RX_FC_EN | LAN9303_BP_EN);
1328 if (tx_pause)
1329 reg |= LAN9303_TX_FC_EN;
1330 regmap_write(chip->regmap, flow_ctl_reg[port], reg);
1331 }
1332
1333 static const struct dsa_switch_ops lan9303_switch_ops = {
1334 .get_tag_protocol = lan9303_get_tag_protocol,
1335 .setup = lan9303_setup,
1336 .get_strings = lan9303_get_strings,
1337 .phy_read = lan9303_phy_read,
1338 .phy_write = lan9303_phy_write,
1339 .phylink_get_caps = lan9303_phylink_get_caps,
1340 .phylink_mac_link_up = lan9303_phylink_mac_link_up,
1341 .get_ethtool_stats = lan9303_get_ethtool_stats,
1342 .get_sset_count = lan9303_get_sset_count,
1343 .port_enable = lan9303_port_enable,
1344 .port_disable = lan9303_port_disable,
1345 .port_bridge_join = lan9303_port_bridge_join,
1346 .port_bridge_leave = lan9303_port_bridge_leave,
1347 .port_stp_state_set = lan9303_port_stp_state_set,
1348 .port_fast_age = lan9303_port_fast_age,
1349 .port_fdb_add = lan9303_port_fdb_add,
1350 .port_fdb_del = lan9303_port_fdb_del,
1351 .port_fdb_dump = lan9303_port_fdb_dump,
1352 .port_mdb_add = lan9303_port_mdb_add,
1353 .port_mdb_del = lan9303_port_mdb_del,
1354 };
1355
lan9303_register_switch(struct lan9303 * chip)1356 static int lan9303_register_switch(struct lan9303 *chip)
1357 {
1358 chip->ds = devm_kzalloc(chip->dev, sizeof(*chip->ds), GFP_KERNEL);
1359 if (!chip->ds)
1360 return -ENOMEM;
1361
1362 chip->ds->dev = chip->dev;
1363 chip->ds->num_ports = LAN9303_NUM_PORTS;
1364 chip->ds->priv = chip;
1365 chip->ds->ops = &lan9303_switch_ops;
1366 chip->ds->phys_mii_mask = GENMASK(LAN9303_NUM_PORTS - 1, 0);
1367
1368 return dsa_register_switch(chip->ds);
1369 }
1370
lan9303_probe_reset_gpio(struct lan9303 * chip,struct device_node * np)1371 static int lan9303_probe_reset_gpio(struct lan9303 *chip,
1372 struct device_node *np)
1373 {
1374 chip->reset_gpio = devm_gpiod_get_optional(chip->dev, "reset",
1375 GPIOD_OUT_HIGH);
1376 if (IS_ERR(chip->reset_gpio))
1377 return PTR_ERR(chip->reset_gpio);
1378
1379 if (!chip->reset_gpio) {
1380 dev_dbg(chip->dev, "No reset GPIO defined\n");
1381 return 0;
1382 }
1383
1384 chip->reset_duration = 200;
1385
1386 if (np) {
1387 of_property_read_u32(np, "reset-duration",
1388 &chip->reset_duration);
1389 } else {
1390 dev_dbg(chip->dev, "reset duration defaults to 200 ms\n");
1391 }
1392
1393 /* A sane reset duration should not be longer than 1s */
1394 if (chip->reset_duration > 1000)
1395 chip->reset_duration = 1000;
1396
1397 return 0;
1398 }
1399
lan9303_probe(struct lan9303 * chip,struct device_node * np)1400 int lan9303_probe(struct lan9303 *chip, struct device_node *np)
1401 {
1402 int ret;
1403 u32 reg;
1404
1405 mutex_init(&chip->indirect_mutex);
1406 mutex_init(&chip->alr_mutex);
1407
1408 ret = lan9303_probe_reset_gpio(chip, np);
1409 if (ret)
1410 return ret;
1411
1412 lan9303_handle_reset(chip);
1413
1414 /* First read to the device. This is a Dummy read to ensure MDIO */
1415 /* access is in 32-bit sync. */
1416 ret = lan9303_read(chip->regmap, LAN9303_BYTE_ORDER, ®);
1417 if (ret) {
1418 dev_err(chip->dev, "failed to access the device: %d\n",
1419 ret);
1420 if (!chip->reset_gpio) {
1421 dev_dbg(chip->dev,
1422 "hint: maybe failed due to missing reset GPIO\n");
1423 }
1424 return ret;
1425 }
1426
1427 ret = lan9303_check_device(chip);
1428 if (ret)
1429 return ret;
1430
1431 ret = lan9303_register_switch(chip);
1432 if (ret) {
1433 dev_dbg(chip->dev, "Failed to register switch: %d\n", ret);
1434 return ret;
1435 }
1436
1437 return 0;
1438 }
1439 EXPORT_SYMBOL(lan9303_probe);
1440
lan9303_remove(struct lan9303 * chip)1441 int lan9303_remove(struct lan9303 *chip)
1442 {
1443 int rc;
1444
1445 rc = lan9303_disable_processing(chip);
1446 if (rc != 0)
1447 dev_warn(chip->dev, "shutting down failed\n");
1448
1449 dsa_unregister_switch(chip->ds);
1450
1451 /* assert reset to the whole device to prevent it from doing anything */
1452 gpiod_set_value_cansleep(chip->reset_gpio, 1);
1453
1454 return 0;
1455 }
1456 EXPORT_SYMBOL(lan9303_remove);
1457
lan9303_shutdown(struct lan9303 * chip)1458 void lan9303_shutdown(struct lan9303 *chip)
1459 {
1460 dsa_switch_shutdown(chip->ds);
1461 }
1462 EXPORT_SYMBOL(lan9303_shutdown);
1463
1464 MODULE_AUTHOR("Juergen Borleis <kernel@pengutronix.de>");
1465 MODULE_DESCRIPTION("Core driver for SMSC/Microchip LAN9303 three port ethernet switch");
1466 MODULE_LICENSE("GPL v2");
1467