1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*  *********************************************************************
3     *  BCM1280/BCM1480 Board Support Package
4     *
5     *  Interrupt Mapper definitions		File: bcm1480_int.h
6     *
7     *  This module contains constants for manipulating the
8     *  BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
9     *  definitions for the interrupt sources.
10     *
11     *  BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
12     *
13     *********************************************************************
14     *
15     *  Copyright 2000,2001,2002,2003
16     *  Broadcom Corporation. All rights reserved.
17     *
18     ********************************************************************* */
19 
20 
21 #ifndef _BCM1480_INT_H
22 #define _BCM1480_INT_H
23 
24 #include <asm/sibyte/sb1250_defs.h>
25 
26 /*  *********************************************************************
27     *  Interrupt Mapper Constants
28     ********************************************************************* */
29 
30 /*
31  * The interrupt mapper deals with 128-bit logical registers that are
32  * implemented as pairs of 64-bit registers, with the "low" 64 bits in
33  * a register that has an address 0x1000 higher(!) than the
34  * corresponding "high" register.
35  *
36  * For appropriate registers, bit 0 of the "high" register is a
37  * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
38  * register.
39  */
40 
41 /*
42  * This entire file uses _BCM1480_ in all the symbols because it is
43  * entirely BCM1480 specific.
44  */
45 
46 /*
47  * Interrupt sources (Table 22)
48  */
49 
50 #define K_BCM1480_INT_SOURCES		    128
51 
52 #define _BCM1480_INT_HIGH(k)   (k)
53 #define _BCM1480_INT_LOW(k)    ((k)+64)
54 
55 #define K_BCM1480_INT_ADDR_TRAP		    _BCM1480_INT_HIGH(1)
56 #define K_BCM1480_INT_GPIO_0		    _BCM1480_INT_HIGH(4)
57 #define K_BCM1480_INT_GPIO_1		    _BCM1480_INT_HIGH(5)
58 #define K_BCM1480_INT_GPIO_2		    _BCM1480_INT_HIGH(6)
59 #define K_BCM1480_INT_GPIO_3		    _BCM1480_INT_HIGH(7)
60 #define K_BCM1480_INT_PCI_INTA		    _BCM1480_INT_HIGH(8)
61 #define K_BCM1480_INT_PCI_INTB		    _BCM1480_INT_HIGH(9)
62 #define K_BCM1480_INT_PCI_INTC		    _BCM1480_INT_HIGH(10)
63 #define K_BCM1480_INT_PCI_INTD		    _BCM1480_INT_HIGH(11)
64 #define K_BCM1480_INT_CYCLE_CP0		    _BCM1480_INT_HIGH(12)
65 #define K_BCM1480_INT_CYCLE_CP1		    _BCM1480_INT_HIGH(13)
66 #define K_BCM1480_INT_CYCLE_CP2		    _BCM1480_INT_HIGH(14)
67 #define K_BCM1480_INT_CYCLE_CP3		    _BCM1480_INT_HIGH(15)
68 #define K_BCM1480_INT_TIMER_0		    _BCM1480_INT_HIGH(20)
69 #define K_BCM1480_INT_TIMER_1		    _BCM1480_INT_HIGH(21)
70 #define K_BCM1480_INT_TIMER_2		    _BCM1480_INT_HIGH(22)
71 #define K_BCM1480_INT_TIMER_3		    _BCM1480_INT_HIGH(23)
72 #define K_BCM1480_INT_DM_CH_0		    _BCM1480_INT_HIGH(28)
73 #define K_BCM1480_INT_DM_CH_1		    _BCM1480_INT_HIGH(29)
74 #define K_BCM1480_INT_DM_CH_2		    _BCM1480_INT_HIGH(30)
75 #define K_BCM1480_INT_DM_CH_3		    _BCM1480_INT_HIGH(31)
76 #define K_BCM1480_INT_MAC_0		    _BCM1480_INT_HIGH(36)
77 #define K_BCM1480_INT_MAC_0_CH1		    _BCM1480_INT_HIGH(37)
78 #define K_BCM1480_INT_MAC_1		    _BCM1480_INT_HIGH(38)
79 #define K_BCM1480_INT_MAC_1_CH1		    _BCM1480_INT_HIGH(39)
80 #define K_BCM1480_INT_MAC_2		    _BCM1480_INT_HIGH(40)
81 #define K_BCM1480_INT_MAC_2_CH1		    _BCM1480_INT_HIGH(41)
82 #define K_BCM1480_INT_MAC_3		    _BCM1480_INT_HIGH(42)
83 #define K_BCM1480_INT_MAC_3_CH1		    _BCM1480_INT_HIGH(43)
84 #define K_BCM1480_INT_PMI_LOW		    _BCM1480_INT_HIGH(52)
85 #define K_BCM1480_INT_PMI_HIGH		    _BCM1480_INT_HIGH(53)
86 #define K_BCM1480_INT_PMO_LOW		    _BCM1480_INT_HIGH(54)
87 #define K_BCM1480_INT_PMO_HIGH		    _BCM1480_INT_HIGH(55)
88 #define K_BCM1480_INT_MBOX_0_0		    _BCM1480_INT_HIGH(56)
89 #define K_BCM1480_INT_MBOX_0_1		    _BCM1480_INT_HIGH(57)
90 #define K_BCM1480_INT_MBOX_0_2		    _BCM1480_INT_HIGH(58)
91 #define K_BCM1480_INT_MBOX_0_3		    _BCM1480_INT_HIGH(59)
92 #define K_BCM1480_INT_MBOX_1_0		    _BCM1480_INT_HIGH(60)
93 #define K_BCM1480_INT_MBOX_1_1		    _BCM1480_INT_HIGH(61)
94 #define K_BCM1480_INT_MBOX_1_2		    _BCM1480_INT_HIGH(62)
95 #define K_BCM1480_INT_MBOX_1_3		    _BCM1480_INT_HIGH(63)
96 
97 #define K_BCM1480_INT_BAD_ECC		    _BCM1480_INT_LOW(1)
98 #define K_BCM1480_INT_COR_ECC		    _BCM1480_INT_LOW(2)
99 #define K_BCM1480_INT_IO_BUS		    _BCM1480_INT_LOW(3)
100 #define K_BCM1480_INT_PERF_CNT		    _BCM1480_INT_LOW(4)
101 #define K_BCM1480_INT_SW_PERF_CNT	    _BCM1480_INT_LOW(5)
102 #define K_BCM1480_INT_TRACE_FREEZE	    _BCM1480_INT_LOW(6)
103 #define K_BCM1480_INT_SW_TRACE_FREEZE	    _BCM1480_INT_LOW(7)
104 #define K_BCM1480_INT_WATCHDOG_TIMER_0	    _BCM1480_INT_LOW(8)
105 #define K_BCM1480_INT_WATCHDOG_TIMER_1	    _BCM1480_INT_LOW(9)
106 #define K_BCM1480_INT_WATCHDOG_TIMER_2	    _BCM1480_INT_LOW(10)
107 #define K_BCM1480_INT_WATCHDOG_TIMER_3	    _BCM1480_INT_LOW(11)
108 #define K_BCM1480_INT_PCI_ERROR		    _BCM1480_INT_LOW(16)
109 #define K_BCM1480_INT_PCI_RESET		    _BCM1480_INT_LOW(17)
110 #define K_BCM1480_INT_NODE_CONTROLLER	    _BCM1480_INT_LOW(18)
111 #define K_BCM1480_INT_HOST_BRIDGE	    _BCM1480_INT_LOW(19)
112 #define K_BCM1480_INT_PORT_0_FATAL	    _BCM1480_INT_LOW(20)
113 #define K_BCM1480_INT_PORT_0_NONFATAL	    _BCM1480_INT_LOW(21)
114 #define K_BCM1480_INT_PORT_1_FATAL	    _BCM1480_INT_LOW(22)
115 #define K_BCM1480_INT_PORT_1_NONFATAL	    _BCM1480_INT_LOW(23)
116 #define K_BCM1480_INT_PORT_2_FATAL	    _BCM1480_INT_LOW(24)
117 #define K_BCM1480_INT_PORT_2_NONFATAL	    _BCM1480_INT_LOW(25)
118 #define K_BCM1480_INT_LDT_SMI		    _BCM1480_INT_LOW(32)
119 #define K_BCM1480_INT_LDT_NMI		    _BCM1480_INT_LOW(33)
120 #define K_BCM1480_INT_LDT_INIT		    _BCM1480_INT_LOW(34)
121 #define K_BCM1480_INT_LDT_STARTUP	    _BCM1480_INT_LOW(35)
122 #define K_BCM1480_INT_LDT_EXT		    _BCM1480_INT_LOW(36)
123 #define K_BCM1480_INT_SMB_0		    _BCM1480_INT_LOW(40)
124 #define K_BCM1480_INT_SMB_1		    _BCM1480_INT_LOW(41)
125 #define K_BCM1480_INT_PCMCIA		    _BCM1480_INT_LOW(42)
126 #define K_BCM1480_INT_UART_0		    _BCM1480_INT_LOW(44)
127 #define K_BCM1480_INT_UART_1		    _BCM1480_INT_LOW(45)
128 #define K_BCM1480_INT_UART_2		    _BCM1480_INT_LOW(46)
129 #define K_BCM1480_INT_UART_3		    _BCM1480_INT_LOW(47)
130 #define K_BCM1480_INT_GPIO_4		    _BCM1480_INT_LOW(52)
131 #define K_BCM1480_INT_GPIO_5		    _BCM1480_INT_LOW(53)
132 #define K_BCM1480_INT_GPIO_6		    _BCM1480_INT_LOW(54)
133 #define K_BCM1480_INT_GPIO_7		    _BCM1480_INT_LOW(55)
134 #define K_BCM1480_INT_GPIO_8		    _BCM1480_INT_LOW(56)
135 #define K_BCM1480_INT_GPIO_9		    _BCM1480_INT_LOW(57)
136 #define K_BCM1480_INT_GPIO_10		    _BCM1480_INT_LOW(58)
137 #define K_BCM1480_INT_GPIO_11		    _BCM1480_INT_LOW(59)
138 #define K_BCM1480_INT_GPIO_12		    _BCM1480_INT_LOW(60)
139 #define K_BCM1480_INT_GPIO_13		    _BCM1480_INT_LOW(61)
140 #define K_BCM1480_INT_GPIO_14		    _BCM1480_INT_LOW(62)
141 #define K_BCM1480_INT_GPIO_15		    _BCM1480_INT_LOW(63)
142 
143 /*
144  * Mask values for each interrupt
145  */
146 
147 #define _BCM1480_INT_MASK(w, n)		     _SB_MAKEMASK(w, ((n) & 0x3F))
148 #define _BCM1480_INT_MASK1(n)		    _SB_MAKEMASK1(((n) & 0x3F))
149 #define _BCM1480_INT_OFFSET(n)		    (((n) & 0x40) << 6)
150 
151 #define M_BCM1480_INT_CASCADE		    _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
152 
153 #define M_BCM1480_INT_ADDR_TRAP		    _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
154 #define M_BCM1480_INT_GPIO_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
155 #define M_BCM1480_INT_GPIO_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
156 #define M_BCM1480_INT_GPIO_2		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
157 #define M_BCM1480_INT_GPIO_3		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
158 #define M_BCM1480_INT_PCI_INTA		    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
159 #define M_BCM1480_INT_PCI_INTB		    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
160 #define M_BCM1480_INT_PCI_INTC		    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
161 #define M_BCM1480_INT_PCI_INTD		    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
162 #define M_BCM1480_INT_CYCLE_CP0		    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
163 #define M_BCM1480_INT_CYCLE_CP1		    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
164 #define M_BCM1480_INT_CYCLE_CP2		    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
165 #define M_BCM1480_INT_CYCLE_CP3		    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
166 #define M_BCM1480_INT_TIMER_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
167 #define M_BCM1480_INT_TIMER_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
168 #define M_BCM1480_INT_TIMER_2		    _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
169 #define M_BCM1480_INT_TIMER_3		    _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
170 #define M_BCM1480_INT_DM_CH_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
171 #define M_BCM1480_INT_DM_CH_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
172 #define M_BCM1480_INT_DM_CH_2		    _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
173 #define M_BCM1480_INT_DM_CH_3		    _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
174 #define M_BCM1480_INT_MAC_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
175 #define M_BCM1480_INT_MAC_0_CH1		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
176 #define M_BCM1480_INT_MAC_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
177 #define M_BCM1480_INT_MAC_1_CH1		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
178 #define M_BCM1480_INT_MAC_2		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
179 #define M_BCM1480_INT_MAC_2_CH1		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
180 #define M_BCM1480_INT_MAC_3		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
181 #define M_BCM1480_INT_MAC_3_CH1		    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
182 #define M_BCM1480_INT_PMI_LOW		    _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
183 #define M_BCM1480_INT_PMI_HIGH		    _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
184 #define M_BCM1480_INT_PMO_LOW		    _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
185 #define M_BCM1480_INT_PMO_HIGH		    _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
186 #define M_BCM1480_INT_MBOX_ALL		    _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
187 #define M_BCM1480_INT_MBOX_0_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
188 #define M_BCM1480_INT_MBOX_0_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
189 #define M_BCM1480_INT_MBOX_0_2		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
190 #define M_BCM1480_INT_MBOX_0_3		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
191 #define M_BCM1480_INT_MBOX_1_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
192 #define M_BCM1480_INT_MBOX_1_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
193 #define M_BCM1480_INT_MBOX_1_2		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
194 #define M_BCM1480_INT_MBOX_1_3		    _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
195 #define M_BCM1480_INT_BAD_ECC		    _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
196 #define M_BCM1480_INT_COR_ECC		    _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
197 #define M_BCM1480_INT_IO_BUS		    _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
198 #define M_BCM1480_INT_PERF_CNT		    _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
199 #define M_BCM1480_INT_SW_PERF_CNT	    _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
200 #define M_BCM1480_INT_TRACE_FREEZE	    _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
201 #define M_BCM1480_INT_SW_TRACE_FREEZE	    _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
202 #define M_BCM1480_INT_WATCHDOG_TIMER_0	    _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
203 #define M_BCM1480_INT_WATCHDOG_TIMER_1	    _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
204 #define M_BCM1480_INT_WATCHDOG_TIMER_2	    _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
205 #define M_BCM1480_INT_WATCHDOG_TIMER_3	    _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
206 #define M_BCM1480_INT_PCI_ERROR		    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
207 #define M_BCM1480_INT_PCI_RESET		    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
208 #define M_BCM1480_INT_NODE_CONTROLLER	    _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
209 #define M_BCM1480_INT_HOST_BRIDGE	    _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
210 #define M_BCM1480_INT_PORT_0_FATAL	    _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
211 #define M_BCM1480_INT_PORT_0_NONFATAL	    _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
212 #define M_BCM1480_INT_PORT_1_FATAL	    _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
213 #define M_BCM1480_INT_PORT_1_NONFATAL	    _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
214 #define M_BCM1480_INT_PORT_2_FATAL	    _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
215 #define M_BCM1480_INT_PORT_2_NONFATAL	    _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
216 #define M_BCM1480_INT_LDT_SMI		    _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
217 #define M_BCM1480_INT_LDT_NMI		    _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
218 #define M_BCM1480_INT_LDT_INIT		    _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
219 #define M_BCM1480_INT_LDT_STARTUP	    _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
220 #define M_BCM1480_INT_LDT_EXT		    _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
221 #define M_BCM1480_INT_SMB_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
222 #define M_BCM1480_INT_SMB_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
223 #define M_BCM1480_INT_PCMCIA		    _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
224 #define M_BCM1480_INT_UART_0		    _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
225 #define M_BCM1480_INT_UART_1		    _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
226 #define M_BCM1480_INT_UART_2		    _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
227 #define M_BCM1480_INT_UART_3		    _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
228 #define M_BCM1480_INT_GPIO_4		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
229 #define M_BCM1480_INT_GPIO_5		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
230 #define M_BCM1480_INT_GPIO_6		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
231 #define M_BCM1480_INT_GPIO_7		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
232 #define M_BCM1480_INT_GPIO_8		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
233 #define M_BCM1480_INT_GPIO_9		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
234 #define M_BCM1480_INT_GPIO_10		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
235 #define M_BCM1480_INT_GPIO_11		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
236 #define M_BCM1480_INT_GPIO_12		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
237 #define M_BCM1480_INT_GPIO_13		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
238 #define M_BCM1480_INT_GPIO_14		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
239 #define M_BCM1480_INT_GPIO_15		    _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
240 
241 /*
242  * Interrupt mappings (Table 18)
243  */
244 
245 #define K_BCM1480_INT_MAP_I0	0		/* interrupt pins on processor */
246 #define K_BCM1480_INT_MAP_I1	1
247 #define K_BCM1480_INT_MAP_I2	2
248 #define K_BCM1480_INT_MAP_I3	3
249 #define K_BCM1480_INT_MAP_I4	4
250 #define K_BCM1480_INT_MAP_I5	5
251 #define K_BCM1480_INT_MAP_NMI	6		/* nonmaskable */
252 #define K_BCM1480_INT_MAP_DINT	7		/* debug interrupt */
253 
254 /*
255  * Interrupt LDT Set Register (Table 19)
256  */
257 
258 #define S_BCM1480_INT_HT_INTMSG		    0
259 #define M_BCM1480_INT_HT_INTMSG		    _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
260 #define V_BCM1480_INT_HT_INTMSG(x)	    _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
261 #define G_BCM1480_INT_HT_INTMSG(x)	    _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
262 
263 #define K_BCM1480_INT_HT_INTMSG_FIXED	    0
264 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1
265 #define K_BCM1480_INT_HT_INTMSG_SMI	    2
266 #define K_BCM1480_INT_HT_INTMSG_NMI	    3
267 #define K_BCM1480_INT_HT_INTMSG_INIT	    4
268 #define K_BCM1480_INT_HT_INTMSG_STARTUP	    5
269 #define K_BCM1480_INT_HT_INTMSG_EXTINT	    6
270 #define K_BCM1480_INT_HT_INTMSG_RESERVED    7
271 
272 #define M_BCM1480_INT_HT_TRIGGERMODE	    _SB_MAKEMASK1(3)
273 #define V_BCM1480_INT_HT_EDGETRIGGER	    0
274 #define V_BCM1480_INT_HT_LEVELTRIGGER	    M_BCM1480_INT_HT_TRIGGERMODE
275 
276 #define M_BCM1480_INT_HT_DESTMODE	    _SB_MAKEMASK1(4)
277 #define V_BCM1480_INT_HT_PHYSICALDEST	    0
278 #define V_BCM1480_INT_HT_LOGICALDEST	    M_BCM1480_INT_HT_DESTMODE
279 
280 #define S_BCM1480_INT_HT_INTDEST	    5
281 #define M_BCM1480_INT_HT_INTDEST	    _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
282 #define V_BCM1480_INT_HT_INTDEST(x)	    _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
283 #define G_BCM1480_INT_HT_INTDEST(x)	    _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
284 
285 #define S_BCM1480_INT_HT_VECTOR		    13
286 #define M_BCM1480_INT_HT_VECTOR		    _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
287 #define V_BCM1480_INT_HT_VECTOR(x)	    _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
288 #define G_BCM1480_INT_HT_VECTOR(x)	    _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
289 
290 /*
291  * Vector prefix (Table 4-7)
292  */
293 
294 #define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00
295 #define M_BCM1480_HTVECT_RAISE_MBOX_0	    0x40
296 #define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80
297 #define M_BCM1480_HTVECT_RAISE_MBOX_1	    0xC0
298 
299 #endif /* _BCM1480_INT_H */
300