xref: /openbmc/linux/arch/x86/kvm/x86.c (revision 93937573)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Kernel-based Virtual Machine driver for Linux
4  *
5  * derived from drivers/kvm/kvm_main.c
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright (C) 2008 Qumranet, Inc.
9  * Copyright IBM Corporation, 2008
10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11  *
12  * Authors:
13  *   Avi Kivity   <avi@qumranet.com>
14  *   Yaniv Kamay  <yaniv@qumranet.com>
15  *   Amit Shah    <amit.shah@qumranet.com>
16  *   Ben-Ami Yassour <benami@il.ibm.com>
17  */
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 
20 #include <linux/kvm_host.h>
21 #include "irq.h"
22 #include "ioapic.h"
23 #include "mmu.h"
24 #include "i8254.h"
25 #include "tss.h"
26 #include "kvm_cache_regs.h"
27 #include "kvm_emulate.h"
28 #include "mmu/page_track.h"
29 #include "x86.h"
30 #include "cpuid.h"
31 #include "pmu.h"
32 #include "hyperv.h"
33 #include "lapic.h"
34 #include "xen.h"
35 #include "smm.h"
36 
37 #include <linux/clocksource.h>
38 #include <linux/interrupt.h>
39 #include <linux/kvm.h>
40 #include <linux/fs.h>
41 #include <linux/vmalloc.h>
42 #include <linux/export.h>
43 #include <linux/moduleparam.h>
44 #include <linux/mman.h>
45 #include <linux/highmem.h>
46 #include <linux/iommu.h>
47 #include <linux/cpufreq.h>
48 #include <linux/user-return-notifier.h>
49 #include <linux/srcu.h>
50 #include <linux/slab.h>
51 #include <linux/perf_event.h>
52 #include <linux/uaccess.h>
53 #include <linux/hash.h>
54 #include <linux/pci.h>
55 #include <linux/timekeeper_internal.h>
56 #include <linux/pvclock_gtod.h>
57 #include <linux/kvm_irqfd.h>
58 #include <linux/irqbypass.h>
59 #include <linux/sched/stat.h>
60 #include <linux/sched/isolation.h>
61 #include <linux/mem_encrypt.h>
62 #include <linux/entry-kvm.h>
63 #include <linux/suspend.h>
64 #include <linux/smp.h>
65 
66 #include <trace/events/ipi.h>
67 #include <trace/events/kvm.h>
68 
69 #include <asm/debugreg.h>
70 #include <asm/msr.h>
71 #include <asm/desc.h>
72 #include <asm/mce.h>
73 #include <asm/pkru.h>
74 #include <linux/kernel_stat.h>
75 #include <asm/fpu/api.h>
76 #include <asm/fpu/xcr.h>
77 #include <asm/fpu/xstate.h>
78 #include <asm/pvclock.h>
79 #include <asm/div64.h>
80 #include <asm/irq_remapping.h>
81 #include <asm/mshyperv.h>
82 #include <asm/hypervisor.h>
83 #include <asm/tlbflush.h>
84 #include <asm/intel_pt.h>
85 #include <asm/emulate_prefix.h>
86 #include <asm/sgx.h>
87 #include <clocksource/hyperv_timer.h>
88 
89 #define CREATE_TRACE_POINTS
90 #include "trace.h"
91 
92 #define MAX_IO_MSRS 256
93 #define KVM_MAX_MCE_BANKS 32
94 
95 struct kvm_caps kvm_caps __read_mostly = {
96 	.supported_mce_cap = MCG_CTL_P | MCG_SER_P,
97 };
98 EXPORT_SYMBOL_GPL(kvm_caps);
99 
100 #define  ERR_PTR_USR(e)  ((void __user *)ERR_PTR(e))
101 
102 #define emul_to_vcpu(ctxt) \
103 	((struct kvm_vcpu *)(ctxt)->vcpu)
104 
105 /* EFER defaults:
106  * - enable syscall per default because its emulated by KVM
107  * - enable LME and LMA per default on 64 bit KVM
108  */
109 #ifdef CONFIG_X86_64
110 static
111 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
112 #else
113 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
114 #endif
115 
116 static u64 __read_mostly cr4_reserved_bits = CR4_RESERVED_BITS;
117 
118 #define KVM_EXIT_HYPERCALL_VALID_MASK (1 << KVM_HC_MAP_GPA_RANGE)
119 
120 #define KVM_CAP_PMU_VALID_MASK KVM_PMU_CAP_DISABLE
121 
122 #define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
123                                     KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
124 
125 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
126 static void process_nmi(struct kvm_vcpu *vcpu);
127 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
128 static void store_regs(struct kvm_vcpu *vcpu);
129 static int sync_regs(struct kvm_vcpu *vcpu);
130 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu);
131 
132 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
133 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2);
134 
135 static DEFINE_MUTEX(vendor_module_lock);
136 struct kvm_x86_ops kvm_x86_ops __read_mostly;
137 
138 #define KVM_X86_OP(func)					     \
139 	DEFINE_STATIC_CALL_NULL(kvm_x86_##func,			     \
140 				*(((struct kvm_x86_ops *)0)->func));
141 #define KVM_X86_OP_OPTIONAL KVM_X86_OP
142 #define KVM_X86_OP_OPTIONAL_RET0 KVM_X86_OP
143 #include <asm/kvm-x86-ops.h>
144 EXPORT_STATIC_CALL_GPL(kvm_x86_get_cs_db_l_bits);
145 EXPORT_STATIC_CALL_GPL(kvm_x86_cache_reg);
146 
147 static bool __read_mostly ignore_msrs = 0;
148 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
149 
150 bool __read_mostly report_ignored_msrs = true;
151 module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
152 EXPORT_SYMBOL_GPL(report_ignored_msrs);
153 
154 unsigned int min_timer_period_us = 200;
155 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
156 
157 static bool __read_mostly kvmclock_periodic_sync = true;
158 module_param(kvmclock_periodic_sync, bool, S_IRUGO);
159 
160 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
161 static u32 __read_mostly tsc_tolerance_ppm = 250;
162 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
163 
164 /*
165  * lapic timer advance (tscdeadline mode only) in nanoseconds.  '-1' enables
166  * adaptive tuning starting from default advancement of 1000ns.  '0' disables
167  * advancement entirely.  Any other value is used as-is and disables adaptive
168  * tuning, i.e. allows privileged userspace to set an exact advancement time.
169  */
170 static int __read_mostly lapic_timer_advance_ns = -1;
171 module_param(lapic_timer_advance_ns, int, S_IRUGO | S_IWUSR);
172 
173 static bool __read_mostly vector_hashing = true;
174 module_param(vector_hashing, bool, S_IRUGO);
175 
176 bool __read_mostly enable_vmware_backdoor = false;
177 module_param(enable_vmware_backdoor, bool, S_IRUGO);
178 EXPORT_SYMBOL_GPL(enable_vmware_backdoor);
179 
180 /*
181  * Flags to manipulate forced emulation behavior (any non-zero value will
182  * enable forced emulation).
183  */
184 #define KVM_FEP_CLEAR_RFLAGS_RF	BIT(1)
185 static int __read_mostly force_emulation_prefix;
186 module_param(force_emulation_prefix, int, 0644);
187 
188 int __read_mostly pi_inject_timer = -1;
189 module_param(pi_inject_timer, bint, S_IRUGO | S_IWUSR);
190 
191 /* Enable/disable PMU virtualization */
192 bool __read_mostly enable_pmu = true;
193 EXPORT_SYMBOL_GPL(enable_pmu);
194 module_param(enable_pmu, bool, 0444);
195 
196 bool __read_mostly eager_page_split = true;
197 module_param(eager_page_split, bool, 0644);
198 
199 /* Enable/disable SMT_RSB bug mitigation */
200 static bool __read_mostly mitigate_smt_rsb;
201 module_param(mitigate_smt_rsb, bool, 0444);
202 
203 /*
204  * Restoring the host value for MSRs that are only consumed when running in
205  * usermode, e.g. SYSCALL MSRs and TSC_AUX, can be deferred until the CPU
206  * returns to userspace, i.e. the kernel can run with the guest's value.
207  */
208 #define KVM_MAX_NR_USER_RETURN_MSRS 16
209 
210 struct kvm_user_return_msrs {
211 	struct user_return_notifier urn;
212 	bool registered;
213 	struct kvm_user_return_msr_values {
214 		u64 host;
215 		u64 curr;
216 	} values[KVM_MAX_NR_USER_RETURN_MSRS];
217 };
218 
219 u32 __read_mostly kvm_nr_uret_msrs;
220 EXPORT_SYMBOL_GPL(kvm_nr_uret_msrs);
221 static u32 __read_mostly kvm_uret_msrs_list[KVM_MAX_NR_USER_RETURN_MSRS];
222 static struct kvm_user_return_msrs __percpu *user_return_msrs;
223 
224 #define KVM_SUPPORTED_XCR0     (XFEATURE_MASK_FP | XFEATURE_MASK_SSE \
225 				| XFEATURE_MASK_YMM | XFEATURE_MASK_BNDREGS \
226 				| XFEATURE_MASK_BNDCSR | XFEATURE_MASK_AVX512 \
227 				| XFEATURE_MASK_PKRU | XFEATURE_MASK_XTILE)
228 
229 u64 __read_mostly host_efer;
230 EXPORT_SYMBOL_GPL(host_efer);
231 
232 bool __read_mostly allow_smaller_maxphyaddr = 0;
233 EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr);
234 
235 bool __read_mostly enable_apicv = true;
236 EXPORT_SYMBOL_GPL(enable_apicv);
237 
238 u64 __read_mostly host_xss;
239 EXPORT_SYMBOL_GPL(host_xss);
240 
241 u64 __read_mostly host_arch_capabilities;
242 EXPORT_SYMBOL_GPL(host_arch_capabilities);
243 
244 const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
245 	KVM_GENERIC_VM_STATS(),
246 	STATS_DESC_COUNTER(VM, mmu_shadow_zapped),
247 	STATS_DESC_COUNTER(VM, mmu_pte_write),
248 	STATS_DESC_COUNTER(VM, mmu_pde_zapped),
249 	STATS_DESC_COUNTER(VM, mmu_flooded),
250 	STATS_DESC_COUNTER(VM, mmu_recycled),
251 	STATS_DESC_COUNTER(VM, mmu_cache_miss),
252 	STATS_DESC_ICOUNTER(VM, mmu_unsync),
253 	STATS_DESC_ICOUNTER(VM, pages_4k),
254 	STATS_DESC_ICOUNTER(VM, pages_2m),
255 	STATS_DESC_ICOUNTER(VM, pages_1g),
256 	STATS_DESC_ICOUNTER(VM, nx_lpage_splits),
257 	STATS_DESC_PCOUNTER(VM, max_mmu_rmap_size),
258 	STATS_DESC_PCOUNTER(VM, max_mmu_page_hash_collisions)
259 };
260 
261 const struct kvm_stats_header kvm_vm_stats_header = {
262 	.name_size = KVM_STATS_NAME_SIZE,
263 	.num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
264 	.id_offset = sizeof(struct kvm_stats_header),
265 	.desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
266 	.data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
267 		       sizeof(kvm_vm_stats_desc),
268 };
269 
270 const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
271 	KVM_GENERIC_VCPU_STATS(),
272 	STATS_DESC_COUNTER(VCPU, pf_taken),
273 	STATS_DESC_COUNTER(VCPU, pf_fixed),
274 	STATS_DESC_COUNTER(VCPU, pf_emulate),
275 	STATS_DESC_COUNTER(VCPU, pf_spurious),
276 	STATS_DESC_COUNTER(VCPU, pf_fast),
277 	STATS_DESC_COUNTER(VCPU, pf_mmio_spte_created),
278 	STATS_DESC_COUNTER(VCPU, pf_guest),
279 	STATS_DESC_COUNTER(VCPU, tlb_flush),
280 	STATS_DESC_COUNTER(VCPU, invlpg),
281 	STATS_DESC_COUNTER(VCPU, exits),
282 	STATS_DESC_COUNTER(VCPU, io_exits),
283 	STATS_DESC_COUNTER(VCPU, mmio_exits),
284 	STATS_DESC_COUNTER(VCPU, signal_exits),
285 	STATS_DESC_COUNTER(VCPU, irq_window_exits),
286 	STATS_DESC_COUNTER(VCPU, nmi_window_exits),
287 	STATS_DESC_COUNTER(VCPU, l1d_flush),
288 	STATS_DESC_COUNTER(VCPU, halt_exits),
289 	STATS_DESC_COUNTER(VCPU, request_irq_exits),
290 	STATS_DESC_COUNTER(VCPU, irq_exits),
291 	STATS_DESC_COUNTER(VCPU, host_state_reload),
292 	STATS_DESC_COUNTER(VCPU, fpu_reload),
293 	STATS_DESC_COUNTER(VCPU, insn_emulation),
294 	STATS_DESC_COUNTER(VCPU, insn_emulation_fail),
295 	STATS_DESC_COUNTER(VCPU, hypercalls),
296 	STATS_DESC_COUNTER(VCPU, irq_injections),
297 	STATS_DESC_COUNTER(VCPU, nmi_injections),
298 	STATS_DESC_COUNTER(VCPU, req_event),
299 	STATS_DESC_COUNTER(VCPU, nested_run),
300 	STATS_DESC_COUNTER(VCPU, directed_yield_attempted),
301 	STATS_DESC_COUNTER(VCPU, directed_yield_successful),
302 	STATS_DESC_COUNTER(VCPU, preemption_reported),
303 	STATS_DESC_COUNTER(VCPU, preemption_other),
304 	STATS_DESC_IBOOLEAN(VCPU, guest_mode),
305 	STATS_DESC_COUNTER(VCPU, notify_window_exits),
306 };
307 
308 const struct kvm_stats_header kvm_vcpu_stats_header = {
309 	.name_size = KVM_STATS_NAME_SIZE,
310 	.num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
311 	.id_offset = sizeof(struct kvm_stats_header),
312 	.desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
313 	.data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
314 		       sizeof(kvm_vcpu_stats_desc),
315 };
316 
317 u64 __read_mostly host_xcr0;
318 
319 static struct kmem_cache *x86_emulator_cache;
320 
321 /*
322  * When called, it means the previous get/set msr reached an invalid msr.
323  * Return true if we want to ignore/silent this failed msr access.
324  */
kvm_msr_ignored_check(u32 msr,u64 data,bool write)325 static bool kvm_msr_ignored_check(u32 msr, u64 data, bool write)
326 {
327 	const char *op = write ? "wrmsr" : "rdmsr";
328 
329 	if (ignore_msrs) {
330 		if (report_ignored_msrs)
331 			kvm_pr_unimpl("ignored %s: 0x%x data 0x%llx\n",
332 				      op, msr, data);
333 		/* Mask the error */
334 		return true;
335 	} else {
336 		kvm_debug_ratelimited("unhandled %s: 0x%x data 0x%llx\n",
337 				      op, msr, data);
338 		return false;
339 	}
340 }
341 
kvm_alloc_emulator_cache(void)342 static struct kmem_cache *kvm_alloc_emulator_cache(void)
343 {
344 	unsigned int useroffset = offsetof(struct x86_emulate_ctxt, src);
345 	unsigned int size = sizeof(struct x86_emulate_ctxt);
346 
347 	return kmem_cache_create_usercopy("x86_emulator", size,
348 					  __alignof__(struct x86_emulate_ctxt),
349 					  SLAB_ACCOUNT, useroffset,
350 					  size - useroffset, NULL);
351 }
352 
353 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
354 
kvm_async_pf_hash_reset(struct kvm_vcpu * vcpu)355 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
356 {
357 	int i;
358 	for (i = 0; i < ASYNC_PF_PER_VCPU; i++)
359 		vcpu->arch.apf.gfns[i] = ~0;
360 }
361 
kvm_on_user_return(struct user_return_notifier * urn)362 static void kvm_on_user_return(struct user_return_notifier *urn)
363 {
364 	unsigned slot;
365 	struct kvm_user_return_msrs *msrs
366 		= container_of(urn, struct kvm_user_return_msrs, urn);
367 	struct kvm_user_return_msr_values *values;
368 	unsigned long flags;
369 
370 	/*
371 	 * Disabling irqs at this point since the following code could be
372 	 * interrupted and executed through kvm_arch_hardware_disable()
373 	 */
374 	local_irq_save(flags);
375 	if (msrs->registered) {
376 		msrs->registered = false;
377 		user_return_notifier_unregister(urn);
378 	}
379 	local_irq_restore(flags);
380 	for (slot = 0; slot < kvm_nr_uret_msrs; ++slot) {
381 		values = &msrs->values[slot];
382 		if (values->host != values->curr) {
383 			wrmsrl(kvm_uret_msrs_list[slot], values->host);
384 			values->curr = values->host;
385 		}
386 	}
387 }
388 
kvm_probe_user_return_msr(u32 msr)389 static int kvm_probe_user_return_msr(u32 msr)
390 {
391 	u64 val;
392 	int ret;
393 
394 	preempt_disable();
395 	ret = rdmsrl_safe(msr, &val);
396 	if (ret)
397 		goto out;
398 	ret = wrmsrl_safe(msr, val);
399 out:
400 	preempt_enable();
401 	return ret;
402 }
403 
kvm_add_user_return_msr(u32 msr)404 int kvm_add_user_return_msr(u32 msr)
405 {
406 	BUG_ON(kvm_nr_uret_msrs >= KVM_MAX_NR_USER_RETURN_MSRS);
407 
408 	if (kvm_probe_user_return_msr(msr))
409 		return -1;
410 
411 	kvm_uret_msrs_list[kvm_nr_uret_msrs] = msr;
412 	return kvm_nr_uret_msrs++;
413 }
414 EXPORT_SYMBOL_GPL(kvm_add_user_return_msr);
415 
kvm_find_user_return_msr(u32 msr)416 int kvm_find_user_return_msr(u32 msr)
417 {
418 	int i;
419 
420 	for (i = 0; i < kvm_nr_uret_msrs; ++i) {
421 		if (kvm_uret_msrs_list[i] == msr)
422 			return i;
423 	}
424 	return -1;
425 }
426 EXPORT_SYMBOL_GPL(kvm_find_user_return_msr);
427 
kvm_user_return_msr_cpu_online(void)428 static void kvm_user_return_msr_cpu_online(void)
429 {
430 	unsigned int cpu = smp_processor_id();
431 	struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
432 	u64 value;
433 	int i;
434 
435 	for (i = 0; i < kvm_nr_uret_msrs; ++i) {
436 		rdmsrl_safe(kvm_uret_msrs_list[i], &value);
437 		msrs->values[i].host = value;
438 		msrs->values[i].curr = value;
439 	}
440 }
441 
kvm_set_user_return_msr(unsigned slot,u64 value,u64 mask)442 int kvm_set_user_return_msr(unsigned slot, u64 value, u64 mask)
443 {
444 	unsigned int cpu = smp_processor_id();
445 	struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
446 	int err;
447 
448 	value = (value & mask) | (msrs->values[slot].host & ~mask);
449 	if (value == msrs->values[slot].curr)
450 		return 0;
451 	err = wrmsrl_safe(kvm_uret_msrs_list[slot], value);
452 	if (err)
453 		return 1;
454 
455 	msrs->values[slot].curr = value;
456 	if (!msrs->registered) {
457 		msrs->urn.on_user_return = kvm_on_user_return;
458 		user_return_notifier_register(&msrs->urn);
459 		msrs->registered = true;
460 	}
461 	return 0;
462 }
463 EXPORT_SYMBOL_GPL(kvm_set_user_return_msr);
464 
drop_user_return_notifiers(void)465 static void drop_user_return_notifiers(void)
466 {
467 	unsigned int cpu = smp_processor_id();
468 	struct kvm_user_return_msrs *msrs = per_cpu_ptr(user_return_msrs, cpu);
469 
470 	if (msrs->registered)
471 		kvm_on_user_return(&msrs->urn);
472 }
473 
kvm_get_apic_base(struct kvm_vcpu * vcpu)474 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
475 {
476 	return vcpu->arch.apic_base;
477 }
478 
kvm_get_apic_mode(struct kvm_vcpu * vcpu)479 enum lapic_mode kvm_get_apic_mode(struct kvm_vcpu *vcpu)
480 {
481 	return kvm_apic_mode(kvm_get_apic_base(vcpu));
482 }
483 EXPORT_SYMBOL_GPL(kvm_get_apic_mode);
484 
kvm_set_apic_base(struct kvm_vcpu * vcpu,struct msr_data * msr_info)485 int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
486 {
487 	enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
488 	enum lapic_mode new_mode = kvm_apic_mode(msr_info->data);
489 	u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
490 		(guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
491 
492 	if ((msr_info->data & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
493 		return 1;
494 	if (!msr_info->host_initiated) {
495 		if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
496 			return 1;
497 		if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
498 			return 1;
499 	}
500 
501 	kvm_lapic_set_base(vcpu, msr_info->data);
502 	kvm_recalculate_apic_map(vcpu->kvm);
503 	return 0;
504 }
505 
506 /*
507  * Handle a fault on a hardware virtualization (VMX or SVM) instruction.
508  *
509  * Hardware virtualization extension instructions may fault if a reboot turns
510  * off virtualization while processes are running.  Usually after catching the
511  * fault we just panic; during reboot instead the instruction is ignored.
512  */
kvm_spurious_fault(void)513 noinstr void kvm_spurious_fault(void)
514 {
515 	/* Fault while not rebooting.  We want the trace. */
516 	BUG_ON(!kvm_rebooting);
517 }
518 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
519 
520 #define EXCPT_BENIGN		0
521 #define EXCPT_CONTRIBUTORY	1
522 #define EXCPT_PF		2
523 
exception_class(int vector)524 static int exception_class(int vector)
525 {
526 	switch (vector) {
527 	case PF_VECTOR:
528 		return EXCPT_PF;
529 	case DE_VECTOR:
530 	case TS_VECTOR:
531 	case NP_VECTOR:
532 	case SS_VECTOR:
533 	case GP_VECTOR:
534 		return EXCPT_CONTRIBUTORY;
535 	default:
536 		break;
537 	}
538 	return EXCPT_BENIGN;
539 }
540 
541 #define EXCPT_FAULT		0
542 #define EXCPT_TRAP		1
543 #define EXCPT_ABORT		2
544 #define EXCPT_INTERRUPT		3
545 #define EXCPT_DB		4
546 
exception_type(int vector)547 static int exception_type(int vector)
548 {
549 	unsigned int mask;
550 
551 	if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
552 		return EXCPT_INTERRUPT;
553 
554 	mask = 1 << vector;
555 
556 	/*
557 	 * #DBs can be trap-like or fault-like, the caller must check other CPU
558 	 * state, e.g. DR6, to determine whether a #DB is a trap or fault.
559 	 */
560 	if (mask & (1 << DB_VECTOR))
561 		return EXCPT_DB;
562 
563 	if (mask & ((1 << BP_VECTOR) | (1 << OF_VECTOR)))
564 		return EXCPT_TRAP;
565 
566 	if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
567 		return EXCPT_ABORT;
568 
569 	/* Reserved exceptions will result in fault */
570 	return EXCPT_FAULT;
571 }
572 
kvm_deliver_exception_payload(struct kvm_vcpu * vcpu,struct kvm_queued_exception * ex)573 void kvm_deliver_exception_payload(struct kvm_vcpu *vcpu,
574 				   struct kvm_queued_exception *ex)
575 {
576 	if (!ex->has_payload)
577 		return;
578 
579 	switch (ex->vector) {
580 	case DB_VECTOR:
581 		/*
582 		 * "Certain debug exceptions may clear bit 0-3.  The
583 		 * remaining contents of the DR6 register are never
584 		 * cleared by the processor".
585 		 */
586 		vcpu->arch.dr6 &= ~DR_TRAP_BITS;
587 		/*
588 		 * In order to reflect the #DB exception payload in guest
589 		 * dr6, three components need to be considered: active low
590 		 * bit, FIXED_1 bits and active high bits (e.g. DR6_BD,
591 		 * DR6_BS and DR6_BT)
592 		 * DR6_ACTIVE_LOW contains the FIXED_1 and active low bits.
593 		 * In the target guest dr6:
594 		 * FIXED_1 bits should always be set.
595 		 * Active low bits should be cleared if 1-setting in payload.
596 		 * Active high bits should be set if 1-setting in payload.
597 		 *
598 		 * Note, the payload is compatible with the pending debug
599 		 * exceptions/exit qualification under VMX, that active_low bits
600 		 * are active high in payload.
601 		 * So they need to be flipped for DR6.
602 		 */
603 		vcpu->arch.dr6 |= DR6_ACTIVE_LOW;
604 		vcpu->arch.dr6 |= ex->payload;
605 		vcpu->arch.dr6 ^= ex->payload & DR6_ACTIVE_LOW;
606 
607 		/*
608 		 * The #DB payload is defined as compatible with the 'pending
609 		 * debug exceptions' field under VMX, not DR6. While bit 12 is
610 		 * defined in the 'pending debug exceptions' field (enabled
611 		 * breakpoint), it is reserved and must be zero in DR6.
612 		 */
613 		vcpu->arch.dr6 &= ~BIT(12);
614 		break;
615 	case PF_VECTOR:
616 		vcpu->arch.cr2 = ex->payload;
617 		break;
618 	}
619 
620 	ex->has_payload = false;
621 	ex->payload = 0;
622 }
623 EXPORT_SYMBOL_GPL(kvm_deliver_exception_payload);
624 
kvm_queue_exception_vmexit(struct kvm_vcpu * vcpu,unsigned int vector,bool has_error_code,u32 error_code,bool has_payload,unsigned long payload)625 static void kvm_queue_exception_vmexit(struct kvm_vcpu *vcpu, unsigned int vector,
626 				       bool has_error_code, u32 error_code,
627 				       bool has_payload, unsigned long payload)
628 {
629 	struct kvm_queued_exception *ex = &vcpu->arch.exception_vmexit;
630 
631 	ex->vector = vector;
632 	ex->injected = false;
633 	ex->pending = true;
634 	ex->has_error_code = has_error_code;
635 	ex->error_code = error_code;
636 	ex->has_payload = has_payload;
637 	ex->payload = payload;
638 }
639 
640 /* Forcibly leave the nested mode in cases like a vCPU reset */
kvm_leave_nested(struct kvm_vcpu * vcpu)641 static void kvm_leave_nested(struct kvm_vcpu *vcpu)
642 {
643 	kvm_x86_ops.nested_ops->leave_nested(vcpu);
644 }
645 
kvm_multiple_exception(struct kvm_vcpu * vcpu,unsigned nr,bool has_error,u32 error_code,bool has_payload,unsigned long payload,bool reinject)646 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
647 		unsigned nr, bool has_error, u32 error_code,
648 	        bool has_payload, unsigned long payload, bool reinject)
649 {
650 	u32 prev_nr;
651 	int class1, class2;
652 
653 	kvm_make_request(KVM_REQ_EVENT, vcpu);
654 
655 	/*
656 	 * If the exception is destined for L2 and isn't being reinjected,
657 	 * morph it to a VM-Exit if L1 wants to intercept the exception.  A
658 	 * previously injected exception is not checked because it was checked
659 	 * when it was original queued, and re-checking is incorrect if _L1_
660 	 * injected the exception, in which case it's exempt from interception.
661 	 */
662 	if (!reinject && is_guest_mode(vcpu) &&
663 	    kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, nr, error_code)) {
664 		kvm_queue_exception_vmexit(vcpu, nr, has_error, error_code,
665 					   has_payload, payload);
666 		return;
667 	}
668 
669 	if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
670 	queue:
671 		if (reinject) {
672 			/*
673 			 * On VM-Entry, an exception can be pending if and only
674 			 * if event injection was blocked by nested_run_pending.
675 			 * In that case, however, vcpu_enter_guest() requests an
676 			 * immediate exit, and the guest shouldn't proceed far
677 			 * enough to need reinjection.
678 			 */
679 			WARN_ON_ONCE(kvm_is_exception_pending(vcpu));
680 			vcpu->arch.exception.injected = true;
681 			if (WARN_ON_ONCE(has_payload)) {
682 				/*
683 				 * A reinjected event has already
684 				 * delivered its payload.
685 				 */
686 				has_payload = false;
687 				payload = 0;
688 			}
689 		} else {
690 			vcpu->arch.exception.pending = true;
691 			vcpu->arch.exception.injected = false;
692 		}
693 		vcpu->arch.exception.has_error_code = has_error;
694 		vcpu->arch.exception.vector = nr;
695 		vcpu->arch.exception.error_code = error_code;
696 		vcpu->arch.exception.has_payload = has_payload;
697 		vcpu->arch.exception.payload = payload;
698 		if (!is_guest_mode(vcpu))
699 			kvm_deliver_exception_payload(vcpu,
700 						      &vcpu->arch.exception);
701 		return;
702 	}
703 
704 	/* to check exception */
705 	prev_nr = vcpu->arch.exception.vector;
706 	if (prev_nr == DF_VECTOR) {
707 		/* triple fault -> shutdown */
708 		kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
709 		return;
710 	}
711 	class1 = exception_class(prev_nr);
712 	class2 = exception_class(nr);
713 	if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY) ||
714 	    (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
715 		/*
716 		 * Synthesize #DF.  Clear the previously injected or pending
717 		 * exception so as not to incorrectly trigger shutdown.
718 		 */
719 		vcpu->arch.exception.injected = false;
720 		vcpu->arch.exception.pending = false;
721 
722 		kvm_queue_exception_e(vcpu, DF_VECTOR, 0);
723 	} else {
724 		/* replace previous exception with a new one in a hope
725 		   that instruction re-execution will regenerate lost
726 		   exception */
727 		goto queue;
728 	}
729 }
730 
kvm_queue_exception(struct kvm_vcpu * vcpu,unsigned nr)731 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
732 {
733 	kvm_multiple_exception(vcpu, nr, false, 0, false, 0, false);
734 }
735 EXPORT_SYMBOL_GPL(kvm_queue_exception);
736 
kvm_requeue_exception(struct kvm_vcpu * vcpu,unsigned nr)737 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
738 {
739 	kvm_multiple_exception(vcpu, nr, false, 0, false, 0, true);
740 }
741 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
742 
kvm_queue_exception_p(struct kvm_vcpu * vcpu,unsigned nr,unsigned long payload)743 void kvm_queue_exception_p(struct kvm_vcpu *vcpu, unsigned nr,
744 			   unsigned long payload)
745 {
746 	kvm_multiple_exception(vcpu, nr, false, 0, true, payload, false);
747 }
748 EXPORT_SYMBOL_GPL(kvm_queue_exception_p);
749 
kvm_queue_exception_e_p(struct kvm_vcpu * vcpu,unsigned nr,u32 error_code,unsigned long payload)750 static void kvm_queue_exception_e_p(struct kvm_vcpu *vcpu, unsigned nr,
751 				    u32 error_code, unsigned long payload)
752 {
753 	kvm_multiple_exception(vcpu, nr, true, error_code,
754 			       true, payload, false);
755 }
756 
kvm_complete_insn_gp(struct kvm_vcpu * vcpu,int err)757 int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
758 {
759 	if (err)
760 		kvm_inject_gp(vcpu, 0);
761 	else
762 		return kvm_skip_emulated_instruction(vcpu);
763 
764 	return 1;
765 }
766 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
767 
complete_emulated_insn_gp(struct kvm_vcpu * vcpu,int err)768 static int complete_emulated_insn_gp(struct kvm_vcpu *vcpu, int err)
769 {
770 	if (err) {
771 		kvm_inject_gp(vcpu, 0);
772 		return 1;
773 	}
774 
775 	return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
776 				       EMULTYPE_COMPLETE_USER_EXIT);
777 }
778 
kvm_inject_page_fault(struct kvm_vcpu * vcpu,struct x86_exception * fault)779 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
780 {
781 	++vcpu->stat.pf_guest;
782 
783 	/*
784 	 * Async #PF in L2 is always forwarded to L1 as a VM-Exit regardless of
785 	 * whether or not L1 wants to intercept "regular" #PF.
786 	 */
787 	if (is_guest_mode(vcpu) && fault->async_page_fault)
788 		kvm_queue_exception_vmexit(vcpu, PF_VECTOR,
789 					   true, fault->error_code,
790 					   true, fault->address);
791 	else
792 		kvm_queue_exception_e_p(vcpu, PF_VECTOR, fault->error_code,
793 					fault->address);
794 }
795 
kvm_inject_emulated_page_fault(struct kvm_vcpu * vcpu,struct x86_exception * fault)796 void kvm_inject_emulated_page_fault(struct kvm_vcpu *vcpu,
797 				    struct x86_exception *fault)
798 {
799 	struct kvm_mmu *fault_mmu;
800 	WARN_ON_ONCE(fault->vector != PF_VECTOR);
801 
802 	fault_mmu = fault->nested_page_fault ? vcpu->arch.mmu :
803 					       vcpu->arch.walk_mmu;
804 
805 	/*
806 	 * Invalidate the TLB entry for the faulting address, if it exists,
807 	 * else the access will fault indefinitely (and to emulate hardware).
808 	 */
809 	if ((fault->error_code & PFERR_PRESENT_MASK) &&
810 	    !(fault->error_code & PFERR_RSVD_MASK))
811 		kvm_mmu_invalidate_addr(vcpu, fault_mmu, fault->address,
812 					KVM_MMU_ROOT_CURRENT);
813 
814 	fault_mmu->inject_page_fault(vcpu, fault);
815 }
816 EXPORT_SYMBOL_GPL(kvm_inject_emulated_page_fault);
817 
kvm_inject_nmi(struct kvm_vcpu * vcpu)818 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
819 {
820 	atomic_inc(&vcpu->arch.nmi_queued);
821 	kvm_make_request(KVM_REQ_NMI, vcpu);
822 }
823 
kvm_queue_exception_e(struct kvm_vcpu * vcpu,unsigned nr,u32 error_code)824 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
825 {
826 	kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, false);
827 }
828 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
829 
kvm_requeue_exception_e(struct kvm_vcpu * vcpu,unsigned nr,u32 error_code)830 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
831 {
832 	kvm_multiple_exception(vcpu, nr, true, error_code, false, 0, true);
833 }
834 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
835 
836 /*
837  * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
838  * a #GP and return false.
839  */
kvm_require_cpl(struct kvm_vcpu * vcpu,int required_cpl)840 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
841 {
842 	if (static_call(kvm_x86_get_cpl)(vcpu) <= required_cpl)
843 		return true;
844 	kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
845 	return false;
846 }
847 
kvm_require_dr(struct kvm_vcpu * vcpu,int dr)848 bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
849 {
850 	if ((dr != 4 && dr != 5) || !kvm_is_cr4_bit_set(vcpu, X86_CR4_DE))
851 		return true;
852 
853 	kvm_queue_exception(vcpu, UD_VECTOR);
854 	return false;
855 }
856 EXPORT_SYMBOL_GPL(kvm_require_dr);
857 
pdptr_rsvd_bits(struct kvm_vcpu * vcpu)858 static inline u64 pdptr_rsvd_bits(struct kvm_vcpu *vcpu)
859 {
860 	return vcpu->arch.reserved_gpa_bits | rsvd_bits(5, 8) | rsvd_bits(1, 2);
861 }
862 
863 /*
864  * Load the pae pdptrs.  Return 1 if they are all valid, 0 otherwise.
865  */
load_pdptrs(struct kvm_vcpu * vcpu,unsigned long cr3)866 int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
867 {
868 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
869 	gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
870 	gpa_t real_gpa;
871 	int i;
872 	int ret;
873 	u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
874 
875 	/*
876 	 * If the MMU is nested, CR3 holds an L2 GPA and needs to be translated
877 	 * to an L1 GPA.
878 	 */
879 	real_gpa = kvm_translate_gpa(vcpu, mmu, gfn_to_gpa(pdpt_gfn),
880 				     PFERR_USER_MASK | PFERR_WRITE_MASK, NULL);
881 	if (real_gpa == INVALID_GPA)
882 		return 0;
883 
884 	/* Note the offset, PDPTRs are 32 byte aligned when using PAE paging. */
885 	ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(real_gpa), pdpte,
886 				       cr3 & GENMASK(11, 5), sizeof(pdpte));
887 	if (ret < 0)
888 		return 0;
889 
890 	for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
891 		if ((pdpte[i] & PT_PRESENT_MASK) &&
892 		    (pdpte[i] & pdptr_rsvd_bits(vcpu))) {
893 			return 0;
894 		}
895 	}
896 
897 	/*
898 	 * Marking VCPU_EXREG_PDPTR dirty doesn't work for !tdp_enabled.
899 	 * Shadow page roots need to be reconstructed instead.
900 	 */
901 	if (!tdp_enabled && memcmp(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs)))
902 		kvm_mmu_free_roots(vcpu->kvm, mmu, KVM_MMU_ROOT_CURRENT);
903 
904 	memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
905 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
906 	kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
907 	vcpu->arch.pdptrs_from_userspace = false;
908 
909 	return 1;
910 }
911 EXPORT_SYMBOL_GPL(load_pdptrs);
912 
kvm_is_valid_cr0(struct kvm_vcpu * vcpu,unsigned long cr0)913 static bool kvm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
914 {
915 #ifdef CONFIG_X86_64
916 	if (cr0 & 0xffffffff00000000UL)
917 		return false;
918 #endif
919 
920 	if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
921 		return false;
922 
923 	if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
924 		return false;
925 
926 	return static_call(kvm_x86_is_valid_cr0)(vcpu, cr0);
927 }
928 
kvm_post_set_cr0(struct kvm_vcpu * vcpu,unsigned long old_cr0,unsigned long cr0)929 void kvm_post_set_cr0(struct kvm_vcpu *vcpu, unsigned long old_cr0, unsigned long cr0)
930 {
931 	/*
932 	 * CR0.WP is incorporated into the MMU role, but only for non-nested,
933 	 * indirect shadow MMUs.  If paging is disabled, no updates are needed
934 	 * as there are no permission bits to emulate.  If TDP is enabled, the
935 	 * MMU's metadata needs to be updated, e.g. so that emulating guest
936 	 * translations does the right thing, but there's no need to unload the
937 	 * root as CR0.WP doesn't affect SPTEs.
938 	 */
939 	if ((cr0 ^ old_cr0) == X86_CR0_WP) {
940 		if (!(cr0 & X86_CR0_PG))
941 			return;
942 
943 		if (tdp_enabled) {
944 			kvm_init_mmu(vcpu);
945 			return;
946 		}
947 	}
948 
949 	if ((cr0 ^ old_cr0) & X86_CR0_PG) {
950 		kvm_clear_async_pf_completion_queue(vcpu);
951 		kvm_async_pf_hash_reset(vcpu);
952 
953 		/*
954 		 * Clearing CR0.PG is defined to flush the TLB from the guest's
955 		 * perspective.
956 		 */
957 		if (!(cr0 & X86_CR0_PG))
958 			kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
959 	}
960 
961 	if ((cr0 ^ old_cr0) & KVM_MMU_CR0_ROLE_BITS)
962 		kvm_mmu_reset_context(vcpu);
963 
964 	if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
965 	    kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
966 	    !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
967 		kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
968 }
969 EXPORT_SYMBOL_GPL(kvm_post_set_cr0);
970 
kvm_set_cr0(struct kvm_vcpu * vcpu,unsigned long cr0)971 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
972 {
973 	unsigned long old_cr0 = kvm_read_cr0(vcpu);
974 
975 	if (!kvm_is_valid_cr0(vcpu, cr0))
976 		return 1;
977 
978 	cr0 |= X86_CR0_ET;
979 
980 	/* Write to CR0 reserved bits are ignored, even on Intel. */
981 	cr0 &= ~CR0_RESERVED_BITS;
982 
983 #ifdef CONFIG_X86_64
984 	if ((vcpu->arch.efer & EFER_LME) && !is_paging(vcpu) &&
985 	    (cr0 & X86_CR0_PG)) {
986 		int cs_db, cs_l;
987 
988 		if (!is_pae(vcpu))
989 			return 1;
990 		static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
991 		if (cs_l)
992 			return 1;
993 	}
994 #endif
995 	if (!(vcpu->arch.efer & EFER_LME) && (cr0 & X86_CR0_PG) &&
996 	    is_pae(vcpu) && ((cr0 ^ old_cr0) & X86_CR0_PDPTR_BITS) &&
997 	    !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
998 		return 1;
999 
1000 	if (!(cr0 & X86_CR0_PG) &&
1001 	    (is_64_bit_mode(vcpu) || kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)))
1002 		return 1;
1003 
1004 	static_call(kvm_x86_set_cr0)(vcpu, cr0);
1005 
1006 	kvm_post_set_cr0(vcpu, old_cr0, cr0);
1007 
1008 	return 0;
1009 }
1010 EXPORT_SYMBOL_GPL(kvm_set_cr0);
1011 
kvm_lmsw(struct kvm_vcpu * vcpu,unsigned long msw)1012 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
1013 {
1014 	(void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
1015 }
1016 EXPORT_SYMBOL_GPL(kvm_lmsw);
1017 
kvm_load_guest_xsave_state(struct kvm_vcpu * vcpu)1018 void kvm_load_guest_xsave_state(struct kvm_vcpu *vcpu)
1019 {
1020 	if (vcpu->arch.guest_state_protected)
1021 		return;
1022 
1023 	if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1024 
1025 		if (vcpu->arch.xcr0 != host_xcr0)
1026 			xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
1027 
1028 		if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1029 		    vcpu->arch.ia32_xss != host_xss)
1030 			wrmsrl(MSR_IA32_XSS, vcpu->arch.ia32_xss);
1031 	}
1032 
1033 	if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1034 	    vcpu->arch.pkru != vcpu->arch.host_pkru &&
1035 	    ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1036 	     kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)))
1037 		write_pkru(vcpu->arch.pkru);
1038 }
1039 EXPORT_SYMBOL_GPL(kvm_load_guest_xsave_state);
1040 
kvm_load_host_xsave_state(struct kvm_vcpu * vcpu)1041 void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
1042 {
1043 	if (vcpu->arch.guest_state_protected)
1044 		return;
1045 
1046 	if (cpu_feature_enabled(X86_FEATURE_PKU) &&
1047 	    ((vcpu->arch.xcr0 & XFEATURE_MASK_PKRU) ||
1048 	     kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE))) {
1049 		vcpu->arch.pkru = rdpkru();
1050 		if (vcpu->arch.pkru != vcpu->arch.host_pkru)
1051 			write_pkru(vcpu->arch.host_pkru);
1052 	}
1053 
1054 	if (kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)) {
1055 
1056 		if (vcpu->arch.xcr0 != host_xcr0)
1057 			xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
1058 
1059 		if (guest_can_use(vcpu, X86_FEATURE_XSAVES) &&
1060 		    vcpu->arch.ia32_xss != host_xss)
1061 			wrmsrl(MSR_IA32_XSS, host_xss);
1062 	}
1063 
1064 }
1065 EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
1066 
1067 #ifdef CONFIG_X86_64
kvm_guest_supported_xfd(struct kvm_vcpu * vcpu)1068 static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
1069 {
1070 	return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
1071 }
1072 #endif
1073 
__kvm_set_xcr(struct kvm_vcpu * vcpu,u32 index,u64 xcr)1074 static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
1075 {
1076 	u64 xcr0 = xcr;
1077 	u64 old_xcr0 = vcpu->arch.xcr0;
1078 	u64 valid_bits;
1079 
1080 	/* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now  */
1081 	if (index != XCR_XFEATURE_ENABLED_MASK)
1082 		return 1;
1083 	if (!(xcr0 & XFEATURE_MASK_FP))
1084 		return 1;
1085 	if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
1086 		return 1;
1087 
1088 	/*
1089 	 * Do not allow the guest to set bits that we do not support
1090 	 * saving.  However, xcr0 bit 0 is always set, even if the
1091 	 * emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
1092 	 */
1093 	valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
1094 	if (xcr0 & ~valid_bits)
1095 		return 1;
1096 
1097 	if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
1098 	    (!(xcr0 & XFEATURE_MASK_BNDCSR)))
1099 		return 1;
1100 
1101 	if (xcr0 & XFEATURE_MASK_AVX512) {
1102 		if (!(xcr0 & XFEATURE_MASK_YMM))
1103 			return 1;
1104 		if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
1105 			return 1;
1106 	}
1107 
1108 	if ((xcr0 & XFEATURE_MASK_XTILE) &&
1109 	    ((xcr0 & XFEATURE_MASK_XTILE) != XFEATURE_MASK_XTILE))
1110 		return 1;
1111 
1112 	vcpu->arch.xcr0 = xcr0;
1113 
1114 	if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
1115 		kvm_update_cpuid_runtime(vcpu);
1116 	return 0;
1117 }
1118 
kvm_emulate_xsetbv(struct kvm_vcpu * vcpu)1119 int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
1120 {
1121 	/* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
1122 	if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
1123 	    __kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
1124 		kvm_inject_gp(vcpu, 0);
1125 		return 1;
1126 	}
1127 
1128 	return kvm_skip_emulated_instruction(vcpu);
1129 }
1130 EXPORT_SYMBOL_GPL(kvm_emulate_xsetbv);
1131 
__kvm_is_valid_cr4(struct kvm_vcpu * vcpu,unsigned long cr4)1132 bool __kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1133 {
1134 	if (cr4 & cr4_reserved_bits)
1135 		return false;
1136 
1137 	if (cr4 & vcpu->arch.cr4_guest_rsvd_bits)
1138 		return false;
1139 
1140 	return true;
1141 }
1142 EXPORT_SYMBOL_GPL(__kvm_is_valid_cr4);
1143 
kvm_is_valid_cr4(struct kvm_vcpu * vcpu,unsigned long cr4)1144 static bool kvm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1145 {
1146 	return __kvm_is_valid_cr4(vcpu, cr4) &&
1147 	       static_call(kvm_x86_is_valid_cr4)(vcpu, cr4);
1148 }
1149 
kvm_post_set_cr4(struct kvm_vcpu * vcpu,unsigned long old_cr4,unsigned long cr4)1150 void kvm_post_set_cr4(struct kvm_vcpu *vcpu, unsigned long old_cr4, unsigned long cr4)
1151 {
1152 	if ((cr4 ^ old_cr4) & KVM_MMU_CR4_ROLE_BITS)
1153 		kvm_mmu_reset_context(vcpu);
1154 
1155 	/*
1156 	 * If CR4.PCIDE is changed 0 -> 1, there is no need to flush the TLB
1157 	 * according to the SDM; however, stale prev_roots could be reused
1158 	 * incorrectly in the future after a MOV to CR3 with NOFLUSH=1, so we
1159 	 * free them all.  This is *not* a superset of KVM_REQ_TLB_FLUSH_GUEST
1160 	 * or KVM_REQ_TLB_FLUSH_CURRENT, because the hardware TLB is not flushed,
1161 	 * so fall through.
1162 	 */
1163 	if (!tdp_enabled &&
1164 	    (cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE))
1165 		kvm_mmu_unload(vcpu);
1166 
1167 	/*
1168 	 * The TLB has to be flushed for all PCIDs if any of the following
1169 	 * (architecturally required) changes happen:
1170 	 * - CR4.PCIDE is changed from 1 to 0
1171 	 * - CR4.PGE is toggled
1172 	 *
1173 	 * This is a superset of KVM_REQ_TLB_FLUSH_CURRENT.
1174 	 */
1175 	if (((cr4 ^ old_cr4) & X86_CR4_PGE) ||
1176 	    (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
1177 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1178 
1179 	/*
1180 	 * The TLB has to be flushed for the current PCID if any of the
1181 	 * following (architecturally required) changes happen:
1182 	 * - CR4.SMEP is changed from 0 to 1
1183 	 * - CR4.PAE is toggled
1184 	 */
1185 	else if (((cr4 ^ old_cr4) & X86_CR4_PAE) ||
1186 		 ((cr4 & X86_CR4_SMEP) && !(old_cr4 & X86_CR4_SMEP)))
1187 		kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1188 
1189 }
1190 EXPORT_SYMBOL_GPL(kvm_post_set_cr4);
1191 
kvm_set_cr4(struct kvm_vcpu * vcpu,unsigned long cr4)1192 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1193 {
1194 	unsigned long old_cr4 = kvm_read_cr4(vcpu);
1195 
1196 	if (!kvm_is_valid_cr4(vcpu, cr4))
1197 		return 1;
1198 
1199 	if (is_long_mode(vcpu)) {
1200 		if (!(cr4 & X86_CR4_PAE))
1201 			return 1;
1202 		if ((cr4 ^ old_cr4) & X86_CR4_LA57)
1203 			return 1;
1204 	} else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
1205 		   && ((cr4 ^ old_cr4) & X86_CR4_PDPTR_BITS)
1206 		   && !load_pdptrs(vcpu, kvm_read_cr3(vcpu)))
1207 		return 1;
1208 
1209 	if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
1210 		/* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
1211 		if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
1212 			return 1;
1213 	}
1214 
1215 	static_call(kvm_x86_set_cr4)(vcpu, cr4);
1216 
1217 	kvm_post_set_cr4(vcpu, old_cr4, cr4);
1218 
1219 	return 0;
1220 }
1221 EXPORT_SYMBOL_GPL(kvm_set_cr4);
1222 
kvm_invalidate_pcid(struct kvm_vcpu * vcpu,unsigned long pcid)1223 static void kvm_invalidate_pcid(struct kvm_vcpu *vcpu, unsigned long pcid)
1224 {
1225 	struct kvm_mmu *mmu = vcpu->arch.mmu;
1226 	unsigned long roots_to_free = 0;
1227 	int i;
1228 
1229 	/*
1230 	 * MOV CR3 and INVPCID are usually not intercepted when using TDP, but
1231 	 * this is reachable when running EPT=1 and unrestricted_guest=0,  and
1232 	 * also via the emulator.  KVM's TDP page tables are not in the scope of
1233 	 * the invalidation, but the guest's TLB entries need to be flushed as
1234 	 * the CPU may have cached entries in its TLB for the target PCID.
1235 	 */
1236 	if (unlikely(tdp_enabled)) {
1237 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
1238 		return;
1239 	}
1240 
1241 	/*
1242 	 * If neither the current CR3 nor any of the prev_roots use the given
1243 	 * PCID, then nothing needs to be done here because a resync will
1244 	 * happen anyway before switching to any other CR3.
1245 	 */
1246 	if (kvm_get_active_pcid(vcpu) == pcid) {
1247 		kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1248 		kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1249 	}
1250 
1251 	/*
1252 	 * If PCID is disabled, there is no need to free prev_roots even if the
1253 	 * PCIDs for them are also 0, because MOV to CR3 always flushes the TLB
1254 	 * with PCIDE=0.
1255 	 */
1256 	if (!kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE))
1257 		return;
1258 
1259 	for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
1260 		if (kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd) == pcid)
1261 			roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
1262 
1263 	kvm_mmu_free_roots(vcpu->kvm, mmu, roots_to_free);
1264 }
1265 
kvm_set_cr3(struct kvm_vcpu * vcpu,unsigned long cr3)1266 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1267 {
1268 	bool skip_tlb_flush = false;
1269 	unsigned long pcid = 0;
1270 #ifdef CONFIG_X86_64
1271 	if (kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE)) {
1272 		skip_tlb_flush = cr3 & X86_CR3_PCID_NOFLUSH;
1273 		cr3 &= ~X86_CR3_PCID_NOFLUSH;
1274 		pcid = cr3 & X86_CR3_PCID_MASK;
1275 	}
1276 #endif
1277 
1278 	/* PDPTRs are always reloaded for PAE paging. */
1279 	if (cr3 == kvm_read_cr3(vcpu) && !is_pae_paging(vcpu))
1280 		goto handle_tlb_flush;
1281 
1282 	/*
1283 	 * Do not condition the GPA check on long mode, this helper is used to
1284 	 * stuff CR3, e.g. for RSM emulation, and there is no guarantee that
1285 	 * the current vCPU mode is accurate.
1286 	 */
1287 	if (kvm_vcpu_is_illegal_gpa(vcpu, cr3))
1288 		return 1;
1289 
1290 	if (is_pae_paging(vcpu) && !load_pdptrs(vcpu, cr3))
1291 		return 1;
1292 
1293 	if (cr3 != kvm_read_cr3(vcpu))
1294 		kvm_mmu_new_pgd(vcpu, cr3);
1295 
1296 	vcpu->arch.cr3 = cr3;
1297 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
1298 	/* Do not call post_set_cr3, we do not get here for confidential guests.  */
1299 
1300 handle_tlb_flush:
1301 	/*
1302 	 * A load of CR3 that flushes the TLB flushes only the current PCID,
1303 	 * even if PCID is disabled, in which case PCID=0 is flushed.  It's a
1304 	 * moot point in the end because _disabling_ PCID will flush all PCIDs,
1305 	 * and it's impossible to use a non-zero PCID when PCID is disabled,
1306 	 * i.e. only PCID=0 can be relevant.
1307 	 */
1308 	if (!skip_tlb_flush)
1309 		kvm_invalidate_pcid(vcpu, pcid);
1310 
1311 	return 0;
1312 }
1313 EXPORT_SYMBOL_GPL(kvm_set_cr3);
1314 
kvm_set_cr8(struct kvm_vcpu * vcpu,unsigned long cr8)1315 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
1316 {
1317 	if (cr8 & CR8_RESERVED_BITS)
1318 		return 1;
1319 	if (lapic_in_kernel(vcpu))
1320 		kvm_lapic_set_tpr(vcpu, cr8);
1321 	else
1322 		vcpu->arch.cr8 = cr8;
1323 	return 0;
1324 }
1325 EXPORT_SYMBOL_GPL(kvm_set_cr8);
1326 
kvm_get_cr8(struct kvm_vcpu * vcpu)1327 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
1328 {
1329 	if (lapic_in_kernel(vcpu))
1330 		return kvm_lapic_get_cr8(vcpu);
1331 	else
1332 		return vcpu->arch.cr8;
1333 }
1334 EXPORT_SYMBOL_GPL(kvm_get_cr8);
1335 
kvm_update_dr0123(struct kvm_vcpu * vcpu)1336 static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
1337 {
1338 	int i;
1339 
1340 	if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1341 		for (i = 0; i < KVM_NR_DB_REGS; i++)
1342 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
1343 	}
1344 }
1345 
kvm_update_dr7(struct kvm_vcpu * vcpu)1346 void kvm_update_dr7(struct kvm_vcpu *vcpu)
1347 {
1348 	unsigned long dr7;
1349 
1350 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1351 		dr7 = vcpu->arch.guest_debug_dr7;
1352 	else
1353 		dr7 = vcpu->arch.dr7;
1354 	static_call(kvm_x86_set_dr7)(vcpu, dr7);
1355 	vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
1356 	if (dr7 & DR7_BP_EN_MASK)
1357 		vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
1358 }
1359 EXPORT_SYMBOL_GPL(kvm_update_dr7);
1360 
kvm_dr6_fixed(struct kvm_vcpu * vcpu)1361 static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
1362 {
1363 	u64 fixed = DR6_FIXED_1;
1364 
1365 	if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
1366 		fixed |= DR6_RTM;
1367 
1368 	if (!guest_cpuid_has(vcpu, X86_FEATURE_BUS_LOCK_DETECT))
1369 		fixed |= DR6_BUS_LOCK;
1370 	return fixed;
1371 }
1372 
kvm_set_dr(struct kvm_vcpu * vcpu,int dr,unsigned long val)1373 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
1374 {
1375 	size_t size = ARRAY_SIZE(vcpu->arch.db);
1376 
1377 	switch (dr) {
1378 	case 0 ... 3:
1379 		vcpu->arch.db[array_index_nospec(dr, size)] = val;
1380 		if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1381 			vcpu->arch.eff_db[dr] = val;
1382 		break;
1383 	case 4:
1384 	case 6:
1385 		if (!kvm_dr6_valid(val))
1386 			return 1; /* #GP */
1387 		vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
1388 		break;
1389 	case 5:
1390 	default: /* 7 */
1391 		if (!kvm_dr7_valid(val))
1392 			return 1; /* #GP */
1393 		vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
1394 		kvm_update_dr7(vcpu);
1395 		break;
1396 	}
1397 
1398 	return 0;
1399 }
1400 EXPORT_SYMBOL_GPL(kvm_set_dr);
1401 
kvm_get_dr(struct kvm_vcpu * vcpu,int dr,unsigned long * val)1402 void kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
1403 {
1404 	size_t size = ARRAY_SIZE(vcpu->arch.db);
1405 
1406 	switch (dr) {
1407 	case 0 ... 3:
1408 		*val = vcpu->arch.db[array_index_nospec(dr, size)];
1409 		break;
1410 	case 4:
1411 	case 6:
1412 		*val = vcpu->arch.dr6;
1413 		break;
1414 	case 5:
1415 	default: /* 7 */
1416 		*val = vcpu->arch.dr7;
1417 		break;
1418 	}
1419 }
1420 EXPORT_SYMBOL_GPL(kvm_get_dr);
1421 
kvm_emulate_rdpmc(struct kvm_vcpu * vcpu)1422 int kvm_emulate_rdpmc(struct kvm_vcpu *vcpu)
1423 {
1424 	u32 ecx = kvm_rcx_read(vcpu);
1425 	u64 data;
1426 
1427 	if (kvm_pmu_rdpmc(vcpu, ecx, &data)) {
1428 		kvm_inject_gp(vcpu, 0);
1429 		return 1;
1430 	}
1431 
1432 	kvm_rax_write(vcpu, (u32)data);
1433 	kvm_rdx_write(vcpu, data >> 32);
1434 	return kvm_skip_emulated_instruction(vcpu);
1435 }
1436 EXPORT_SYMBOL_GPL(kvm_emulate_rdpmc);
1437 
1438 /*
1439  * The three MSR lists(msrs_to_save, emulated_msrs, msr_based_features) track
1440  * the set of MSRs that KVM exposes to userspace through KVM_GET_MSRS,
1441  * KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.  msrs_to_save holds MSRs that
1442  * require host support, i.e. should be probed via RDMSR.  emulated_msrs holds
1443  * MSRs that KVM emulates without strictly requiring host support.
1444  * msr_based_features holds MSRs that enumerate features, i.e. are effectively
1445  * CPUID leafs.  Note, msr_based_features isn't mutually exclusive with
1446  * msrs_to_save and emulated_msrs.
1447  */
1448 
1449 static const u32 msrs_to_save_base[] = {
1450 	MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
1451 	MSR_STAR,
1452 #ifdef CONFIG_X86_64
1453 	MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1454 #endif
1455 	MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
1456 	MSR_IA32_FEAT_CTL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
1457 	MSR_IA32_SPEC_CTRL, MSR_IA32_TSX_CTRL,
1458 	MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_STATUS, MSR_IA32_RTIT_CR3_MATCH,
1459 	MSR_IA32_RTIT_OUTPUT_BASE, MSR_IA32_RTIT_OUTPUT_MASK,
1460 	MSR_IA32_RTIT_ADDR0_A, MSR_IA32_RTIT_ADDR0_B,
1461 	MSR_IA32_RTIT_ADDR1_A, MSR_IA32_RTIT_ADDR1_B,
1462 	MSR_IA32_RTIT_ADDR2_A, MSR_IA32_RTIT_ADDR2_B,
1463 	MSR_IA32_RTIT_ADDR3_A, MSR_IA32_RTIT_ADDR3_B,
1464 	MSR_IA32_UMWAIT_CONTROL,
1465 
1466 	MSR_IA32_XFD, MSR_IA32_XFD_ERR,
1467 };
1468 
1469 static const u32 msrs_to_save_pmu[] = {
1470 	MSR_ARCH_PERFMON_FIXED_CTR0, MSR_ARCH_PERFMON_FIXED_CTR1,
1471 	MSR_ARCH_PERFMON_FIXED_CTR0 + 2,
1472 	MSR_CORE_PERF_FIXED_CTR_CTRL, MSR_CORE_PERF_GLOBAL_STATUS,
1473 	MSR_CORE_PERF_GLOBAL_CTRL, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1474 	MSR_IA32_PEBS_ENABLE, MSR_IA32_DS_AREA, MSR_PEBS_DATA_CFG,
1475 
1476 	/* This part of MSRs should match KVM_INTEL_PMC_MAX_GENERIC. */
1477 	MSR_ARCH_PERFMON_PERFCTR0, MSR_ARCH_PERFMON_PERFCTR1,
1478 	MSR_ARCH_PERFMON_PERFCTR0 + 2, MSR_ARCH_PERFMON_PERFCTR0 + 3,
1479 	MSR_ARCH_PERFMON_PERFCTR0 + 4, MSR_ARCH_PERFMON_PERFCTR0 + 5,
1480 	MSR_ARCH_PERFMON_PERFCTR0 + 6, MSR_ARCH_PERFMON_PERFCTR0 + 7,
1481 	MSR_ARCH_PERFMON_EVENTSEL0, MSR_ARCH_PERFMON_EVENTSEL1,
1482 	MSR_ARCH_PERFMON_EVENTSEL0 + 2, MSR_ARCH_PERFMON_EVENTSEL0 + 3,
1483 	MSR_ARCH_PERFMON_EVENTSEL0 + 4, MSR_ARCH_PERFMON_EVENTSEL0 + 5,
1484 	MSR_ARCH_PERFMON_EVENTSEL0 + 6, MSR_ARCH_PERFMON_EVENTSEL0 + 7,
1485 
1486 	MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
1487 	MSR_K7_PERFCTR0, MSR_K7_PERFCTR1, MSR_K7_PERFCTR2, MSR_K7_PERFCTR3,
1488 
1489 	/* This part of MSRs should match KVM_AMD_PMC_MAX_GENERIC. */
1490 	MSR_F15H_PERF_CTL0, MSR_F15H_PERF_CTL1, MSR_F15H_PERF_CTL2,
1491 	MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5,
1492 	MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2,
1493 	MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5,
1494 
1495 	MSR_AMD64_PERF_CNTR_GLOBAL_CTL,
1496 	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS,
1497 	MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR,
1498 };
1499 
1500 static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) +
1501 			ARRAY_SIZE(msrs_to_save_pmu)];
1502 static unsigned num_msrs_to_save;
1503 
1504 static const u32 emulated_msrs_all[] = {
1505 	MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1506 	MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1507 	HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1508 	HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
1509 	HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
1510 	HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1511 	HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
1512 	HV_X64_MSR_RESET,
1513 	HV_X64_MSR_VP_INDEX,
1514 	HV_X64_MSR_VP_RUNTIME,
1515 	HV_X64_MSR_SCONTROL,
1516 	HV_X64_MSR_STIMER0_CONFIG,
1517 	HV_X64_MSR_VP_ASSIST_PAGE,
1518 	HV_X64_MSR_REENLIGHTENMENT_CONTROL, HV_X64_MSR_TSC_EMULATION_CONTROL,
1519 	HV_X64_MSR_TSC_EMULATION_STATUS, HV_X64_MSR_TSC_INVARIANT_CONTROL,
1520 	HV_X64_MSR_SYNDBG_OPTIONS,
1521 	HV_X64_MSR_SYNDBG_CONTROL, HV_X64_MSR_SYNDBG_STATUS,
1522 	HV_X64_MSR_SYNDBG_SEND_BUFFER, HV_X64_MSR_SYNDBG_RECV_BUFFER,
1523 	HV_X64_MSR_SYNDBG_PENDING_BUFFER,
1524 
1525 	MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1526 	MSR_KVM_PV_EOI_EN, MSR_KVM_ASYNC_PF_INT, MSR_KVM_ASYNC_PF_ACK,
1527 
1528 	MSR_IA32_TSC_ADJUST,
1529 	MSR_IA32_TSC_DEADLINE,
1530 	MSR_IA32_ARCH_CAPABILITIES,
1531 	MSR_IA32_PERF_CAPABILITIES,
1532 	MSR_IA32_MISC_ENABLE,
1533 	MSR_IA32_MCG_STATUS,
1534 	MSR_IA32_MCG_CTL,
1535 	MSR_IA32_MCG_EXT_CTL,
1536 	MSR_IA32_SMBASE,
1537 	MSR_SMI_COUNT,
1538 	MSR_PLATFORM_INFO,
1539 	MSR_MISC_FEATURES_ENABLES,
1540 	MSR_AMD64_VIRT_SPEC_CTRL,
1541 	MSR_AMD64_TSC_RATIO,
1542 	MSR_IA32_POWER_CTL,
1543 	MSR_IA32_UCODE_REV,
1544 
1545 	/*
1546 	 * KVM always supports the "true" VMX control MSRs, even if the host
1547 	 * does not.  The VMX MSRs as a whole are considered "emulated" as KVM
1548 	 * doesn't strictly require them to exist in the host (ignoring that
1549 	 * KVM would refuse to load in the first place if the core set of MSRs
1550 	 * aren't supported).
1551 	 */
1552 	MSR_IA32_VMX_BASIC,
1553 	MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1554 	MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1555 	MSR_IA32_VMX_TRUE_EXIT_CTLS,
1556 	MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1557 	MSR_IA32_VMX_MISC,
1558 	MSR_IA32_VMX_CR0_FIXED0,
1559 	MSR_IA32_VMX_CR4_FIXED0,
1560 	MSR_IA32_VMX_VMCS_ENUM,
1561 	MSR_IA32_VMX_PROCBASED_CTLS2,
1562 	MSR_IA32_VMX_EPT_VPID_CAP,
1563 	MSR_IA32_VMX_VMFUNC,
1564 
1565 	MSR_K7_HWCR,
1566 	MSR_KVM_POLL_CONTROL,
1567 };
1568 
1569 static u32 emulated_msrs[ARRAY_SIZE(emulated_msrs_all)];
1570 static unsigned num_emulated_msrs;
1571 
1572 /*
1573  * List of MSRs that control the existence of MSR-based features, i.e. MSRs
1574  * that are effectively CPUID leafs.  VMX MSRs are also included in the set of
1575  * feature MSRs, but are handled separately to allow expedited lookups.
1576  */
1577 static const u32 msr_based_features_all_except_vmx[] = {
1578 	MSR_AMD64_DE_CFG,
1579 	MSR_IA32_UCODE_REV,
1580 	MSR_IA32_ARCH_CAPABILITIES,
1581 	MSR_IA32_PERF_CAPABILITIES,
1582 };
1583 
1584 static u32 msr_based_features[ARRAY_SIZE(msr_based_features_all_except_vmx) +
1585 			      (KVM_LAST_EMULATED_VMX_MSR - KVM_FIRST_EMULATED_VMX_MSR + 1)];
1586 static unsigned int num_msr_based_features;
1587 
1588 /*
1589  * All feature MSRs except uCode revID, which tracks the currently loaded uCode
1590  * patch, are immutable once the vCPU model is defined.
1591  */
kvm_is_immutable_feature_msr(u32 msr)1592 static bool kvm_is_immutable_feature_msr(u32 msr)
1593 {
1594 	int i;
1595 
1596 	if (msr >= KVM_FIRST_EMULATED_VMX_MSR && msr <= KVM_LAST_EMULATED_VMX_MSR)
1597 		return true;
1598 
1599 	for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++) {
1600 		if (msr == msr_based_features_all_except_vmx[i])
1601 			return msr != MSR_IA32_UCODE_REV;
1602 	}
1603 
1604 	return false;
1605 }
1606 
1607 /*
1608  * Some IA32_ARCH_CAPABILITIES bits have dependencies on MSRs that KVM
1609  * does not yet virtualize. These include:
1610  *   10 - MISC_PACKAGE_CTRLS
1611  *   11 - ENERGY_FILTERING_CTL
1612  *   12 - DOITM
1613  *   18 - FB_CLEAR_CTRL
1614  *   21 - XAPIC_DISABLE_STATUS
1615  *   23 - OVERCLOCKING_STATUS
1616  */
1617 
1618 #define KVM_SUPPORTED_ARCH_CAP \
1619 	(ARCH_CAP_RDCL_NO | ARCH_CAP_IBRS_ALL | ARCH_CAP_RSBA | \
1620 	 ARCH_CAP_SKIP_VMENTRY_L1DFLUSH | ARCH_CAP_SSB_NO | ARCH_CAP_MDS_NO | \
1621 	 ARCH_CAP_PSCHANGE_MC_NO | ARCH_CAP_TSX_CTRL_MSR | ARCH_CAP_TAA_NO | \
1622 	 ARCH_CAP_SBDR_SSDP_NO | ARCH_CAP_FBSDP_NO | ARCH_CAP_PSDP_NO | \
1623 	 ARCH_CAP_FB_CLEAR | ARCH_CAP_RRSBA | ARCH_CAP_PBRSB_NO | ARCH_CAP_GDS_NO | \
1624 	 ARCH_CAP_RFDS_NO | ARCH_CAP_RFDS_CLEAR | ARCH_CAP_BHI_NO)
1625 
kvm_get_arch_capabilities(void)1626 static u64 kvm_get_arch_capabilities(void)
1627 {
1628 	u64 data = host_arch_capabilities & KVM_SUPPORTED_ARCH_CAP;
1629 
1630 	/*
1631 	 * If nx_huge_pages is enabled, KVM's shadow paging will ensure that
1632 	 * the nested hypervisor runs with NX huge pages.  If it is not,
1633 	 * L1 is anyway vulnerable to ITLB_MULTIHIT exploits from other
1634 	 * L1 guests, so it need not worry about its own (L2) guests.
1635 	 */
1636 	data |= ARCH_CAP_PSCHANGE_MC_NO;
1637 
1638 	/*
1639 	 * If we're doing cache flushes (either "always" or "cond")
1640 	 * we will do one whenever the guest does a vmlaunch/vmresume.
1641 	 * If an outer hypervisor is doing the cache flush for us
1642 	 * (ARCH_CAP_SKIP_VMENTRY_L1DFLUSH), we can safely pass that
1643 	 * capability to the guest too, and if EPT is disabled we're not
1644 	 * vulnerable.  Overall, only VMENTER_L1D_FLUSH_NEVER will
1645 	 * require a nested hypervisor to do a flush of its own.
1646 	 */
1647 	if (l1tf_vmx_mitigation != VMENTER_L1D_FLUSH_NEVER)
1648 		data |= ARCH_CAP_SKIP_VMENTRY_L1DFLUSH;
1649 
1650 	if (!boot_cpu_has_bug(X86_BUG_CPU_MELTDOWN))
1651 		data |= ARCH_CAP_RDCL_NO;
1652 	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1653 		data |= ARCH_CAP_SSB_NO;
1654 	if (!boot_cpu_has_bug(X86_BUG_MDS))
1655 		data |= ARCH_CAP_MDS_NO;
1656 	if (!boot_cpu_has_bug(X86_BUG_RFDS))
1657 		data |= ARCH_CAP_RFDS_NO;
1658 
1659 	if (!boot_cpu_has(X86_FEATURE_RTM)) {
1660 		/*
1661 		 * If RTM=0 because the kernel has disabled TSX, the host might
1662 		 * have TAA_NO or TSX_CTRL.  Clear TAA_NO (the guest sees RTM=0
1663 		 * and therefore knows that there cannot be TAA) but keep
1664 		 * TSX_CTRL: some buggy userspaces leave it set on tsx=on hosts,
1665 		 * and we want to allow migrating those guests to tsx=off hosts.
1666 		 */
1667 		data &= ~ARCH_CAP_TAA_NO;
1668 	} else if (!boot_cpu_has_bug(X86_BUG_TAA)) {
1669 		data |= ARCH_CAP_TAA_NO;
1670 	} else {
1671 		/*
1672 		 * Nothing to do here; we emulate TSX_CTRL if present on the
1673 		 * host so the guest can choose between disabling TSX or
1674 		 * using VERW to clear CPU buffers.
1675 		 */
1676 	}
1677 
1678 	if (!boot_cpu_has_bug(X86_BUG_GDS) || gds_ucode_mitigated())
1679 		data |= ARCH_CAP_GDS_NO;
1680 
1681 	return data;
1682 }
1683 
kvm_get_msr_feature(struct kvm_msr_entry * msr)1684 static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1685 {
1686 	switch (msr->index) {
1687 	case MSR_IA32_ARCH_CAPABILITIES:
1688 		msr->data = kvm_get_arch_capabilities();
1689 		break;
1690 	case MSR_IA32_PERF_CAPABILITIES:
1691 		msr->data = kvm_caps.supported_perf_cap;
1692 		break;
1693 	case MSR_IA32_UCODE_REV:
1694 		rdmsrl_safe(msr->index, &msr->data);
1695 		break;
1696 	default:
1697 		return static_call(kvm_x86_get_msr_feature)(msr);
1698 	}
1699 	return 0;
1700 }
1701 
do_get_msr_feature(struct kvm_vcpu * vcpu,unsigned index,u64 * data)1702 static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1703 {
1704 	struct kvm_msr_entry msr;
1705 	int r;
1706 
1707 	msr.index = index;
1708 	r = kvm_get_msr_feature(&msr);
1709 
1710 	if (r == KVM_MSR_RET_INVALID) {
1711 		/* Unconditionally clear the output for simplicity */
1712 		*data = 0;
1713 		if (kvm_msr_ignored_check(index, 0, false))
1714 			r = 0;
1715 	}
1716 
1717 	if (r)
1718 		return r;
1719 
1720 	*data = msr.data;
1721 
1722 	return 0;
1723 }
1724 
__kvm_valid_efer(struct kvm_vcpu * vcpu,u64 efer)1725 static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1726 {
1727 	if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS))
1728 		return false;
1729 
1730 	if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
1731 		return false;
1732 
1733 	if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
1734 		return false;
1735 
1736 	if (efer & (EFER_LME | EFER_LMA) &&
1737 	    !guest_cpuid_has(vcpu, X86_FEATURE_LM))
1738 		return false;
1739 
1740 	if (efer & EFER_NX && !guest_cpuid_has(vcpu, X86_FEATURE_NX))
1741 		return false;
1742 
1743 	return true;
1744 
1745 }
kvm_valid_efer(struct kvm_vcpu * vcpu,u64 efer)1746 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
1747 {
1748 	if (efer & efer_reserved_bits)
1749 		return false;
1750 
1751 	return __kvm_valid_efer(vcpu, efer);
1752 }
1753 EXPORT_SYMBOL_GPL(kvm_valid_efer);
1754 
set_efer(struct kvm_vcpu * vcpu,struct msr_data * msr_info)1755 static int set_efer(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1756 {
1757 	u64 old_efer = vcpu->arch.efer;
1758 	u64 efer = msr_info->data;
1759 	int r;
1760 
1761 	if (efer & efer_reserved_bits)
1762 		return 1;
1763 
1764 	if (!msr_info->host_initiated) {
1765 		if (!__kvm_valid_efer(vcpu, efer))
1766 			return 1;
1767 
1768 		if (is_paging(vcpu) &&
1769 		    (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1770 			return 1;
1771 	}
1772 
1773 	efer &= ~EFER_LMA;
1774 	efer |= vcpu->arch.efer & EFER_LMA;
1775 
1776 	r = static_call(kvm_x86_set_efer)(vcpu, efer);
1777 	if (r) {
1778 		WARN_ON(r > 0);
1779 		return r;
1780 	}
1781 
1782 	if ((efer ^ old_efer) & KVM_MMU_EFER_ROLE_BITS)
1783 		kvm_mmu_reset_context(vcpu);
1784 
1785 	return 0;
1786 }
1787 
kvm_enable_efer_bits(u64 mask)1788 void kvm_enable_efer_bits(u64 mask)
1789 {
1790        efer_reserved_bits &= ~mask;
1791 }
1792 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1793 
kvm_msr_allowed(struct kvm_vcpu * vcpu,u32 index,u32 type)1794 bool kvm_msr_allowed(struct kvm_vcpu *vcpu, u32 index, u32 type)
1795 {
1796 	struct kvm_x86_msr_filter *msr_filter;
1797 	struct msr_bitmap_range *ranges;
1798 	struct kvm *kvm = vcpu->kvm;
1799 	bool allowed;
1800 	int idx;
1801 	u32 i;
1802 
1803 	/* x2APIC MSRs do not support filtering. */
1804 	if (index >= 0x800 && index <= 0x8ff)
1805 		return true;
1806 
1807 	idx = srcu_read_lock(&kvm->srcu);
1808 
1809 	msr_filter = srcu_dereference(kvm->arch.msr_filter, &kvm->srcu);
1810 	if (!msr_filter) {
1811 		allowed = true;
1812 		goto out;
1813 	}
1814 
1815 	allowed = msr_filter->default_allow;
1816 	ranges = msr_filter->ranges;
1817 
1818 	for (i = 0; i < msr_filter->count; i++) {
1819 		u32 start = ranges[i].base;
1820 		u32 end = start + ranges[i].nmsrs;
1821 		u32 flags = ranges[i].flags;
1822 		unsigned long *bitmap = ranges[i].bitmap;
1823 
1824 		if ((index >= start) && (index < end) && (flags & type)) {
1825 			allowed = test_bit(index - start, bitmap);
1826 			break;
1827 		}
1828 	}
1829 
1830 out:
1831 	srcu_read_unlock(&kvm->srcu, idx);
1832 
1833 	return allowed;
1834 }
1835 EXPORT_SYMBOL_GPL(kvm_msr_allowed);
1836 
1837 /*
1838  * Write @data into the MSR specified by @index.  Select MSR specific fault
1839  * checks are bypassed if @host_initiated is %true.
1840  * Returns 0 on success, non-0 otherwise.
1841  * Assumes vcpu_load() was already called.
1842  */
__kvm_set_msr(struct kvm_vcpu * vcpu,u32 index,u64 data,bool host_initiated)1843 static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
1844 			 bool host_initiated)
1845 {
1846 	struct msr_data msr;
1847 
1848 	switch (index) {
1849 	case MSR_FS_BASE:
1850 	case MSR_GS_BASE:
1851 	case MSR_KERNEL_GS_BASE:
1852 	case MSR_CSTAR:
1853 	case MSR_LSTAR:
1854 		if (is_noncanonical_address(data, vcpu))
1855 			return 1;
1856 		break;
1857 	case MSR_IA32_SYSENTER_EIP:
1858 	case MSR_IA32_SYSENTER_ESP:
1859 		/*
1860 		 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1861 		 * non-canonical address is written on Intel but not on
1862 		 * AMD (which ignores the top 32-bits, because it does
1863 		 * not implement 64-bit SYSENTER).
1864 		 *
1865 		 * 64-bit code should hence be able to write a non-canonical
1866 		 * value on AMD.  Making the address canonical ensures that
1867 		 * vmentry does not fail on Intel after writing a non-canonical
1868 		 * value, and that something deterministic happens if the guest
1869 		 * invokes 64-bit SYSENTER.
1870 		 */
1871 		data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
1872 		break;
1873 	case MSR_TSC_AUX:
1874 		if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1875 			return 1;
1876 
1877 		if (!host_initiated &&
1878 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1879 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1880 			return 1;
1881 
1882 		/*
1883 		 * Per Intel's SDM, bits 63:32 are reserved, but AMD's APM has
1884 		 * incomplete and conflicting architectural behavior.  Current
1885 		 * AMD CPUs completely ignore bits 63:32, i.e. they aren't
1886 		 * reserved and always read as zeros.  Enforce Intel's reserved
1887 		 * bits check if and only if the guest CPU is Intel, and clear
1888 		 * the bits in all other cases.  This ensures cross-vendor
1889 		 * migration will provide consistent behavior for the guest.
1890 		 */
1891 		if (guest_cpuid_is_intel(vcpu) && (data >> 32) != 0)
1892 			return 1;
1893 
1894 		data = (u32)data;
1895 		break;
1896 	}
1897 
1898 	msr.data = data;
1899 	msr.index = index;
1900 	msr.host_initiated = host_initiated;
1901 
1902 	return static_call(kvm_x86_set_msr)(vcpu, &msr);
1903 }
1904 
kvm_set_msr_ignored_check(struct kvm_vcpu * vcpu,u32 index,u64 data,bool host_initiated)1905 static int kvm_set_msr_ignored_check(struct kvm_vcpu *vcpu,
1906 				     u32 index, u64 data, bool host_initiated)
1907 {
1908 	int ret = __kvm_set_msr(vcpu, index, data, host_initiated);
1909 
1910 	if (ret == KVM_MSR_RET_INVALID)
1911 		if (kvm_msr_ignored_check(index, data, true))
1912 			ret = 0;
1913 
1914 	return ret;
1915 }
1916 
1917 /*
1918  * Read the MSR specified by @index into @data.  Select MSR specific fault
1919  * checks are bypassed if @host_initiated is %true.
1920  * Returns 0 on success, non-0 otherwise.
1921  * Assumes vcpu_load() was already called.
1922  */
__kvm_get_msr(struct kvm_vcpu * vcpu,u32 index,u64 * data,bool host_initiated)1923 int __kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data,
1924 		  bool host_initiated)
1925 {
1926 	struct msr_data msr;
1927 	int ret;
1928 
1929 	switch (index) {
1930 	case MSR_TSC_AUX:
1931 		if (!kvm_is_supported_user_return_msr(MSR_TSC_AUX))
1932 			return 1;
1933 
1934 		if (!host_initiated &&
1935 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP) &&
1936 		    !guest_cpuid_has(vcpu, X86_FEATURE_RDPID))
1937 			return 1;
1938 		break;
1939 	}
1940 
1941 	msr.index = index;
1942 	msr.host_initiated = host_initiated;
1943 
1944 	ret = static_call(kvm_x86_get_msr)(vcpu, &msr);
1945 	if (!ret)
1946 		*data = msr.data;
1947 	return ret;
1948 }
1949 
kvm_get_msr_ignored_check(struct kvm_vcpu * vcpu,u32 index,u64 * data,bool host_initiated)1950 static int kvm_get_msr_ignored_check(struct kvm_vcpu *vcpu,
1951 				     u32 index, u64 *data, bool host_initiated)
1952 {
1953 	int ret = __kvm_get_msr(vcpu, index, data, host_initiated);
1954 
1955 	if (ret == KVM_MSR_RET_INVALID) {
1956 		/* Unconditionally clear *data for simplicity */
1957 		*data = 0;
1958 		if (kvm_msr_ignored_check(index, 0, false))
1959 			ret = 0;
1960 	}
1961 
1962 	return ret;
1963 }
1964 
kvm_get_msr_with_filter(struct kvm_vcpu * vcpu,u32 index,u64 * data)1965 static int kvm_get_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1966 {
1967 	if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_READ))
1968 		return KVM_MSR_RET_FILTERED;
1969 	return kvm_get_msr_ignored_check(vcpu, index, data, false);
1970 }
1971 
kvm_set_msr_with_filter(struct kvm_vcpu * vcpu,u32 index,u64 data)1972 static int kvm_set_msr_with_filter(struct kvm_vcpu *vcpu, u32 index, u64 data)
1973 {
1974 	if (!kvm_msr_allowed(vcpu, index, KVM_MSR_FILTER_WRITE))
1975 		return KVM_MSR_RET_FILTERED;
1976 	return kvm_set_msr_ignored_check(vcpu, index, data, false);
1977 }
1978 
kvm_get_msr(struct kvm_vcpu * vcpu,u32 index,u64 * data)1979 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 index, u64 *data)
1980 {
1981 	return kvm_get_msr_ignored_check(vcpu, index, data, false);
1982 }
1983 EXPORT_SYMBOL_GPL(kvm_get_msr);
1984 
kvm_set_msr(struct kvm_vcpu * vcpu,u32 index,u64 data)1985 int kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data)
1986 {
1987 	return kvm_set_msr_ignored_check(vcpu, index, data, false);
1988 }
1989 EXPORT_SYMBOL_GPL(kvm_set_msr);
1990 
complete_userspace_rdmsr(struct kvm_vcpu * vcpu)1991 static void complete_userspace_rdmsr(struct kvm_vcpu *vcpu)
1992 {
1993 	if (!vcpu->run->msr.error) {
1994 		kvm_rax_write(vcpu, (u32)vcpu->run->msr.data);
1995 		kvm_rdx_write(vcpu, vcpu->run->msr.data >> 32);
1996 	}
1997 }
1998 
complete_emulated_msr_access(struct kvm_vcpu * vcpu)1999 static int complete_emulated_msr_access(struct kvm_vcpu *vcpu)
2000 {
2001 	return complete_emulated_insn_gp(vcpu, vcpu->run->msr.error);
2002 }
2003 
complete_emulated_rdmsr(struct kvm_vcpu * vcpu)2004 static int complete_emulated_rdmsr(struct kvm_vcpu *vcpu)
2005 {
2006 	complete_userspace_rdmsr(vcpu);
2007 	return complete_emulated_msr_access(vcpu);
2008 }
2009 
complete_fast_msr_access(struct kvm_vcpu * vcpu)2010 static int complete_fast_msr_access(struct kvm_vcpu *vcpu)
2011 {
2012 	return static_call(kvm_x86_complete_emulated_msr)(vcpu, vcpu->run->msr.error);
2013 }
2014 
complete_fast_rdmsr(struct kvm_vcpu * vcpu)2015 static int complete_fast_rdmsr(struct kvm_vcpu *vcpu)
2016 {
2017 	complete_userspace_rdmsr(vcpu);
2018 	return complete_fast_msr_access(vcpu);
2019 }
2020 
kvm_msr_reason(int r)2021 static u64 kvm_msr_reason(int r)
2022 {
2023 	switch (r) {
2024 	case KVM_MSR_RET_INVALID:
2025 		return KVM_MSR_EXIT_REASON_UNKNOWN;
2026 	case KVM_MSR_RET_FILTERED:
2027 		return KVM_MSR_EXIT_REASON_FILTER;
2028 	default:
2029 		return KVM_MSR_EXIT_REASON_INVAL;
2030 	}
2031 }
2032 
kvm_msr_user_space(struct kvm_vcpu * vcpu,u32 index,u32 exit_reason,u64 data,int (* completion)(struct kvm_vcpu * vcpu),int r)2033 static int kvm_msr_user_space(struct kvm_vcpu *vcpu, u32 index,
2034 			      u32 exit_reason, u64 data,
2035 			      int (*completion)(struct kvm_vcpu *vcpu),
2036 			      int r)
2037 {
2038 	u64 msr_reason = kvm_msr_reason(r);
2039 
2040 	/* Check if the user wanted to know about this MSR fault */
2041 	if (!(vcpu->kvm->arch.user_space_msr_mask & msr_reason))
2042 		return 0;
2043 
2044 	vcpu->run->exit_reason = exit_reason;
2045 	vcpu->run->msr.error = 0;
2046 	memset(vcpu->run->msr.pad, 0, sizeof(vcpu->run->msr.pad));
2047 	vcpu->run->msr.reason = msr_reason;
2048 	vcpu->run->msr.index = index;
2049 	vcpu->run->msr.data = data;
2050 	vcpu->arch.complete_userspace_io = completion;
2051 
2052 	return 1;
2053 }
2054 
kvm_emulate_rdmsr(struct kvm_vcpu * vcpu)2055 int kvm_emulate_rdmsr(struct kvm_vcpu *vcpu)
2056 {
2057 	u32 ecx = kvm_rcx_read(vcpu);
2058 	u64 data;
2059 	int r;
2060 
2061 	r = kvm_get_msr_with_filter(vcpu, ecx, &data);
2062 
2063 	if (!r) {
2064 		trace_kvm_msr_read(ecx, data);
2065 
2066 		kvm_rax_write(vcpu, data & -1u);
2067 		kvm_rdx_write(vcpu, (data >> 32) & -1u);
2068 	} else {
2069 		/* MSR read failed? See if we should ask user space */
2070 		if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_RDMSR, 0,
2071 				       complete_fast_rdmsr, r))
2072 			return 0;
2073 		trace_kvm_msr_read_ex(ecx);
2074 	}
2075 
2076 	return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2077 }
2078 EXPORT_SYMBOL_GPL(kvm_emulate_rdmsr);
2079 
kvm_emulate_wrmsr(struct kvm_vcpu * vcpu)2080 int kvm_emulate_wrmsr(struct kvm_vcpu *vcpu)
2081 {
2082 	u32 ecx = kvm_rcx_read(vcpu);
2083 	u64 data = kvm_read_edx_eax(vcpu);
2084 	int r;
2085 
2086 	r = kvm_set_msr_with_filter(vcpu, ecx, data);
2087 
2088 	if (!r) {
2089 		trace_kvm_msr_write(ecx, data);
2090 	} else {
2091 		/* MSR write failed? See if we should ask user space */
2092 		if (kvm_msr_user_space(vcpu, ecx, KVM_EXIT_X86_WRMSR, data,
2093 				       complete_fast_msr_access, r))
2094 			return 0;
2095 		/* Signal all other negative errors to userspace */
2096 		if (r < 0)
2097 			return r;
2098 		trace_kvm_msr_write_ex(ecx, data);
2099 	}
2100 
2101 	return static_call(kvm_x86_complete_emulated_msr)(vcpu, r);
2102 }
2103 EXPORT_SYMBOL_GPL(kvm_emulate_wrmsr);
2104 
kvm_emulate_as_nop(struct kvm_vcpu * vcpu)2105 int kvm_emulate_as_nop(struct kvm_vcpu *vcpu)
2106 {
2107 	return kvm_skip_emulated_instruction(vcpu);
2108 }
2109 
kvm_emulate_invd(struct kvm_vcpu * vcpu)2110 int kvm_emulate_invd(struct kvm_vcpu *vcpu)
2111 {
2112 	/* Treat an INVD instruction as a NOP and just skip it. */
2113 	return kvm_emulate_as_nop(vcpu);
2114 }
2115 EXPORT_SYMBOL_GPL(kvm_emulate_invd);
2116 
kvm_handle_invalid_op(struct kvm_vcpu * vcpu)2117 int kvm_handle_invalid_op(struct kvm_vcpu *vcpu)
2118 {
2119 	kvm_queue_exception(vcpu, UD_VECTOR);
2120 	return 1;
2121 }
2122 EXPORT_SYMBOL_GPL(kvm_handle_invalid_op);
2123 
2124 
kvm_emulate_monitor_mwait(struct kvm_vcpu * vcpu,const char * insn)2125 static int kvm_emulate_monitor_mwait(struct kvm_vcpu *vcpu, const char *insn)
2126 {
2127 	if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS) &&
2128 	    !guest_cpuid_has(vcpu, X86_FEATURE_MWAIT))
2129 		return kvm_handle_invalid_op(vcpu);
2130 
2131 	pr_warn_once("%s instruction emulated as NOP!\n", insn);
2132 	return kvm_emulate_as_nop(vcpu);
2133 }
kvm_emulate_mwait(struct kvm_vcpu * vcpu)2134 int kvm_emulate_mwait(struct kvm_vcpu *vcpu)
2135 {
2136 	return kvm_emulate_monitor_mwait(vcpu, "MWAIT");
2137 }
2138 EXPORT_SYMBOL_GPL(kvm_emulate_mwait);
2139 
kvm_emulate_monitor(struct kvm_vcpu * vcpu)2140 int kvm_emulate_monitor(struct kvm_vcpu *vcpu)
2141 {
2142 	return kvm_emulate_monitor_mwait(vcpu, "MONITOR");
2143 }
2144 EXPORT_SYMBOL_GPL(kvm_emulate_monitor);
2145 
kvm_vcpu_exit_request(struct kvm_vcpu * vcpu)2146 static inline bool kvm_vcpu_exit_request(struct kvm_vcpu *vcpu)
2147 {
2148 	xfer_to_guest_mode_prepare();
2149 	return vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu) ||
2150 		xfer_to_guest_mode_work_pending();
2151 }
2152 
2153 /*
2154  * The fast path for frequent and performance sensitive wrmsr emulation,
2155  * i.e. the sending of IPI, sending IPI early in the VM-Exit flow reduces
2156  * the latency of virtual IPI by avoiding the expensive bits of transitioning
2157  * from guest to host, e.g. reacquiring KVM's SRCU lock. In contrast to the
2158  * other cases which must be called after interrupts are enabled on the host.
2159  */
handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu * vcpu,u64 data)2160 static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data)
2161 {
2162 	if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(vcpu->arch.apic))
2163 		return 1;
2164 
2165 	if (((data & APIC_SHORT_MASK) == APIC_DEST_NOSHORT) &&
2166 	    ((data & APIC_DEST_MASK) == APIC_DEST_PHYSICAL) &&
2167 	    ((data & APIC_MODE_MASK) == APIC_DM_FIXED) &&
2168 	    ((u32)(data >> 32) != X2APIC_BROADCAST))
2169 		return kvm_x2apic_icr_write(vcpu->arch.apic, data);
2170 
2171 	return 1;
2172 }
2173 
handle_fastpath_set_tscdeadline(struct kvm_vcpu * vcpu,u64 data)2174 static int handle_fastpath_set_tscdeadline(struct kvm_vcpu *vcpu, u64 data)
2175 {
2176 	if (!kvm_can_use_hv_timer(vcpu))
2177 		return 1;
2178 
2179 	kvm_set_lapic_tscdeadline_msr(vcpu, data);
2180 	return 0;
2181 }
2182 
handle_fastpath_set_msr_irqoff(struct kvm_vcpu * vcpu)2183 fastpath_t handle_fastpath_set_msr_irqoff(struct kvm_vcpu *vcpu)
2184 {
2185 	u32 msr = kvm_rcx_read(vcpu);
2186 	u64 data;
2187 	fastpath_t ret = EXIT_FASTPATH_NONE;
2188 
2189 	kvm_vcpu_srcu_read_lock(vcpu);
2190 
2191 	switch (msr) {
2192 	case APIC_BASE_MSR + (APIC_ICR >> 4):
2193 		data = kvm_read_edx_eax(vcpu);
2194 		if (!handle_fastpath_set_x2apic_icr_irqoff(vcpu, data)) {
2195 			kvm_skip_emulated_instruction(vcpu);
2196 			ret = EXIT_FASTPATH_EXIT_HANDLED;
2197 		}
2198 		break;
2199 	case MSR_IA32_TSC_DEADLINE:
2200 		data = kvm_read_edx_eax(vcpu);
2201 		if (!handle_fastpath_set_tscdeadline(vcpu, data)) {
2202 			kvm_skip_emulated_instruction(vcpu);
2203 			ret = EXIT_FASTPATH_REENTER_GUEST;
2204 		}
2205 		break;
2206 	default:
2207 		break;
2208 	}
2209 
2210 	if (ret != EXIT_FASTPATH_NONE)
2211 		trace_kvm_msr_write(msr, data);
2212 
2213 	kvm_vcpu_srcu_read_unlock(vcpu);
2214 
2215 	return ret;
2216 }
2217 EXPORT_SYMBOL_GPL(handle_fastpath_set_msr_irqoff);
2218 
2219 /*
2220  * Adapt set_msr() to msr_io()'s calling convention
2221  */
do_get_msr(struct kvm_vcpu * vcpu,unsigned index,u64 * data)2222 static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2223 {
2224 	return kvm_get_msr_ignored_check(vcpu, index, data, true);
2225 }
2226 
do_set_msr(struct kvm_vcpu * vcpu,unsigned index,u64 * data)2227 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
2228 {
2229 	u64 val;
2230 
2231 	/*
2232 	 * Disallow writes to immutable feature MSRs after KVM_RUN.  KVM does
2233 	 * not support modifying the guest vCPU model on the fly, e.g. changing
2234 	 * the nVMX capabilities while L2 is running is nonsensical.  Ignore
2235 	 * writes of the same value, e.g. to allow userspace to blindly stuff
2236 	 * all MSRs when emulating RESET.
2237 	 */
2238 	if (kvm_vcpu_has_run(vcpu) && kvm_is_immutable_feature_msr(index)) {
2239 		if (do_get_msr(vcpu, index, &val) || *data != val)
2240 			return -EINVAL;
2241 
2242 		return 0;
2243 	}
2244 
2245 	return kvm_set_msr_ignored_check(vcpu, index, *data, true);
2246 }
2247 
2248 #ifdef CONFIG_X86_64
2249 struct pvclock_clock {
2250 	int vclock_mode;
2251 	u64 cycle_last;
2252 	u64 mask;
2253 	u32 mult;
2254 	u32 shift;
2255 	u64 base_cycles;
2256 	u64 offset;
2257 };
2258 
2259 struct pvclock_gtod_data {
2260 	seqcount_t	seq;
2261 
2262 	struct pvclock_clock clock; /* extract of a clocksource struct */
2263 	struct pvclock_clock raw_clock; /* extract of a clocksource struct */
2264 
2265 	ktime_t		offs_boot;
2266 	u64		wall_time_sec;
2267 };
2268 
2269 static struct pvclock_gtod_data pvclock_gtod_data;
2270 
update_pvclock_gtod(struct timekeeper * tk)2271 static void update_pvclock_gtod(struct timekeeper *tk)
2272 {
2273 	struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
2274 
2275 	write_seqcount_begin(&vdata->seq);
2276 
2277 	/* copy pvclock gtod data */
2278 	vdata->clock.vclock_mode	= tk->tkr_mono.clock->vdso_clock_mode;
2279 	vdata->clock.cycle_last		= tk->tkr_mono.cycle_last;
2280 	vdata->clock.mask		= tk->tkr_mono.mask;
2281 	vdata->clock.mult		= tk->tkr_mono.mult;
2282 	vdata->clock.shift		= tk->tkr_mono.shift;
2283 	vdata->clock.base_cycles	= tk->tkr_mono.xtime_nsec;
2284 	vdata->clock.offset		= tk->tkr_mono.base;
2285 
2286 	vdata->raw_clock.vclock_mode	= tk->tkr_raw.clock->vdso_clock_mode;
2287 	vdata->raw_clock.cycle_last	= tk->tkr_raw.cycle_last;
2288 	vdata->raw_clock.mask		= tk->tkr_raw.mask;
2289 	vdata->raw_clock.mult		= tk->tkr_raw.mult;
2290 	vdata->raw_clock.shift		= tk->tkr_raw.shift;
2291 	vdata->raw_clock.base_cycles	= tk->tkr_raw.xtime_nsec;
2292 	vdata->raw_clock.offset		= tk->tkr_raw.base;
2293 
2294 	vdata->wall_time_sec            = tk->xtime_sec;
2295 
2296 	vdata->offs_boot		= tk->offs_boot;
2297 
2298 	write_seqcount_end(&vdata->seq);
2299 }
2300 
get_kvmclock_base_ns(void)2301 static s64 get_kvmclock_base_ns(void)
2302 {
2303 	/* Count up from boot time, but with the frequency of the raw clock.  */
2304 	return ktime_to_ns(ktime_add(ktime_get_raw(), pvclock_gtod_data.offs_boot));
2305 }
2306 #else
get_kvmclock_base_ns(void)2307 static s64 get_kvmclock_base_ns(void)
2308 {
2309 	/* Master clock not used, so we can just use CLOCK_BOOTTIME.  */
2310 	return ktime_get_boottime_ns();
2311 }
2312 #endif
2313 
kvm_write_wall_clock(struct kvm * kvm,gpa_t wall_clock,int sec_hi_ofs)2314 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock, int sec_hi_ofs)
2315 {
2316 	int version;
2317 	int r;
2318 	struct pvclock_wall_clock wc;
2319 	u32 wc_sec_hi;
2320 	u64 wall_nsec;
2321 
2322 	if (!wall_clock)
2323 		return;
2324 
2325 	r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
2326 	if (r)
2327 		return;
2328 
2329 	if (version & 1)
2330 		++version;  /* first time write, random junk */
2331 
2332 	++version;
2333 
2334 	if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
2335 		return;
2336 
2337 	/*
2338 	 * The guest calculates current wall clock time by adding
2339 	 * system time (updated by kvm_guest_time_update below) to the
2340 	 * wall clock specified here.  We do the reverse here.
2341 	 */
2342 	wall_nsec = ktime_get_real_ns() - get_kvmclock_ns(kvm);
2343 
2344 	wc.nsec = do_div(wall_nsec, 1000000000);
2345 	wc.sec = (u32)wall_nsec; /* overflow in 2106 guest time */
2346 	wc.version = version;
2347 
2348 	kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
2349 
2350 	if (sec_hi_ofs) {
2351 		wc_sec_hi = wall_nsec >> 32;
2352 		kvm_write_guest(kvm, wall_clock + sec_hi_ofs,
2353 				&wc_sec_hi, sizeof(wc_sec_hi));
2354 	}
2355 
2356 	version++;
2357 	kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
2358 }
2359 
kvm_write_system_time(struct kvm_vcpu * vcpu,gpa_t system_time,bool old_msr,bool host_initiated)2360 static void kvm_write_system_time(struct kvm_vcpu *vcpu, gpa_t system_time,
2361 				  bool old_msr, bool host_initiated)
2362 {
2363 	struct kvm_arch *ka = &vcpu->kvm->arch;
2364 
2365 	if (vcpu->vcpu_id == 0 && !host_initiated) {
2366 		if (ka->boot_vcpu_runs_old_kvmclock != old_msr)
2367 			kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2368 
2369 		ka->boot_vcpu_runs_old_kvmclock = old_msr;
2370 	}
2371 
2372 	vcpu->arch.time = system_time;
2373 	kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
2374 
2375 	/* we verify if the enable bit is set... */
2376 	if (system_time & 1)
2377 		kvm_gpc_activate(&vcpu->arch.pv_time, system_time & ~1ULL,
2378 				 sizeof(struct pvclock_vcpu_time_info));
2379 	else
2380 		kvm_gpc_deactivate(&vcpu->arch.pv_time);
2381 
2382 	return;
2383 }
2384 
div_frac(uint32_t dividend,uint32_t divisor)2385 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
2386 {
2387 	do_shl32_div32(dividend, divisor);
2388 	return dividend;
2389 }
2390 
kvm_get_time_scale(uint64_t scaled_hz,uint64_t base_hz,s8 * pshift,u32 * pmultiplier)2391 static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
2392 			       s8 *pshift, u32 *pmultiplier)
2393 {
2394 	uint64_t scaled64;
2395 	int32_t  shift = 0;
2396 	uint64_t tps64;
2397 	uint32_t tps32;
2398 
2399 	tps64 = base_hz;
2400 	scaled64 = scaled_hz;
2401 	while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
2402 		tps64 >>= 1;
2403 		shift--;
2404 	}
2405 
2406 	tps32 = (uint32_t)tps64;
2407 	while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
2408 		if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
2409 			scaled64 >>= 1;
2410 		else
2411 			tps32 <<= 1;
2412 		shift++;
2413 	}
2414 
2415 	*pshift = shift;
2416 	*pmultiplier = div_frac(scaled64, tps32);
2417 }
2418 
2419 #ifdef CONFIG_X86_64
2420 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
2421 #endif
2422 
2423 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
2424 static unsigned long max_tsc_khz;
2425 
adjust_tsc_khz(u32 khz,s32 ppm)2426 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
2427 {
2428 	u64 v = (u64)khz * (1000000 + ppm);
2429 	do_div(v, 1000000);
2430 	return v;
2431 }
2432 
2433 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier);
2434 
set_tsc_khz(struct kvm_vcpu * vcpu,u32 user_tsc_khz,bool scale)2435 static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
2436 {
2437 	u64 ratio;
2438 
2439 	/* Guest TSC same frequency as host TSC? */
2440 	if (!scale) {
2441 		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2442 		return 0;
2443 	}
2444 
2445 	/* TSC scaling supported? */
2446 	if (!kvm_caps.has_tsc_control) {
2447 		if (user_tsc_khz > tsc_khz) {
2448 			vcpu->arch.tsc_catchup = 1;
2449 			vcpu->arch.tsc_always_catchup = 1;
2450 			return 0;
2451 		} else {
2452 			pr_warn_ratelimited("user requested TSC rate below hardware speed\n");
2453 			return -1;
2454 		}
2455 	}
2456 
2457 	/* TSC scaling required  - calculate ratio */
2458 	ratio = mul_u64_u32_div(1ULL << kvm_caps.tsc_scaling_ratio_frac_bits,
2459 				user_tsc_khz, tsc_khz);
2460 
2461 	if (ratio == 0 || ratio >= kvm_caps.max_tsc_scaling_ratio) {
2462 		pr_warn_ratelimited("Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
2463 			            user_tsc_khz);
2464 		return -1;
2465 	}
2466 
2467 	kvm_vcpu_write_tsc_multiplier(vcpu, ratio);
2468 	return 0;
2469 }
2470 
kvm_set_tsc_khz(struct kvm_vcpu * vcpu,u32 user_tsc_khz)2471 static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
2472 {
2473 	u32 thresh_lo, thresh_hi;
2474 	int use_scaling = 0;
2475 
2476 	/* tsc_khz can be zero if TSC calibration fails */
2477 	if (user_tsc_khz == 0) {
2478 		/* set tsc_scaling_ratio to a safe value */
2479 		kvm_vcpu_write_tsc_multiplier(vcpu, kvm_caps.default_tsc_scaling_ratio);
2480 		return -1;
2481 	}
2482 
2483 	/* Compute a scale to convert nanoseconds in TSC cycles */
2484 	kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
2485 			   &vcpu->arch.virtual_tsc_shift,
2486 			   &vcpu->arch.virtual_tsc_mult);
2487 	vcpu->arch.virtual_tsc_khz = user_tsc_khz;
2488 
2489 	/*
2490 	 * Compute the variation in TSC rate which is acceptable
2491 	 * within the range of tolerance and decide if the
2492 	 * rate being applied is within that bounds of the hardware
2493 	 * rate.  If so, no scaling or compensation need be done.
2494 	 */
2495 	thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
2496 	thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
2497 	if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
2498 		pr_debug("requested TSC rate %u falls outside tolerance [%u,%u]\n",
2499 			 user_tsc_khz, thresh_lo, thresh_hi);
2500 		use_scaling = 1;
2501 	}
2502 	return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
2503 }
2504 
compute_guest_tsc(struct kvm_vcpu * vcpu,s64 kernel_ns)2505 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
2506 {
2507 	u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
2508 				      vcpu->arch.virtual_tsc_mult,
2509 				      vcpu->arch.virtual_tsc_shift);
2510 	tsc += vcpu->arch.this_tsc_write;
2511 	return tsc;
2512 }
2513 
2514 #ifdef CONFIG_X86_64
gtod_is_based_on_tsc(int mode)2515 static inline int gtod_is_based_on_tsc(int mode)
2516 {
2517 	return mode == VDSO_CLOCKMODE_TSC || mode == VDSO_CLOCKMODE_HVCLOCK;
2518 }
2519 #endif
2520 
kvm_track_tsc_matching(struct kvm_vcpu * vcpu)2521 static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
2522 {
2523 #ifdef CONFIG_X86_64
2524 	bool vcpus_matched;
2525 	struct kvm_arch *ka = &vcpu->kvm->arch;
2526 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2527 
2528 	vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2529 			 atomic_read(&vcpu->kvm->online_vcpus));
2530 
2531 	/*
2532 	 * Once the masterclock is enabled, always perform request in
2533 	 * order to update it.
2534 	 *
2535 	 * In order to enable masterclock, the host clocksource must be TSC
2536 	 * and the vcpus need to have matched TSCs.  When that happens,
2537 	 * perform request to enable masterclock.
2538 	 */
2539 	if (ka->use_master_clock ||
2540 	    (gtod_is_based_on_tsc(gtod->clock.vclock_mode) && vcpus_matched))
2541 		kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
2542 
2543 	trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
2544 			    atomic_read(&vcpu->kvm->online_vcpus),
2545 		            ka->use_master_clock, gtod->clock.vclock_mode);
2546 #endif
2547 }
2548 
2549 /*
2550  * Multiply tsc by a fixed point number represented by ratio.
2551  *
2552  * The most significant 64-N bits (mult) of ratio represent the
2553  * integral part of the fixed point number; the remaining N bits
2554  * (frac) represent the fractional part, ie. ratio represents a fixed
2555  * point number (mult + frac * 2^(-N)).
2556  *
2557  * N equals to kvm_caps.tsc_scaling_ratio_frac_bits.
2558  */
__scale_tsc(u64 ratio,u64 tsc)2559 static inline u64 __scale_tsc(u64 ratio, u64 tsc)
2560 {
2561 	return mul_u64_u64_shr(tsc, ratio, kvm_caps.tsc_scaling_ratio_frac_bits);
2562 }
2563 
kvm_scale_tsc(u64 tsc,u64 ratio)2564 u64 kvm_scale_tsc(u64 tsc, u64 ratio)
2565 {
2566 	u64 _tsc = tsc;
2567 
2568 	if (ratio != kvm_caps.default_tsc_scaling_ratio)
2569 		_tsc = __scale_tsc(ratio, tsc);
2570 
2571 	return _tsc;
2572 }
2573 
kvm_compute_l1_tsc_offset(struct kvm_vcpu * vcpu,u64 target_tsc)2574 static u64 kvm_compute_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2575 {
2576 	u64 tsc;
2577 
2578 	tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio);
2579 
2580 	return target_tsc - tsc;
2581 }
2582 
kvm_read_l1_tsc(struct kvm_vcpu * vcpu,u64 host_tsc)2583 u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2584 {
2585 	return vcpu->arch.l1_tsc_offset +
2586 		kvm_scale_tsc(host_tsc, vcpu->arch.l1_tsc_scaling_ratio);
2587 }
2588 EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
2589 
kvm_calc_nested_tsc_offset(u64 l1_offset,u64 l2_offset,u64 l2_multiplier)2590 u64 kvm_calc_nested_tsc_offset(u64 l1_offset, u64 l2_offset, u64 l2_multiplier)
2591 {
2592 	u64 nested_offset;
2593 
2594 	if (l2_multiplier == kvm_caps.default_tsc_scaling_ratio)
2595 		nested_offset = l1_offset;
2596 	else
2597 		nested_offset = mul_s64_u64_shr((s64) l1_offset, l2_multiplier,
2598 						kvm_caps.tsc_scaling_ratio_frac_bits);
2599 
2600 	nested_offset += l2_offset;
2601 	return nested_offset;
2602 }
2603 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_offset);
2604 
kvm_calc_nested_tsc_multiplier(u64 l1_multiplier,u64 l2_multiplier)2605 u64 kvm_calc_nested_tsc_multiplier(u64 l1_multiplier, u64 l2_multiplier)
2606 {
2607 	if (l2_multiplier != kvm_caps.default_tsc_scaling_ratio)
2608 		return mul_u64_u64_shr(l1_multiplier, l2_multiplier,
2609 				       kvm_caps.tsc_scaling_ratio_frac_bits);
2610 
2611 	return l1_multiplier;
2612 }
2613 EXPORT_SYMBOL_GPL(kvm_calc_nested_tsc_multiplier);
2614 
kvm_vcpu_write_tsc_offset(struct kvm_vcpu * vcpu,u64 l1_offset)2615 static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 l1_offset)
2616 {
2617 	trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2618 				   vcpu->arch.l1_tsc_offset,
2619 				   l1_offset);
2620 
2621 	vcpu->arch.l1_tsc_offset = l1_offset;
2622 
2623 	/*
2624 	 * If we are here because L1 chose not to trap WRMSR to TSC then
2625 	 * according to the spec this should set L1's TSC (as opposed to
2626 	 * setting L1's offset for L2).
2627 	 */
2628 	if (is_guest_mode(vcpu))
2629 		vcpu->arch.tsc_offset = kvm_calc_nested_tsc_offset(
2630 			l1_offset,
2631 			static_call(kvm_x86_get_l2_tsc_offset)(vcpu),
2632 			static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2633 	else
2634 		vcpu->arch.tsc_offset = l1_offset;
2635 
2636 	static_call(kvm_x86_write_tsc_offset)(vcpu);
2637 }
2638 
kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu * vcpu,u64 l1_multiplier)2639 static void kvm_vcpu_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 l1_multiplier)
2640 {
2641 	vcpu->arch.l1_tsc_scaling_ratio = l1_multiplier;
2642 
2643 	/* Userspace is changing the multiplier while L2 is active */
2644 	if (is_guest_mode(vcpu))
2645 		vcpu->arch.tsc_scaling_ratio = kvm_calc_nested_tsc_multiplier(
2646 			l1_multiplier,
2647 			static_call(kvm_x86_get_l2_tsc_multiplier)(vcpu));
2648 	else
2649 		vcpu->arch.tsc_scaling_ratio = l1_multiplier;
2650 
2651 	if (kvm_caps.has_tsc_control)
2652 		static_call(kvm_x86_write_tsc_multiplier)(vcpu);
2653 }
2654 
kvm_check_tsc_unstable(void)2655 static inline bool kvm_check_tsc_unstable(void)
2656 {
2657 #ifdef CONFIG_X86_64
2658 	/*
2659 	 * TSC is marked unstable when we're running on Hyper-V,
2660 	 * 'TSC page' clocksource is good.
2661 	 */
2662 	if (pvclock_gtod_data.clock.vclock_mode == VDSO_CLOCKMODE_HVCLOCK)
2663 		return false;
2664 #endif
2665 	return check_tsc_unstable();
2666 }
2667 
2668 /*
2669  * Infers attempts to synchronize the guest's tsc from host writes. Sets the
2670  * offset for the vcpu and tracks the TSC matching generation that the vcpu
2671  * participates in.
2672  */
__kvm_synchronize_tsc(struct kvm_vcpu * vcpu,u64 offset,u64 tsc,u64 ns,bool matched)2673 static void __kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 offset, u64 tsc,
2674 				  u64 ns, bool matched)
2675 {
2676 	struct kvm *kvm = vcpu->kvm;
2677 
2678 	lockdep_assert_held(&kvm->arch.tsc_write_lock);
2679 
2680 	/*
2681 	 * We also track th most recent recorded KHZ, write and time to
2682 	 * allow the matching interval to be extended at each write.
2683 	 */
2684 	kvm->arch.last_tsc_nsec = ns;
2685 	kvm->arch.last_tsc_write = tsc;
2686 	kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
2687 	kvm->arch.last_tsc_offset = offset;
2688 
2689 	vcpu->arch.last_guest_tsc = tsc;
2690 
2691 	kvm_vcpu_write_tsc_offset(vcpu, offset);
2692 
2693 	if (!matched) {
2694 		/*
2695 		 * We split periods of matched TSC writes into generations.
2696 		 * For each generation, we track the original measured
2697 		 * nanosecond time, offset, and write, so if TSCs are in
2698 		 * sync, we can match exact offset, and if not, we can match
2699 		 * exact software computation in compute_guest_tsc()
2700 		 *
2701 		 * These values are tracked in kvm->arch.cur_xxx variables.
2702 		 */
2703 		kvm->arch.cur_tsc_generation++;
2704 		kvm->arch.cur_tsc_nsec = ns;
2705 		kvm->arch.cur_tsc_write = tsc;
2706 		kvm->arch.cur_tsc_offset = offset;
2707 		kvm->arch.nr_vcpus_matched_tsc = 0;
2708 	} else if (vcpu->arch.this_tsc_generation != kvm->arch.cur_tsc_generation) {
2709 		kvm->arch.nr_vcpus_matched_tsc++;
2710 	}
2711 
2712 	/* Keep track of which generation this VCPU has synchronized to */
2713 	vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
2714 	vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
2715 	vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
2716 
2717 	kvm_track_tsc_matching(vcpu);
2718 }
2719 
kvm_synchronize_tsc(struct kvm_vcpu * vcpu,u64 data)2720 static void kvm_synchronize_tsc(struct kvm_vcpu *vcpu, u64 data)
2721 {
2722 	struct kvm *kvm = vcpu->kvm;
2723 	u64 offset, ns, elapsed;
2724 	unsigned long flags;
2725 	bool matched = false;
2726 	bool synchronizing = false;
2727 
2728 	raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
2729 	offset = kvm_compute_l1_tsc_offset(vcpu, data);
2730 	ns = get_kvmclock_base_ns();
2731 	elapsed = ns - kvm->arch.last_tsc_nsec;
2732 
2733 	if (vcpu->arch.virtual_tsc_khz) {
2734 		if (data == 0) {
2735 			/*
2736 			 * detection of vcpu initialization -- need to sync
2737 			 * with other vCPUs. This particularly helps to keep
2738 			 * kvm_clock stable after CPU hotplug
2739 			 */
2740 			synchronizing = true;
2741 		} else {
2742 			u64 tsc_exp = kvm->arch.last_tsc_write +
2743 						nsec_to_cycles(vcpu, elapsed);
2744 			u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
2745 			/*
2746 			 * Special case: TSC write with a small delta (1 second)
2747 			 * of virtual cycle time against real time is
2748 			 * interpreted as an attempt to synchronize the CPU.
2749 			 */
2750 			synchronizing = data < tsc_exp + tsc_hz &&
2751 					data + tsc_hz > tsc_exp;
2752 		}
2753 	}
2754 
2755 	/*
2756 	 * For a reliable TSC, we can match TSC offsets, and for an unstable
2757 	 * TSC, we add elapsed time in this computation.  We could let the
2758 	 * compensation code attempt to catch up if we fall behind, but
2759 	 * it's better to try to match offsets from the beginning.
2760          */
2761 	if (synchronizing &&
2762 	    vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
2763 		if (!kvm_check_tsc_unstable()) {
2764 			offset = kvm->arch.cur_tsc_offset;
2765 		} else {
2766 			u64 delta = nsec_to_cycles(vcpu, elapsed);
2767 			data += delta;
2768 			offset = kvm_compute_l1_tsc_offset(vcpu, data);
2769 		}
2770 		matched = true;
2771 	}
2772 
2773 	__kvm_synchronize_tsc(vcpu, offset, data, ns, matched);
2774 	raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
2775 }
2776 
adjust_tsc_offset_guest(struct kvm_vcpu * vcpu,s64 adjustment)2777 static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
2778 					   s64 adjustment)
2779 {
2780 	u64 tsc_offset = vcpu->arch.l1_tsc_offset;
2781 	kvm_vcpu_write_tsc_offset(vcpu, tsc_offset + adjustment);
2782 }
2783 
adjust_tsc_offset_host(struct kvm_vcpu * vcpu,s64 adjustment)2784 static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
2785 {
2786 	if (vcpu->arch.l1_tsc_scaling_ratio != kvm_caps.default_tsc_scaling_ratio)
2787 		WARN_ON(adjustment < 0);
2788 	adjustment = kvm_scale_tsc((u64) adjustment,
2789 				   vcpu->arch.l1_tsc_scaling_ratio);
2790 	adjust_tsc_offset_guest(vcpu, adjustment);
2791 }
2792 
2793 #ifdef CONFIG_X86_64
2794 
read_tsc(void)2795 static u64 read_tsc(void)
2796 {
2797 	u64 ret = (u64)rdtsc_ordered();
2798 	u64 last = pvclock_gtod_data.clock.cycle_last;
2799 
2800 	if (likely(ret >= last))
2801 		return ret;
2802 
2803 	/*
2804 	 * GCC likes to generate cmov here, but this branch is extremely
2805 	 * predictable (it's just a function of time and the likely is
2806 	 * very likely) and there's a data dependence, so force GCC
2807 	 * to generate a branch instead.  I don't barrier() because
2808 	 * we don't actually need a barrier, and if this function
2809 	 * ever gets inlined it will generate worse code.
2810 	 */
2811 	asm volatile ("");
2812 	return last;
2813 }
2814 
vgettsc(struct pvclock_clock * clock,u64 * tsc_timestamp,int * mode)2815 static inline u64 vgettsc(struct pvclock_clock *clock, u64 *tsc_timestamp,
2816 			  int *mode)
2817 {
2818 	u64 tsc_pg_val;
2819 	long v;
2820 
2821 	switch (clock->vclock_mode) {
2822 	case VDSO_CLOCKMODE_HVCLOCK:
2823 		if (hv_read_tsc_page_tsc(hv_get_tsc_page(),
2824 					 tsc_timestamp, &tsc_pg_val)) {
2825 			/* TSC page valid */
2826 			*mode = VDSO_CLOCKMODE_HVCLOCK;
2827 			v = (tsc_pg_val - clock->cycle_last) &
2828 				clock->mask;
2829 		} else {
2830 			/* TSC page invalid */
2831 			*mode = VDSO_CLOCKMODE_NONE;
2832 		}
2833 		break;
2834 	case VDSO_CLOCKMODE_TSC:
2835 		*mode = VDSO_CLOCKMODE_TSC;
2836 		*tsc_timestamp = read_tsc();
2837 		v = (*tsc_timestamp - clock->cycle_last) &
2838 			clock->mask;
2839 		break;
2840 	default:
2841 		*mode = VDSO_CLOCKMODE_NONE;
2842 	}
2843 
2844 	if (*mode == VDSO_CLOCKMODE_NONE)
2845 		*tsc_timestamp = v = 0;
2846 
2847 	return v * clock->mult;
2848 }
2849 
do_monotonic_raw(s64 * t,u64 * tsc_timestamp)2850 static int do_monotonic_raw(s64 *t, u64 *tsc_timestamp)
2851 {
2852 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2853 	unsigned long seq;
2854 	int mode;
2855 	u64 ns;
2856 
2857 	do {
2858 		seq = read_seqcount_begin(&gtod->seq);
2859 		ns = gtod->raw_clock.base_cycles;
2860 		ns += vgettsc(&gtod->raw_clock, tsc_timestamp, &mode);
2861 		ns >>= gtod->raw_clock.shift;
2862 		ns += ktime_to_ns(ktime_add(gtod->raw_clock.offset, gtod->offs_boot));
2863 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2864 	*t = ns;
2865 
2866 	return mode;
2867 }
2868 
do_realtime(struct timespec64 * ts,u64 * tsc_timestamp)2869 static int do_realtime(struct timespec64 *ts, u64 *tsc_timestamp)
2870 {
2871 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
2872 	unsigned long seq;
2873 	int mode;
2874 	u64 ns;
2875 
2876 	do {
2877 		seq = read_seqcount_begin(&gtod->seq);
2878 		ts->tv_sec = gtod->wall_time_sec;
2879 		ns = gtod->clock.base_cycles;
2880 		ns += vgettsc(&gtod->clock, tsc_timestamp, &mode);
2881 		ns >>= gtod->clock.shift;
2882 	} while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
2883 
2884 	ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
2885 	ts->tv_nsec = ns;
2886 
2887 	return mode;
2888 }
2889 
2890 /* returns true if host is using TSC based clocksource */
kvm_get_time_and_clockread(s64 * kernel_ns,u64 * tsc_timestamp)2891 static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *tsc_timestamp)
2892 {
2893 	/* checked again under seqlock below */
2894 	if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2895 		return false;
2896 
2897 	return gtod_is_based_on_tsc(do_monotonic_raw(kernel_ns,
2898 						      tsc_timestamp));
2899 }
2900 
2901 /* returns true if host is using TSC based clocksource */
kvm_get_walltime_and_clockread(struct timespec64 * ts,u64 * tsc_timestamp)2902 static bool kvm_get_walltime_and_clockread(struct timespec64 *ts,
2903 					   u64 *tsc_timestamp)
2904 {
2905 	/* checked again under seqlock below */
2906 	if (!gtod_is_based_on_tsc(pvclock_gtod_data.clock.vclock_mode))
2907 		return false;
2908 
2909 	return gtod_is_based_on_tsc(do_realtime(ts, tsc_timestamp));
2910 }
2911 #endif
2912 
2913 /*
2914  *
2915  * Assuming a stable TSC across physical CPUS, and a stable TSC
2916  * across virtual CPUs, the following condition is possible.
2917  * Each numbered line represents an event visible to both
2918  * CPUs at the next numbered event.
2919  *
2920  * "timespecX" represents host monotonic time. "tscX" represents
2921  * RDTSC value.
2922  *
2923  * 		VCPU0 on CPU0		|	VCPU1 on CPU1
2924  *
2925  * 1.  read timespec0,tsc0
2926  * 2.					| timespec1 = timespec0 + N
2927  * 					| tsc1 = tsc0 + M
2928  * 3. transition to guest		| transition to guest
2929  * 4. ret0 = timespec0 + (rdtsc - tsc0) |
2930  * 5.				        | ret1 = timespec1 + (rdtsc - tsc1)
2931  * 				        | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
2932  *
2933  * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
2934  *
2935  * 	- ret0 < ret1
2936  *	- timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
2937  *		...
2938  *	- 0 < N - M => M < N
2939  *
2940  * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
2941  * always the case (the difference between two distinct xtime instances
2942  * might be smaller then the difference between corresponding TSC reads,
2943  * when updating guest vcpus pvclock areas).
2944  *
2945  * To avoid that problem, do not allow visibility of distinct
2946  * system_timestamp/tsc_timestamp values simultaneously: use a master
2947  * copy of host monotonic time values. Update that master copy
2948  * in lockstep.
2949  *
2950  * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
2951  *
2952  */
2953 
pvclock_update_vm_gtod_copy(struct kvm * kvm)2954 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
2955 {
2956 #ifdef CONFIG_X86_64
2957 	struct kvm_arch *ka = &kvm->arch;
2958 	int vclock_mode;
2959 	bool host_tsc_clocksource, vcpus_matched;
2960 
2961 	lockdep_assert_held(&kvm->arch.tsc_write_lock);
2962 	vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
2963 			atomic_read(&kvm->online_vcpus));
2964 
2965 	/*
2966 	 * If the host uses TSC clock, then passthrough TSC as stable
2967 	 * to the guest.
2968 	 */
2969 	host_tsc_clocksource = kvm_get_time_and_clockread(
2970 					&ka->master_kernel_ns,
2971 					&ka->master_cycle_now);
2972 
2973 	ka->use_master_clock = host_tsc_clocksource && vcpus_matched
2974 				&& !ka->backwards_tsc_observed
2975 				&& !ka->boot_vcpu_runs_old_kvmclock;
2976 
2977 	if (ka->use_master_clock)
2978 		atomic_set(&kvm_guest_has_master_clock, 1);
2979 
2980 	vclock_mode = pvclock_gtod_data.clock.vclock_mode;
2981 	trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
2982 					vcpus_matched);
2983 #endif
2984 }
2985 
kvm_make_mclock_inprogress_request(struct kvm * kvm)2986 static void kvm_make_mclock_inprogress_request(struct kvm *kvm)
2987 {
2988 	kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
2989 }
2990 
__kvm_start_pvclock_update(struct kvm * kvm)2991 static void __kvm_start_pvclock_update(struct kvm *kvm)
2992 {
2993 	raw_spin_lock_irq(&kvm->arch.tsc_write_lock);
2994 	write_seqcount_begin(&kvm->arch.pvclock_sc);
2995 }
2996 
kvm_start_pvclock_update(struct kvm * kvm)2997 static void kvm_start_pvclock_update(struct kvm *kvm)
2998 {
2999 	kvm_make_mclock_inprogress_request(kvm);
3000 
3001 	/* no guest entries from this point */
3002 	__kvm_start_pvclock_update(kvm);
3003 }
3004 
kvm_end_pvclock_update(struct kvm * kvm)3005 static void kvm_end_pvclock_update(struct kvm *kvm)
3006 {
3007 	struct kvm_arch *ka = &kvm->arch;
3008 	struct kvm_vcpu *vcpu;
3009 	unsigned long i;
3010 
3011 	write_seqcount_end(&ka->pvclock_sc);
3012 	raw_spin_unlock_irq(&ka->tsc_write_lock);
3013 	kvm_for_each_vcpu(i, vcpu, kvm)
3014 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3015 
3016 	/* guest entries allowed */
3017 	kvm_for_each_vcpu(i, vcpu, kvm)
3018 		kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
3019 }
3020 
kvm_update_masterclock(struct kvm * kvm)3021 static void kvm_update_masterclock(struct kvm *kvm)
3022 {
3023 	kvm_hv_request_tsc_page_update(kvm);
3024 	kvm_start_pvclock_update(kvm);
3025 	pvclock_update_vm_gtod_copy(kvm);
3026 	kvm_end_pvclock_update(kvm);
3027 }
3028 
3029 /*
3030  * Use the kernel's tsc_khz directly if the TSC is constant, otherwise use KVM's
3031  * per-CPU value (which may be zero if a CPU is going offline).  Note, tsc_khz
3032  * can change during boot even if the TSC is constant, as it's possible for KVM
3033  * to be loaded before TSC calibration completes.  Ideally, KVM would get a
3034  * notification when calibration completes, but practically speaking calibration
3035  * will complete before userspace is alive enough to create VMs.
3036  */
get_cpu_tsc_khz(void)3037 static unsigned long get_cpu_tsc_khz(void)
3038 {
3039 	if (static_cpu_has(X86_FEATURE_CONSTANT_TSC))
3040 		return tsc_khz;
3041 	else
3042 		return __this_cpu_read(cpu_tsc_khz);
3043 }
3044 
3045 /* Called within read_seqcount_begin/retry for kvm->pvclock_sc.  */
__get_kvmclock(struct kvm * kvm,struct kvm_clock_data * data)3046 static void __get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3047 {
3048 	struct kvm_arch *ka = &kvm->arch;
3049 	struct pvclock_vcpu_time_info hv_clock;
3050 
3051 	/* both __this_cpu_read() and rdtsc() should be on the same cpu */
3052 	get_cpu();
3053 
3054 	data->flags = 0;
3055 	if (ka->use_master_clock &&
3056 	    (static_cpu_has(X86_FEATURE_CONSTANT_TSC) || __this_cpu_read(cpu_tsc_khz))) {
3057 #ifdef CONFIG_X86_64
3058 		struct timespec64 ts;
3059 
3060 		if (kvm_get_walltime_and_clockread(&ts, &data->host_tsc)) {
3061 			data->realtime = ts.tv_nsec + NSEC_PER_SEC * ts.tv_sec;
3062 			data->flags |= KVM_CLOCK_REALTIME | KVM_CLOCK_HOST_TSC;
3063 		} else
3064 #endif
3065 		data->host_tsc = rdtsc();
3066 
3067 		data->flags |= KVM_CLOCK_TSC_STABLE;
3068 		hv_clock.tsc_timestamp = ka->master_cycle_now;
3069 		hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
3070 		kvm_get_time_scale(NSEC_PER_SEC, get_cpu_tsc_khz() * 1000LL,
3071 				   &hv_clock.tsc_shift,
3072 				   &hv_clock.tsc_to_system_mul);
3073 		data->clock = __pvclock_read_cycles(&hv_clock, data->host_tsc);
3074 	} else {
3075 		data->clock = get_kvmclock_base_ns() + ka->kvmclock_offset;
3076 	}
3077 
3078 	put_cpu();
3079 }
3080 
get_kvmclock(struct kvm * kvm,struct kvm_clock_data * data)3081 static void get_kvmclock(struct kvm *kvm, struct kvm_clock_data *data)
3082 {
3083 	struct kvm_arch *ka = &kvm->arch;
3084 	unsigned seq;
3085 
3086 	do {
3087 		seq = read_seqcount_begin(&ka->pvclock_sc);
3088 		__get_kvmclock(kvm, data);
3089 	} while (read_seqcount_retry(&ka->pvclock_sc, seq));
3090 }
3091 
get_kvmclock_ns(struct kvm * kvm)3092 u64 get_kvmclock_ns(struct kvm *kvm)
3093 {
3094 	struct kvm_clock_data data;
3095 
3096 	get_kvmclock(kvm, &data);
3097 	return data.clock;
3098 }
3099 
kvm_setup_guest_pvclock(struct kvm_vcpu * v,struct gfn_to_pfn_cache * gpc,unsigned int offset)3100 static void kvm_setup_guest_pvclock(struct kvm_vcpu *v,
3101 				    struct gfn_to_pfn_cache *gpc,
3102 				    unsigned int offset)
3103 {
3104 	struct kvm_vcpu_arch *vcpu = &v->arch;
3105 	struct pvclock_vcpu_time_info *guest_hv_clock;
3106 	unsigned long flags;
3107 
3108 	read_lock_irqsave(&gpc->lock, flags);
3109 	while (!kvm_gpc_check(gpc, offset + sizeof(*guest_hv_clock))) {
3110 		read_unlock_irqrestore(&gpc->lock, flags);
3111 
3112 		if (kvm_gpc_refresh(gpc, offset + sizeof(*guest_hv_clock)))
3113 			return;
3114 
3115 		read_lock_irqsave(&gpc->lock, flags);
3116 	}
3117 
3118 	guest_hv_clock = (void *)(gpc->khva + offset);
3119 
3120 	/*
3121 	 * This VCPU is paused, but it's legal for a guest to read another
3122 	 * VCPU's kvmclock, so we really have to follow the specification where
3123 	 * it says that version is odd if data is being modified, and even after
3124 	 * it is consistent.
3125 	 */
3126 
3127 	guest_hv_clock->version = vcpu->hv_clock.version = (guest_hv_clock->version + 1) | 1;
3128 	smp_wmb();
3129 
3130 	/* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
3131 	vcpu->hv_clock.flags |= (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
3132 
3133 	if (vcpu->pvclock_set_guest_stopped_request) {
3134 		vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
3135 		vcpu->pvclock_set_guest_stopped_request = false;
3136 	}
3137 
3138 	memcpy(guest_hv_clock, &vcpu->hv_clock, sizeof(*guest_hv_clock));
3139 	smp_wmb();
3140 
3141 	guest_hv_clock->version = ++vcpu->hv_clock.version;
3142 
3143 	mark_page_dirty_in_slot(v->kvm, gpc->memslot, gpc->gpa >> PAGE_SHIFT);
3144 	read_unlock_irqrestore(&gpc->lock, flags);
3145 
3146 	trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
3147 }
3148 
kvm_guest_time_update(struct kvm_vcpu * v)3149 static int kvm_guest_time_update(struct kvm_vcpu *v)
3150 {
3151 	unsigned long flags, tgt_tsc_khz;
3152 	unsigned seq;
3153 	struct kvm_vcpu_arch *vcpu = &v->arch;
3154 	struct kvm_arch *ka = &v->kvm->arch;
3155 	s64 kernel_ns;
3156 	u64 tsc_timestamp, host_tsc;
3157 	u8 pvclock_flags;
3158 	bool use_master_clock;
3159 
3160 	kernel_ns = 0;
3161 	host_tsc = 0;
3162 
3163 	/*
3164 	 * If the host uses TSC clock, then passthrough TSC as stable
3165 	 * to the guest.
3166 	 */
3167 	do {
3168 		seq = read_seqcount_begin(&ka->pvclock_sc);
3169 		use_master_clock = ka->use_master_clock;
3170 		if (use_master_clock) {
3171 			host_tsc = ka->master_cycle_now;
3172 			kernel_ns = ka->master_kernel_ns;
3173 		}
3174 	} while (read_seqcount_retry(&ka->pvclock_sc, seq));
3175 
3176 	/* Keep irq disabled to prevent changes to the clock */
3177 	local_irq_save(flags);
3178 	tgt_tsc_khz = get_cpu_tsc_khz();
3179 	if (unlikely(tgt_tsc_khz == 0)) {
3180 		local_irq_restore(flags);
3181 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3182 		return 1;
3183 	}
3184 	if (!use_master_clock) {
3185 		host_tsc = rdtsc();
3186 		kernel_ns = get_kvmclock_base_ns();
3187 	}
3188 
3189 	tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
3190 
3191 	/*
3192 	 * We may have to catch up the TSC to match elapsed wall clock
3193 	 * time for two reasons, even if kvmclock is used.
3194 	 *   1) CPU could have been running below the maximum TSC rate
3195 	 *   2) Broken TSC compensation resets the base at each VCPU
3196 	 *      entry to avoid unknown leaps of TSC even when running
3197 	 *      again on the same CPU.  This may cause apparent elapsed
3198 	 *      time to disappear, and the guest to stand still or run
3199 	 *	very slowly.
3200 	 */
3201 	if (vcpu->tsc_catchup) {
3202 		u64 tsc = compute_guest_tsc(v, kernel_ns);
3203 		if (tsc > tsc_timestamp) {
3204 			adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
3205 			tsc_timestamp = tsc;
3206 		}
3207 	}
3208 
3209 	local_irq_restore(flags);
3210 
3211 	/* With all the info we got, fill in the values */
3212 
3213 	if (kvm_caps.has_tsc_control)
3214 		tgt_tsc_khz = kvm_scale_tsc(tgt_tsc_khz,
3215 					    v->arch.l1_tsc_scaling_ratio);
3216 
3217 	if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3218 		kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
3219 				   &vcpu->hv_clock.tsc_shift,
3220 				   &vcpu->hv_clock.tsc_to_system_mul);
3221 		vcpu->hw_tsc_khz = tgt_tsc_khz;
3222 		kvm_xen_update_tsc_info(v);
3223 	}
3224 
3225 	vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
3226 	vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
3227 	vcpu->last_guest_tsc = tsc_timestamp;
3228 
3229 	/* If the host uses TSC clocksource, then it is stable */
3230 	pvclock_flags = 0;
3231 	if (use_master_clock)
3232 		pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
3233 
3234 	vcpu->hv_clock.flags = pvclock_flags;
3235 
3236 	if (vcpu->pv_time.active)
3237 		kvm_setup_guest_pvclock(v, &vcpu->pv_time, 0);
3238 	if (vcpu->xen.vcpu_info_cache.active)
3239 		kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_info_cache,
3240 					offsetof(struct compat_vcpu_info, time));
3241 	if (vcpu->xen.vcpu_time_info_cache.active)
3242 		kvm_setup_guest_pvclock(v, &vcpu->xen.vcpu_time_info_cache, 0);
3243 	kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
3244 	return 0;
3245 }
3246 
3247 /*
3248  * kvmclock updates which are isolated to a given vcpu, such as
3249  * vcpu->cpu migration, should not allow system_timestamp from
3250  * the rest of the vcpus to remain static. Otherwise ntp frequency
3251  * correction applies to one vcpu's system_timestamp but not
3252  * the others.
3253  *
3254  * So in those cases, request a kvmclock update for all vcpus.
3255  * We need to rate-limit these requests though, as they can
3256  * considerably slow guests that have a large number of vcpus.
3257  * The time for a remote vcpu to update its kvmclock is bound
3258  * by the delay we use to rate-limit the updates.
3259  */
3260 
3261 #define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
3262 
kvmclock_update_fn(struct work_struct * work)3263 static void kvmclock_update_fn(struct work_struct *work)
3264 {
3265 	unsigned long i;
3266 	struct delayed_work *dwork = to_delayed_work(work);
3267 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3268 					   kvmclock_update_work);
3269 	struct kvm *kvm = container_of(ka, struct kvm, arch);
3270 	struct kvm_vcpu *vcpu;
3271 
3272 	kvm_for_each_vcpu(i, vcpu, kvm) {
3273 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3274 		kvm_vcpu_kick(vcpu);
3275 	}
3276 }
3277 
kvm_gen_kvmclock_update(struct kvm_vcpu * v)3278 static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
3279 {
3280 	struct kvm *kvm = v->kvm;
3281 
3282 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
3283 	schedule_delayed_work(&kvm->arch.kvmclock_update_work,
3284 					KVMCLOCK_UPDATE_DELAY);
3285 }
3286 
3287 #define KVMCLOCK_SYNC_PERIOD (300 * HZ)
3288 
kvmclock_sync_fn(struct work_struct * work)3289 static void kvmclock_sync_fn(struct work_struct *work)
3290 {
3291 	struct delayed_work *dwork = to_delayed_work(work);
3292 	struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
3293 					   kvmclock_sync_work);
3294 	struct kvm *kvm = container_of(ka, struct kvm, arch);
3295 
3296 	if (!kvmclock_periodic_sync)
3297 		return;
3298 
3299 	schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
3300 	schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
3301 					KVMCLOCK_SYNC_PERIOD);
3302 }
3303 
3304 /* These helpers are safe iff @msr is known to be an MCx bank MSR. */
is_mci_control_msr(u32 msr)3305 static bool is_mci_control_msr(u32 msr)
3306 {
3307 	return (msr & 3) == 0;
3308 }
is_mci_status_msr(u32 msr)3309 static bool is_mci_status_msr(u32 msr)
3310 {
3311 	return (msr & 3) == 1;
3312 }
3313 
3314 /*
3315  * On AMD, HWCR[McStatusWrEn] controls whether setting MCi_STATUS results in #GP.
3316  */
can_set_mci_status(struct kvm_vcpu * vcpu)3317 static bool can_set_mci_status(struct kvm_vcpu *vcpu)
3318 {
3319 	/* McStatusWrEn enabled? */
3320 	if (guest_cpuid_is_amd_compatible(vcpu))
3321 		return !!(vcpu->arch.msr_hwcr & BIT_ULL(18));
3322 
3323 	return false;
3324 }
3325 
set_msr_mce(struct kvm_vcpu * vcpu,struct msr_data * msr_info)3326 static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3327 {
3328 	u64 mcg_cap = vcpu->arch.mcg_cap;
3329 	unsigned bank_num = mcg_cap & 0xff;
3330 	u32 msr = msr_info->index;
3331 	u64 data = msr_info->data;
3332 	u32 offset, last_msr;
3333 
3334 	switch (msr) {
3335 	case MSR_IA32_MCG_STATUS:
3336 		vcpu->arch.mcg_status = data;
3337 		break;
3338 	case MSR_IA32_MCG_CTL:
3339 		if (!(mcg_cap & MCG_CTL_P) &&
3340 		    (data || !msr_info->host_initiated))
3341 			return 1;
3342 		if (data != 0 && data != ~(u64)0)
3343 			return 1;
3344 		vcpu->arch.mcg_ctl = data;
3345 		break;
3346 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3347 		last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
3348 		if (msr > last_msr)
3349 			return 1;
3350 
3351 		if (!(mcg_cap & MCG_CMCI_P) && (data || !msr_info->host_initiated))
3352 			return 1;
3353 		/* An attempt to write a 1 to a reserved bit raises #GP */
3354 		if (data & ~(MCI_CTL2_CMCI_EN | MCI_CTL2_CMCI_THRESHOLD_MASK))
3355 			return 1;
3356 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
3357 					    last_msr + 1 - MSR_IA32_MC0_CTL2);
3358 		vcpu->arch.mci_ctl2_banks[offset] = data;
3359 		break;
3360 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3361 		last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
3362 		if (msr > last_msr)
3363 			return 1;
3364 
3365 		/*
3366 		 * Only 0 or all 1s can be written to IA32_MCi_CTL, all other
3367 		 * values are architecturally undefined.  But, some Linux
3368 		 * kernels clear bit 10 in bank 4 to workaround a BIOS/GART TLB
3369 		 * issue on AMD K8s, allow bit 10 to be clear when setting all
3370 		 * other bits in order to avoid an uncaught #GP in the guest.
3371 		 *
3372 		 * UNIXWARE clears bit 0 of MC1_CTL to ignore correctable,
3373 		 * single-bit ECC data errors.
3374 		 */
3375 		if (is_mci_control_msr(msr) &&
3376 		    data != 0 && (data | (1 << 10) | 1) != ~(u64)0)
3377 			return 1;
3378 
3379 		/*
3380 		 * All CPUs allow writing 0 to MCi_STATUS MSRs to clear the MSR.
3381 		 * AMD-based CPUs allow non-zero values, but if and only if
3382 		 * HWCR[McStatusWrEn] is set.
3383 		 */
3384 		if (!msr_info->host_initiated && is_mci_status_msr(msr) &&
3385 		    data != 0 && !can_set_mci_status(vcpu))
3386 			return 1;
3387 
3388 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
3389 					    last_msr + 1 - MSR_IA32_MC0_CTL);
3390 		vcpu->arch.mce_banks[offset] = data;
3391 		break;
3392 	default:
3393 		return 1;
3394 	}
3395 	return 0;
3396 }
3397 
kvm_pv_async_pf_enabled(struct kvm_vcpu * vcpu)3398 static inline bool kvm_pv_async_pf_enabled(struct kvm_vcpu *vcpu)
3399 {
3400 	u64 mask = KVM_ASYNC_PF_ENABLED | KVM_ASYNC_PF_DELIVERY_AS_INT;
3401 
3402 	return (vcpu->arch.apf.msr_en_val & mask) == mask;
3403 }
3404 
kvm_pv_enable_async_pf(struct kvm_vcpu * vcpu,u64 data)3405 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
3406 {
3407 	gpa_t gpa = data & ~0x3f;
3408 
3409 	/* Bits 4:5 are reserved, Should be zero */
3410 	if (data & 0x30)
3411 		return 1;
3412 
3413 	if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_VMEXIT) &&
3414 	    (data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT))
3415 		return 1;
3416 
3417 	if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT) &&
3418 	    (data & KVM_ASYNC_PF_DELIVERY_AS_INT))
3419 		return 1;
3420 
3421 	if (!lapic_in_kernel(vcpu))
3422 		return data ? 1 : 0;
3423 
3424 	vcpu->arch.apf.msr_en_val = data;
3425 
3426 	if (!kvm_pv_async_pf_enabled(vcpu)) {
3427 		kvm_clear_async_pf_completion_queue(vcpu);
3428 		kvm_async_pf_hash_reset(vcpu);
3429 		return 0;
3430 	}
3431 
3432 	if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
3433 					sizeof(u64)))
3434 		return 1;
3435 
3436 	vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
3437 	vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
3438 
3439 	kvm_async_pf_wakeup_all(vcpu);
3440 
3441 	return 0;
3442 }
3443 
kvm_pv_enable_async_pf_int(struct kvm_vcpu * vcpu,u64 data)3444 static int kvm_pv_enable_async_pf_int(struct kvm_vcpu *vcpu, u64 data)
3445 {
3446 	/* Bits 8-63 are reserved */
3447 	if (data >> 8)
3448 		return 1;
3449 
3450 	if (!lapic_in_kernel(vcpu))
3451 		return 1;
3452 
3453 	vcpu->arch.apf.msr_int_val = data;
3454 
3455 	vcpu->arch.apf.vec = data & KVM_ASYNC_PF_VEC_MASK;
3456 
3457 	return 0;
3458 }
3459 
kvmclock_reset(struct kvm_vcpu * vcpu)3460 static void kvmclock_reset(struct kvm_vcpu *vcpu)
3461 {
3462 	kvm_gpc_deactivate(&vcpu->arch.pv_time);
3463 	vcpu->arch.time = 0;
3464 }
3465 
kvm_vcpu_flush_tlb_all(struct kvm_vcpu * vcpu)3466 static void kvm_vcpu_flush_tlb_all(struct kvm_vcpu *vcpu)
3467 {
3468 	++vcpu->stat.tlb_flush;
3469 	static_call(kvm_x86_flush_tlb_all)(vcpu);
3470 
3471 	/* Flushing all ASIDs flushes the current ASID... */
3472 	kvm_clear_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
3473 }
3474 
kvm_vcpu_flush_tlb_guest(struct kvm_vcpu * vcpu)3475 static void kvm_vcpu_flush_tlb_guest(struct kvm_vcpu *vcpu)
3476 {
3477 	++vcpu->stat.tlb_flush;
3478 
3479 	if (!tdp_enabled) {
3480 		/*
3481 		 * A TLB flush on behalf of the guest is equivalent to
3482 		 * INVPCID(all), toggling CR4.PGE, etc., which requires
3483 		 * a forced sync of the shadow page tables.  Ensure all the
3484 		 * roots are synced and the guest TLB in hardware is clean.
3485 		 */
3486 		kvm_mmu_sync_roots(vcpu);
3487 		kvm_mmu_sync_prev_roots(vcpu);
3488 	}
3489 
3490 	static_call(kvm_x86_flush_tlb_guest)(vcpu);
3491 
3492 	/*
3493 	 * Flushing all "guest" TLB is always a superset of Hyper-V's fine
3494 	 * grained flushing.
3495 	 */
3496 	kvm_hv_vcpu_purge_flush_tlb(vcpu);
3497 }
3498 
3499 
kvm_vcpu_flush_tlb_current(struct kvm_vcpu * vcpu)3500 static inline void kvm_vcpu_flush_tlb_current(struct kvm_vcpu *vcpu)
3501 {
3502 	++vcpu->stat.tlb_flush;
3503 	static_call(kvm_x86_flush_tlb_current)(vcpu);
3504 }
3505 
3506 /*
3507  * Service "local" TLB flush requests, which are specific to the current MMU
3508  * context.  In addition to the generic event handling in vcpu_enter_guest(),
3509  * TLB flushes that are targeted at an MMU context also need to be serviced
3510  * prior before nested VM-Enter/VM-Exit.
3511  */
kvm_service_local_tlb_flush_requests(struct kvm_vcpu * vcpu)3512 void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu)
3513 {
3514 	if (kvm_check_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu))
3515 		kvm_vcpu_flush_tlb_current(vcpu);
3516 
3517 	if (kvm_check_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu))
3518 		kvm_vcpu_flush_tlb_guest(vcpu);
3519 }
3520 EXPORT_SYMBOL_GPL(kvm_service_local_tlb_flush_requests);
3521 
record_steal_time(struct kvm_vcpu * vcpu)3522 static void record_steal_time(struct kvm_vcpu *vcpu)
3523 {
3524 	struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
3525 	struct kvm_steal_time __user *st;
3526 	struct kvm_memslots *slots;
3527 	gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
3528 	u64 steal;
3529 	u32 version;
3530 
3531 	if (kvm_xen_msr_enabled(vcpu->kvm)) {
3532 		kvm_xen_runstate_set_running(vcpu);
3533 		return;
3534 	}
3535 
3536 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
3537 		return;
3538 
3539 	if (WARN_ON_ONCE(current->mm != vcpu->kvm->mm))
3540 		return;
3541 
3542 	slots = kvm_memslots(vcpu->kvm);
3543 
3544 	if (unlikely(slots->generation != ghc->generation ||
3545 		     gpa != ghc->gpa ||
3546 		     kvm_is_error_hva(ghc->hva) || !ghc->memslot)) {
3547 		/* We rely on the fact that it fits in a single page. */
3548 		BUILD_BUG_ON((sizeof(*st) - 1) & KVM_STEAL_VALID_BITS);
3549 
3550 		if (kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, gpa, sizeof(*st)) ||
3551 		    kvm_is_error_hva(ghc->hva) || !ghc->memslot)
3552 			return;
3553 	}
3554 
3555 	st = (struct kvm_steal_time __user *)ghc->hva;
3556 	/*
3557 	 * Doing a TLB flush here, on the guest's behalf, can avoid
3558 	 * expensive IPIs.
3559 	 */
3560 	if (guest_pv_has(vcpu, KVM_FEATURE_PV_TLB_FLUSH)) {
3561 		u8 st_preempted = 0;
3562 		int err = -EFAULT;
3563 
3564 		if (!user_access_begin(st, sizeof(*st)))
3565 			return;
3566 
3567 		asm volatile("1: xchgb %0, %2\n"
3568 			     "xor %1, %1\n"
3569 			     "2:\n"
3570 			     _ASM_EXTABLE_UA(1b, 2b)
3571 			     : "+q" (st_preempted),
3572 			       "+&r" (err),
3573 			       "+m" (st->preempted));
3574 		if (err)
3575 			goto out;
3576 
3577 		user_access_end();
3578 
3579 		vcpu->arch.st.preempted = 0;
3580 
3581 		trace_kvm_pv_tlb_flush(vcpu->vcpu_id,
3582 				       st_preempted & KVM_VCPU_FLUSH_TLB);
3583 		if (st_preempted & KVM_VCPU_FLUSH_TLB)
3584 			kvm_vcpu_flush_tlb_guest(vcpu);
3585 
3586 		if (!user_access_begin(st, sizeof(*st)))
3587 			goto dirty;
3588 	} else {
3589 		if (!user_access_begin(st, sizeof(*st)))
3590 			return;
3591 
3592 		unsafe_put_user(0, &st->preempted, out);
3593 		vcpu->arch.st.preempted = 0;
3594 	}
3595 
3596 	unsafe_get_user(version, &st->version, out);
3597 	if (version & 1)
3598 		version += 1;  /* first time write, random junk */
3599 
3600 	version += 1;
3601 	unsafe_put_user(version, &st->version, out);
3602 
3603 	smp_wmb();
3604 
3605 	unsafe_get_user(steal, &st->steal, out);
3606 	steal += current->sched_info.run_delay -
3607 		vcpu->arch.st.last_steal;
3608 	vcpu->arch.st.last_steal = current->sched_info.run_delay;
3609 	unsafe_put_user(steal, &st->steal, out);
3610 
3611 	version += 1;
3612 	unsafe_put_user(version, &st->version, out);
3613 
3614  out:
3615 	user_access_end();
3616  dirty:
3617 	mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
3618 }
3619 
kvm_is_msr_to_save(u32 msr_index)3620 static bool kvm_is_msr_to_save(u32 msr_index)
3621 {
3622 	unsigned int i;
3623 
3624 	for (i = 0; i < num_msrs_to_save; i++) {
3625 		if (msrs_to_save[i] == msr_index)
3626 			return true;
3627 	}
3628 
3629 	return false;
3630 }
3631 
kvm_set_msr_common(struct kvm_vcpu * vcpu,struct msr_data * msr_info)3632 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3633 {
3634 	u32 msr = msr_info->index;
3635 	u64 data = msr_info->data;
3636 
3637 	if (msr && msr == vcpu->kvm->arch.xen_hvm_config.msr)
3638 		return kvm_xen_write_hypercall_page(vcpu, data);
3639 
3640 	switch (msr) {
3641 	case MSR_AMD64_NB_CFG:
3642 	case MSR_IA32_UCODE_WRITE:
3643 	case MSR_VM_HSAVE_PA:
3644 	case MSR_AMD64_PATCH_LOADER:
3645 	case MSR_AMD64_BU_CFG2:
3646 	case MSR_AMD64_DC_CFG:
3647 	case MSR_AMD64_TW_CFG:
3648 	case MSR_F15H_EX_CFG:
3649 		break;
3650 
3651 	case MSR_IA32_UCODE_REV:
3652 		if (msr_info->host_initiated)
3653 			vcpu->arch.microcode_version = data;
3654 		break;
3655 	case MSR_IA32_ARCH_CAPABILITIES:
3656 		if (!msr_info->host_initiated)
3657 			return 1;
3658 		vcpu->arch.arch_capabilities = data;
3659 		break;
3660 	case MSR_IA32_PERF_CAPABILITIES:
3661 		if (!msr_info->host_initiated)
3662 			return 1;
3663 		if (data & ~kvm_caps.supported_perf_cap)
3664 			return 1;
3665 
3666 		/*
3667 		 * Note, this is not just a performance optimization!  KVM
3668 		 * disallows changing feature MSRs after the vCPU has run; PMU
3669 		 * refresh will bug the VM if called after the vCPU has run.
3670 		 */
3671 		if (vcpu->arch.perf_capabilities == data)
3672 			break;
3673 
3674 		vcpu->arch.perf_capabilities = data;
3675 		kvm_pmu_refresh(vcpu);
3676 		break;
3677 	case MSR_IA32_PRED_CMD:
3678 		if (!msr_info->host_initiated && !guest_has_pred_cmd_msr(vcpu))
3679 			return 1;
3680 
3681 		if (!boot_cpu_has(X86_FEATURE_IBPB) || (data & ~PRED_CMD_IBPB))
3682 			return 1;
3683 		if (!data)
3684 			break;
3685 
3686 		wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
3687 		break;
3688 	case MSR_IA32_FLUSH_CMD:
3689 		if (!msr_info->host_initiated &&
3690 		    !guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D))
3691 			return 1;
3692 
3693 		if (!boot_cpu_has(X86_FEATURE_FLUSH_L1D) || (data & ~L1D_FLUSH))
3694 			return 1;
3695 		if (!data)
3696 			break;
3697 
3698 		wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
3699 		break;
3700 	case MSR_EFER:
3701 		return set_efer(vcpu, msr_info);
3702 	case MSR_K7_HWCR:
3703 		data &= ~(u64)0x40;	/* ignore flush filter disable */
3704 		data &= ~(u64)0x100;	/* ignore ignne emulation enable */
3705 		data &= ~(u64)0x8;	/* ignore TLB cache disable */
3706 
3707 		/* Handle McStatusWrEn */
3708 		if (data == BIT_ULL(18)) {
3709 			vcpu->arch.msr_hwcr = data;
3710 		} else if (data != 0) {
3711 			kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3712 			return 1;
3713 		}
3714 		break;
3715 	case MSR_FAM10H_MMIO_CONF_BASE:
3716 		if (data != 0) {
3717 			kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3718 			return 1;
3719 		}
3720 		break;
3721 	case MSR_IA32_CR_PAT:
3722 		if (!kvm_pat_valid(data))
3723 			return 1;
3724 
3725 		vcpu->arch.pat = data;
3726 		break;
3727 	case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
3728 	case MSR_MTRRdefType:
3729 		return kvm_mtrr_set_msr(vcpu, msr, data);
3730 	case MSR_IA32_APICBASE:
3731 		return kvm_set_apic_base(vcpu, msr_info);
3732 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
3733 		return kvm_x2apic_msr_write(vcpu, msr, data);
3734 	case MSR_IA32_TSC_DEADLINE:
3735 		kvm_set_lapic_tscdeadline_msr(vcpu, data);
3736 		break;
3737 	case MSR_IA32_TSC_ADJUST:
3738 		if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
3739 			if (!msr_info->host_initiated) {
3740 				s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
3741 				adjust_tsc_offset_guest(vcpu, adj);
3742 				/* Before back to guest, tsc_timestamp must be adjusted
3743 				 * as well, otherwise guest's percpu pvclock time could jump.
3744 				 */
3745 				kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3746 			}
3747 			vcpu->arch.ia32_tsc_adjust_msr = data;
3748 		}
3749 		break;
3750 	case MSR_IA32_MISC_ENABLE: {
3751 		u64 old_val = vcpu->arch.ia32_misc_enable_msr;
3752 
3753 		if (!msr_info->host_initiated) {
3754 			/* RO bits */
3755 			if ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK)
3756 				return 1;
3757 
3758 			/* R bits, i.e. writes are ignored, but don't fault. */
3759 			data = data & ~MSR_IA32_MISC_ENABLE_EMON;
3760 			data |= old_val & MSR_IA32_MISC_ENABLE_EMON;
3761 		}
3762 
3763 		if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT) &&
3764 		    ((old_val ^ data)  & MSR_IA32_MISC_ENABLE_MWAIT)) {
3765 			if (!guest_cpuid_has(vcpu, X86_FEATURE_XMM3))
3766 				return 1;
3767 			vcpu->arch.ia32_misc_enable_msr = data;
3768 			kvm_update_cpuid_runtime(vcpu);
3769 		} else {
3770 			vcpu->arch.ia32_misc_enable_msr = data;
3771 		}
3772 		break;
3773 	}
3774 	case MSR_IA32_SMBASE:
3775 		if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
3776 			return 1;
3777 		vcpu->arch.smbase = data;
3778 		break;
3779 	case MSR_IA32_POWER_CTL:
3780 		vcpu->arch.msr_ia32_power_ctl = data;
3781 		break;
3782 	case MSR_IA32_TSC:
3783 		if (msr_info->host_initiated) {
3784 			kvm_synchronize_tsc(vcpu, data);
3785 		} else {
3786 			u64 adj = kvm_compute_l1_tsc_offset(vcpu, data) - vcpu->arch.l1_tsc_offset;
3787 			adjust_tsc_offset_guest(vcpu, adj);
3788 			vcpu->arch.ia32_tsc_adjust_msr += adj;
3789 		}
3790 		break;
3791 	case MSR_IA32_XSS:
3792 		if (!msr_info->host_initiated &&
3793 		    !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
3794 			return 1;
3795 		/*
3796 		 * KVM supports exposing PT to the guest, but does not support
3797 		 * IA32_XSS[bit 8]. Guests have to use RDMSR/WRMSR rather than
3798 		 * XSAVES/XRSTORS to save/restore PT MSRs.
3799 		 */
3800 		if (data & ~kvm_caps.supported_xss)
3801 			return 1;
3802 		vcpu->arch.ia32_xss = data;
3803 		kvm_update_cpuid_runtime(vcpu);
3804 		break;
3805 	case MSR_SMI_COUNT:
3806 		if (!msr_info->host_initiated)
3807 			return 1;
3808 		vcpu->arch.smi_count = data;
3809 		break;
3810 	case MSR_KVM_WALL_CLOCK_NEW:
3811 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3812 			return 1;
3813 
3814 		vcpu->kvm->arch.wall_clock = data;
3815 		kvm_write_wall_clock(vcpu->kvm, data, 0);
3816 		break;
3817 	case MSR_KVM_WALL_CLOCK:
3818 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3819 			return 1;
3820 
3821 		vcpu->kvm->arch.wall_clock = data;
3822 		kvm_write_wall_clock(vcpu->kvm, data, 0);
3823 		break;
3824 	case MSR_KVM_SYSTEM_TIME_NEW:
3825 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
3826 			return 1;
3827 
3828 		kvm_write_system_time(vcpu, data, false, msr_info->host_initiated);
3829 		break;
3830 	case MSR_KVM_SYSTEM_TIME:
3831 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
3832 			return 1;
3833 
3834 		kvm_write_system_time(vcpu, data, true,  msr_info->host_initiated);
3835 		break;
3836 	case MSR_KVM_ASYNC_PF_EN:
3837 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
3838 			return 1;
3839 
3840 		if (kvm_pv_enable_async_pf(vcpu, data))
3841 			return 1;
3842 		break;
3843 	case MSR_KVM_ASYNC_PF_INT:
3844 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3845 			return 1;
3846 
3847 		if (kvm_pv_enable_async_pf_int(vcpu, data))
3848 			return 1;
3849 		break;
3850 	case MSR_KVM_ASYNC_PF_ACK:
3851 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
3852 			return 1;
3853 		if (data & 0x1) {
3854 			vcpu->arch.apf.pageready_pending = false;
3855 			kvm_check_async_pf_completion(vcpu);
3856 		}
3857 		break;
3858 	case MSR_KVM_STEAL_TIME:
3859 		if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
3860 			return 1;
3861 
3862 		if (unlikely(!sched_info_on()))
3863 			return 1;
3864 
3865 		if (data & KVM_STEAL_RESERVED_MASK)
3866 			return 1;
3867 
3868 		vcpu->arch.st.msr_val = data;
3869 
3870 		if (!(data & KVM_MSR_ENABLED))
3871 			break;
3872 
3873 		kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
3874 
3875 		break;
3876 	case MSR_KVM_PV_EOI_EN:
3877 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
3878 			return 1;
3879 
3880 		if (kvm_lapic_set_pv_eoi(vcpu, data, sizeof(u8)))
3881 			return 1;
3882 		break;
3883 
3884 	case MSR_KVM_POLL_CONTROL:
3885 		if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
3886 			return 1;
3887 
3888 		/* only enable bit supported */
3889 		if (data & (-1ULL << 1))
3890 			return 1;
3891 
3892 		vcpu->arch.msr_kvm_poll_control = data;
3893 		break;
3894 
3895 	case MSR_IA32_MCG_CTL:
3896 	case MSR_IA32_MCG_STATUS:
3897 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
3898 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
3899 		return set_msr_mce(vcpu, msr_info);
3900 
3901 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
3902 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
3903 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
3904 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
3905 		if (kvm_pmu_is_valid_msr(vcpu, msr))
3906 			return kvm_pmu_set_msr(vcpu, msr_info);
3907 
3908 		if (data)
3909 			kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3910 		break;
3911 	case MSR_K7_CLK_CTL:
3912 		/*
3913 		 * Ignore all writes to this no longer documented MSR.
3914 		 * Writes are only relevant for old K7 processors,
3915 		 * all pre-dating SVM, but a recommended workaround from
3916 		 * AMD for these chips. It is possible to specify the
3917 		 * affected processor models on the command line, hence
3918 		 * the need to ignore the workaround.
3919 		 */
3920 		break;
3921 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
3922 	case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
3923 	case HV_X64_MSR_SYNDBG_OPTIONS:
3924 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3925 	case HV_X64_MSR_CRASH_CTL:
3926 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
3927 	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3928 	case HV_X64_MSR_TSC_EMULATION_CONTROL:
3929 	case HV_X64_MSR_TSC_EMULATION_STATUS:
3930 	case HV_X64_MSR_TSC_INVARIANT_CONTROL:
3931 		return kvm_hv_set_msr_common(vcpu, msr, data,
3932 					     msr_info->host_initiated);
3933 	case MSR_IA32_BBL_CR_CTL3:
3934 		/* Drop writes to this legacy MSR -- see rdmsr
3935 		 * counterpart for further detail.
3936 		 */
3937 		kvm_pr_unimpl_wrmsr(vcpu, msr, data);
3938 		break;
3939 	case MSR_AMD64_OSVW_ID_LENGTH:
3940 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3941 			return 1;
3942 		vcpu->arch.osvw.length = data;
3943 		break;
3944 	case MSR_AMD64_OSVW_STATUS:
3945 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
3946 			return 1;
3947 		vcpu->arch.osvw.status = data;
3948 		break;
3949 	case MSR_PLATFORM_INFO:
3950 		if (!msr_info->host_initiated ||
3951 		    (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
3952 		     cpuid_fault_enabled(vcpu)))
3953 			return 1;
3954 		vcpu->arch.msr_platform_info = data;
3955 		break;
3956 	case MSR_MISC_FEATURES_ENABLES:
3957 		if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
3958 		    (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
3959 		     !supports_cpuid_fault(vcpu)))
3960 			return 1;
3961 		vcpu->arch.msr_misc_features_enables = data;
3962 		break;
3963 #ifdef CONFIG_X86_64
3964 	case MSR_IA32_XFD:
3965 		if (!msr_info->host_initiated &&
3966 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3967 			return 1;
3968 
3969 		if (data & ~kvm_guest_supported_xfd(vcpu))
3970 			return 1;
3971 
3972 		fpu_update_guest_xfd(&vcpu->arch.guest_fpu, data);
3973 		break;
3974 	case MSR_IA32_XFD_ERR:
3975 		if (!msr_info->host_initiated &&
3976 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
3977 			return 1;
3978 
3979 		if (data & ~kvm_guest_supported_xfd(vcpu))
3980 			return 1;
3981 
3982 		vcpu->arch.guest_fpu.xfd_err = data;
3983 		break;
3984 #endif
3985 	default:
3986 		if (kvm_pmu_is_valid_msr(vcpu, msr))
3987 			return kvm_pmu_set_msr(vcpu, msr_info);
3988 
3989 		/*
3990 		 * Userspace is allowed to write '0' to MSRs that KVM reports
3991 		 * as to-be-saved, even if an MSRs isn't fully supported.
3992 		 */
3993 		if (msr_info->host_initiated && !data &&
3994 		    kvm_is_msr_to_save(msr))
3995 			break;
3996 
3997 		return KVM_MSR_RET_INVALID;
3998 	}
3999 	return 0;
4000 }
4001 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
4002 
get_msr_mce(struct kvm_vcpu * vcpu,u32 msr,u64 * pdata,bool host)4003 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata, bool host)
4004 {
4005 	u64 data;
4006 	u64 mcg_cap = vcpu->arch.mcg_cap;
4007 	unsigned bank_num = mcg_cap & 0xff;
4008 	u32 offset, last_msr;
4009 
4010 	switch (msr) {
4011 	case MSR_IA32_P5_MC_ADDR:
4012 	case MSR_IA32_P5_MC_TYPE:
4013 		data = 0;
4014 		break;
4015 	case MSR_IA32_MCG_CAP:
4016 		data = vcpu->arch.mcg_cap;
4017 		break;
4018 	case MSR_IA32_MCG_CTL:
4019 		if (!(mcg_cap & MCG_CTL_P) && !host)
4020 			return 1;
4021 		data = vcpu->arch.mcg_ctl;
4022 		break;
4023 	case MSR_IA32_MCG_STATUS:
4024 		data = vcpu->arch.mcg_status;
4025 		break;
4026 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4027 		last_msr = MSR_IA32_MCx_CTL2(bank_num) - 1;
4028 		if (msr > last_msr)
4029 			return 1;
4030 
4031 		if (!(mcg_cap & MCG_CMCI_P) && !host)
4032 			return 1;
4033 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL2,
4034 					    last_msr + 1 - MSR_IA32_MC0_CTL2);
4035 		data = vcpu->arch.mci_ctl2_banks[offset];
4036 		break;
4037 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4038 		last_msr = MSR_IA32_MCx_CTL(bank_num) - 1;
4039 		if (msr > last_msr)
4040 			return 1;
4041 
4042 		offset = array_index_nospec(msr - MSR_IA32_MC0_CTL,
4043 					    last_msr + 1 - MSR_IA32_MC0_CTL);
4044 		data = vcpu->arch.mce_banks[offset];
4045 		break;
4046 	default:
4047 		return 1;
4048 	}
4049 	*pdata = data;
4050 	return 0;
4051 }
4052 
kvm_get_msr_common(struct kvm_vcpu * vcpu,struct msr_data * msr_info)4053 int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
4054 {
4055 	switch (msr_info->index) {
4056 	case MSR_IA32_PLATFORM_ID:
4057 	case MSR_IA32_EBL_CR_POWERON:
4058 	case MSR_IA32_LASTBRANCHFROMIP:
4059 	case MSR_IA32_LASTBRANCHTOIP:
4060 	case MSR_IA32_LASTINTFROMIP:
4061 	case MSR_IA32_LASTINTTOIP:
4062 	case MSR_AMD64_SYSCFG:
4063 	case MSR_K8_TSEG_ADDR:
4064 	case MSR_K8_TSEG_MASK:
4065 	case MSR_VM_HSAVE_PA:
4066 	case MSR_K8_INT_PENDING_MSG:
4067 	case MSR_AMD64_NB_CFG:
4068 	case MSR_FAM10H_MMIO_CONF_BASE:
4069 	case MSR_AMD64_BU_CFG2:
4070 	case MSR_IA32_PERF_CTL:
4071 	case MSR_AMD64_DC_CFG:
4072 	case MSR_AMD64_TW_CFG:
4073 	case MSR_F15H_EX_CFG:
4074 	/*
4075 	 * Intel Sandy Bridge CPUs must support the RAPL (running average power
4076 	 * limit) MSRs. Just return 0, as we do not want to expose the host
4077 	 * data here. Do not conditionalize this on CPUID, as KVM does not do
4078 	 * so for existing CPU-specific MSRs.
4079 	 */
4080 	case MSR_RAPL_POWER_UNIT:
4081 	case MSR_PP0_ENERGY_STATUS:	/* Power plane 0 (core) */
4082 	case MSR_PP1_ENERGY_STATUS:	/* Power plane 1 (graphics uncore) */
4083 	case MSR_PKG_ENERGY_STATUS:	/* Total package */
4084 	case MSR_DRAM_ENERGY_STATUS:	/* DRAM controller */
4085 		msr_info->data = 0;
4086 		break;
4087 	case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
4088 	case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
4089 	case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
4090 	case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
4091 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4092 			return kvm_pmu_get_msr(vcpu, msr_info);
4093 		msr_info->data = 0;
4094 		break;
4095 	case MSR_IA32_UCODE_REV:
4096 		msr_info->data = vcpu->arch.microcode_version;
4097 		break;
4098 	case MSR_IA32_ARCH_CAPABILITIES:
4099 		if (!msr_info->host_initiated &&
4100 		    !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
4101 			return 1;
4102 		msr_info->data = vcpu->arch.arch_capabilities;
4103 		break;
4104 	case MSR_IA32_PERF_CAPABILITIES:
4105 		if (!msr_info->host_initiated &&
4106 		    !guest_cpuid_has(vcpu, X86_FEATURE_PDCM))
4107 			return 1;
4108 		msr_info->data = vcpu->arch.perf_capabilities;
4109 		break;
4110 	case MSR_IA32_POWER_CTL:
4111 		msr_info->data = vcpu->arch.msr_ia32_power_ctl;
4112 		break;
4113 	case MSR_IA32_TSC: {
4114 		/*
4115 		 * Intel SDM states that MSR_IA32_TSC read adds the TSC offset
4116 		 * even when not intercepted. AMD manual doesn't explicitly
4117 		 * state this but appears to behave the same.
4118 		 *
4119 		 * On userspace reads and writes, however, we unconditionally
4120 		 * return L1's TSC value to ensure backwards-compatible
4121 		 * behavior for migration.
4122 		 */
4123 		u64 offset, ratio;
4124 
4125 		if (msr_info->host_initiated) {
4126 			offset = vcpu->arch.l1_tsc_offset;
4127 			ratio = vcpu->arch.l1_tsc_scaling_ratio;
4128 		} else {
4129 			offset = vcpu->arch.tsc_offset;
4130 			ratio = vcpu->arch.tsc_scaling_ratio;
4131 		}
4132 
4133 		msr_info->data = kvm_scale_tsc(rdtsc(), ratio) + offset;
4134 		break;
4135 	}
4136 	case MSR_IA32_CR_PAT:
4137 		msr_info->data = vcpu->arch.pat;
4138 		break;
4139 	case MSR_MTRRcap:
4140 	case MTRRphysBase_MSR(0) ... MSR_MTRRfix4K_F8000:
4141 	case MSR_MTRRdefType:
4142 		return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
4143 	case 0xcd: /* fsb frequency */
4144 		msr_info->data = 3;
4145 		break;
4146 		/*
4147 		 * MSR_EBC_FREQUENCY_ID
4148 		 * Conservative value valid for even the basic CPU models.
4149 		 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
4150 		 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
4151 		 * and 266MHz for model 3, or 4. Set Core Clock
4152 		 * Frequency to System Bus Frequency Ratio to 1 (bits
4153 		 * 31:24) even though these are only valid for CPU
4154 		 * models > 2, however guests may end up dividing or
4155 		 * multiplying by zero otherwise.
4156 		 */
4157 	case MSR_EBC_FREQUENCY_ID:
4158 		msr_info->data = 1 << 24;
4159 		break;
4160 	case MSR_IA32_APICBASE:
4161 		msr_info->data = kvm_get_apic_base(vcpu);
4162 		break;
4163 	case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
4164 		return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
4165 	case MSR_IA32_TSC_DEADLINE:
4166 		msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
4167 		break;
4168 	case MSR_IA32_TSC_ADJUST:
4169 		msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
4170 		break;
4171 	case MSR_IA32_MISC_ENABLE:
4172 		msr_info->data = vcpu->arch.ia32_misc_enable_msr;
4173 		break;
4174 	case MSR_IA32_SMBASE:
4175 		if (!IS_ENABLED(CONFIG_KVM_SMM) || !msr_info->host_initiated)
4176 			return 1;
4177 		msr_info->data = vcpu->arch.smbase;
4178 		break;
4179 	case MSR_SMI_COUNT:
4180 		msr_info->data = vcpu->arch.smi_count;
4181 		break;
4182 	case MSR_IA32_PERF_STATUS:
4183 		/* TSC increment by tick */
4184 		msr_info->data = 1000ULL;
4185 		/* CPU multiplier */
4186 		msr_info->data |= (((uint64_t)4ULL) << 40);
4187 		break;
4188 	case MSR_EFER:
4189 		msr_info->data = vcpu->arch.efer;
4190 		break;
4191 	case MSR_KVM_WALL_CLOCK:
4192 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4193 			return 1;
4194 
4195 		msr_info->data = vcpu->kvm->arch.wall_clock;
4196 		break;
4197 	case MSR_KVM_WALL_CLOCK_NEW:
4198 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4199 			return 1;
4200 
4201 		msr_info->data = vcpu->kvm->arch.wall_clock;
4202 		break;
4203 	case MSR_KVM_SYSTEM_TIME:
4204 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE))
4205 			return 1;
4206 
4207 		msr_info->data = vcpu->arch.time;
4208 		break;
4209 	case MSR_KVM_SYSTEM_TIME_NEW:
4210 		if (!guest_pv_has(vcpu, KVM_FEATURE_CLOCKSOURCE2))
4211 			return 1;
4212 
4213 		msr_info->data = vcpu->arch.time;
4214 		break;
4215 	case MSR_KVM_ASYNC_PF_EN:
4216 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF))
4217 			return 1;
4218 
4219 		msr_info->data = vcpu->arch.apf.msr_en_val;
4220 		break;
4221 	case MSR_KVM_ASYNC_PF_INT:
4222 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4223 			return 1;
4224 
4225 		msr_info->data = vcpu->arch.apf.msr_int_val;
4226 		break;
4227 	case MSR_KVM_ASYNC_PF_ACK:
4228 		if (!guest_pv_has(vcpu, KVM_FEATURE_ASYNC_PF_INT))
4229 			return 1;
4230 
4231 		msr_info->data = 0;
4232 		break;
4233 	case MSR_KVM_STEAL_TIME:
4234 		if (!guest_pv_has(vcpu, KVM_FEATURE_STEAL_TIME))
4235 			return 1;
4236 
4237 		msr_info->data = vcpu->arch.st.msr_val;
4238 		break;
4239 	case MSR_KVM_PV_EOI_EN:
4240 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_EOI))
4241 			return 1;
4242 
4243 		msr_info->data = vcpu->arch.pv_eoi.msr_val;
4244 		break;
4245 	case MSR_KVM_POLL_CONTROL:
4246 		if (!guest_pv_has(vcpu, KVM_FEATURE_POLL_CONTROL))
4247 			return 1;
4248 
4249 		msr_info->data = vcpu->arch.msr_kvm_poll_control;
4250 		break;
4251 	case MSR_IA32_P5_MC_ADDR:
4252 	case MSR_IA32_P5_MC_TYPE:
4253 	case MSR_IA32_MCG_CAP:
4254 	case MSR_IA32_MCG_CTL:
4255 	case MSR_IA32_MCG_STATUS:
4256 	case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
4257 	case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
4258 		return get_msr_mce(vcpu, msr_info->index, &msr_info->data,
4259 				   msr_info->host_initiated);
4260 	case MSR_IA32_XSS:
4261 		if (!msr_info->host_initiated &&
4262 		    !guest_cpuid_has(vcpu, X86_FEATURE_XSAVES))
4263 			return 1;
4264 		msr_info->data = vcpu->arch.ia32_xss;
4265 		break;
4266 	case MSR_K7_CLK_CTL:
4267 		/*
4268 		 * Provide expected ramp-up count for K7. All other
4269 		 * are set to zero, indicating minimum divisors for
4270 		 * every field.
4271 		 *
4272 		 * This prevents guest kernels on AMD host with CPU
4273 		 * type 6, model 8 and higher from exploding due to
4274 		 * the rdmsr failing.
4275 		 */
4276 		msr_info->data = 0x20000000;
4277 		break;
4278 	case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
4279 	case HV_X64_MSR_SYNDBG_CONTROL ... HV_X64_MSR_SYNDBG_PENDING_BUFFER:
4280 	case HV_X64_MSR_SYNDBG_OPTIONS:
4281 	case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4282 	case HV_X64_MSR_CRASH_CTL:
4283 	case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
4284 	case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4285 	case HV_X64_MSR_TSC_EMULATION_CONTROL:
4286 	case HV_X64_MSR_TSC_EMULATION_STATUS:
4287 	case HV_X64_MSR_TSC_INVARIANT_CONTROL:
4288 		return kvm_hv_get_msr_common(vcpu,
4289 					     msr_info->index, &msr_info->data,
4290 					     msr_info->host_initiated);
4291 	case MSR_IA32_BBL_CR_CTL3:
4292 		/* This legacy MSR exists but isn't fully documented in current
4293 		 * silicon.  It is however accessed by winxp in very narrow
4294 		 * scenarios where it sets bit #19, itself documented as
4295 		 * a "reserved" bit.  Best effort attempt to source coherent
4296 		 * read data here should the balance of the register be
4297 		 * interpreted by the guest:
4298 		 *
4299 		 * L2 cache control register 3: 64GB range, 256KB size,
4300 		 * enabled, latency 0x1, configured
4301 		 */
4302 		msr_info->data = 0xbe702111;
4303 		break;
4304 	case MSR_AMD64_OSVW_ID_LENGTH:
4305 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4306 			return 1;
4307 		msr_info->data = vcpu->arch.osvw.length;
4308 		break;
4309 	case MSR_AMD64_OSVW_STATUS:
4310 		if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
4311 			return 1;
4312 		msr_info->data = vcpu->arch.osvw.status;
4313 		break;
4314 	case MSR_PLATFORM_INFO:
4315 		if (!msr_info->host_initiated &&
4316 		    !vcpu->kvm->arch.guest_can_read_msr_platform_info)
4317 			return 1;
4318 		msr_info->data = vcpu->arch.msr_platform_info;
4319 		break;
4320 	case MSR_MISC_FEATURES_ENABLES:
4321 		msr_info->data = vcpu->arch.msr_misc_features_enables;
4322 		break;
4323 	case MSR_K7_HWCR:
4324 		msr_info->data = vcpu->arch.msr_hwcr;
4325 		break;
4326 #ifdef CONFIG_X86_64
4327 	case MSR_IA32_XFD:
4328 		if (!msr_info->host_initiated &&
4329 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4330 			return 1;
4331 
4332 		msr_info->data = vcpu->arch.guest_fpu.fpstate->xfd;
4333 		break;
4334 	case MSR_IA32_XFD_ERR:
4335 		if (!msr_info->host_initiated &&
4336 		    !guest_cpuid_has(vcpu, X86_FEATURE_XFD))
4337 			return 1;
4338 
4339 		msr_info->data = vcpu->arch.guest_fpu.xfd_err;
4340 		break;
4341 #endif
4342 	default:
4343 		if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
4344 			return kvm_pmu_get_msr(vcpu, msr_info);
4345 
4346 		/*
4347 		 * Userspace is allowed to read MSRs that KVM reports as
4348 		 * to-be-saved, even if an MSR isn't fully supported.
4349 		 */
4350 		if (msr_info->host_initiated &&
4351 		    kvm_is_msr_to_save(msr_info->index)) {
4352 			msr_info->data = 0;
4353 			break;
4354 		}
4355 
4356 		return KVM_MSR_RET_INVALID;
4357 	}
4358 	return 0;
4359 }
4360 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
4361 
4362 /*
4363  * Read or write a bunch of msrs. All parameters are kernel addresses.
4364  *
4365  * @return number of msrs set successfully.
4366  */
__msr_io(struct kvm_vcpu * vcpu,struct kvm_msrs * msrs,struct kvm_msr_entry * entries,int (* do_msr)(struct kvm_vcpu * vcpu,unsigned index,u64 * data))4367 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
4368 		    struct kvm_msr_entry *entries,
4369 		    int (*do_msr)(struct kvm_vcpu *vcpu,
4370 				  unsigned index, u64 *data))
4371 {
4372 	int i;
4373 
4374 	for (i = 0; i < msrs->nmsrs; ++i)
4375 		if (do_msr(vcpu, entries[i].index, &entries[i].data))
4376 			break;
4377 
4378 	return i;
4379 }
4380 
4381 /*
4382  * Read or write a bunch of msrs. Parameters are user addresses.
4383  *
4384  * @return number of msrs set successfully.
4385  */
msr_io(struct kvm_vcpu * vcpu,struct kvm_msrs __user * user_msrs,int (* do_msr)(struct kvm_vcpu * vcpu,unsigned index,u64 * data),int writeback)4386 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
4387 		  int (*do_msr)(struct kvm_vcpu *vcpu,
4388 				unsigned index, u64 *data),
4389 		  int writeback)
4390 {
4391 	struct kvm_msrs msrs;
4392 	struct kvm_msr_entry *entries;
4393 	unsigned size;
4394 	int r;
4395 
4396 	r = -EFAULT;
4397 	if (copy_from_user(&msrs, user_msrs, sizeof(msrs)))
4398 		goto out;
4399 
4400 	r = -E2BIG;
4401 	if (msrs.nmsrs >= MAX_IO_MSRS)
4402 		goto out;
4403 
4404 	size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
4405 	entries = memdup_user(user_msrs->entries, size);
4406 	if (IS_ERR(entries)) {
4407 		r = PTR_ERR(entries);
4408 		goto out;
4409 	}
4410 
4411 	r = __msr_io(vcpu, &msrs, entries, do_msr);
4412 
4413 	if (writeback && copy_to_user(user_msrs->entries, entries, size))
4414 		r = -EFAULT;
4415 
4416 	kfree(entries);
4417 out:
4418 	return r;
4419 }
4420 
kvm_can_mwait_in_guest(void)4421 static inline bool kvm_can_mwait_in_guest(void)
4422 {
4423 	return boot_cpu_has(X86_FEATURE_MWAIT) &&
4424 		!boot_cpu_has_bug(X86_BUG_MONITOR) &&
4425 		boot_cpu_has(X86_FEATURE_ARAT);
4426 }
4427 
kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu * vcpu,struct kvm_cpuid2 __user * cpuid_arg)4428 static int kvm_ioctl_get_supported_hv_cpuid(struct kvm_vcpu *vcpu,
4429 					    struct kvm_cpuid2 __user *cpuid_arg)
4430 {
4431 	struct kvm_cpuid2 cpuid;
4432 	int r;
4433 
4434 	r = -EFAULT;
4435 	if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4436 		return r;
4437 
4438 	r = kvm_get_hv_cpuid(vcpu, &cpuid, cpuid_arg->entries);
4439 	if (r)
4440 		return r;
4441 
4442 	r = -EFAULT;
4443 	if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4444 		return r;
4445 
4446 	return 0;
4447 }
4448 
kvm_vm_ioctl_check_extension(struct kvm * kvm,long ext)4449 int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
4450 {
4451 	int r = 0;
4452 
4453 	switch (ext) {
4454 	case KVM_CAP_IRQCHIP:
4455 	case KVM_CAP_HLT:
4456 	case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
4457 	case KVM_CAP_SET_TSS_ADDR:
4458 	case KVM_CAP_EXT_CPUID:
4459 	case KVM_CAP_EXT_EMUL_CPUID:
4460 	case KVM_CAP_CLOCKSOURCE:
4461 	case KVM_CAP_PIT:
4462 	case KVM_CAP_NOP_IO_DELAY:
4463 	case KVM_CAP_MP_STATE:
4464 	case KVM_CAP_SYNC_MMU:
4465 	case KVM_CAP_USER_NMI:
4466 	case KVM_CAP_REINJECT_CONTROL:
4467 	case KVM_CAP_IRQ_INJECT_STATUS:
4468 	case KVM_CAP_IOEVENTFD:
4469 	case KVM_CAP_IOEVENTFD_NO_LENGTH:
4470 	case KVM_CAP_PIT2:
4471 	case KVM_CAP_PIT_STATE2:
4472 	case KVM_CAP_SET_IDENTITY_MAP_ADDR:
4473 	case KVM_CAP_VCPU_EVENTS:
4474 	case KVM_CAP_HYPERV:
4475 	case KVM_CAP_HYPERV_VAPIC:
4476 	case KVM_CAP_HYPERV_SPIN:
4477 	case KVM_CAP_HYPERV_SYNIC:
4478 	case KVM_CAP_HYPERV_SYNIC2:
4479 	case KVM_CAP_HYPERV_VP_INDEX:
4480 	case KVM_CAP_HYPERV_EVENTFD:
4481 	case KVM_CAP_HYPERV_TLBFLUSH:
4482 	case KVM_CAP_HYPERV_SEND_IPI:
4483 	case KVM_CAP_HYPERV_CPUID:
4484 	case KVM_CAP_HYPERV_ENFORCE_CPUID:
4485 	case KVM_CAP_SYS_HYPERV_CPUID:
4486 	case KVM_CAP_PCI_SEGMENT:
4487 	case KVM_CAP_DEBUGREGS:
4488 	case KVM_CAP_X86_ROBUST_SINGLESTEP:
4489 	case KVM_CAP_XSAVE:
4490 	case KVM_CAP_ASYNC_PF:
4491 	case KVM_CAP_ASYNC_PF_INT:
4492 	case KVM_CAP_GET_TSC_KHZ:
4493 	case KVM_CAP_KVMCLOCK_CTRL:
4494 	case KVM_CAP_READONLY_MEM:
4495 	case KVM_CAP_HYPERV_TIME:
4496 	case KVM_CAP_IOAPIC_POLARITY_IGNORED:
4497 	case KVM_CAP_TSC_DEADLINE_TIMER:
4498 	case KVM_CAP_DISABLE_QUIRKS:
4499 	case KVM_CAP_SET_BOOT_CPU_ID:
4500  	case KVM_CAP_SPLIT_IRQCHIP:
4501 	case KVM_CAP_IMMEDIATE_EXIT:
4502 	case KVM_CAP_PMU_EVENT_FILTER:
4503 	case KVM_CAP_PMU_EVENT_MASKED_EVENTS:
4504 	case KVM_CAP_GET_MSR_FEATURES:
4505 	case KVM_CAP_MSR_PLATFORM_INFO:
4506 	case KVM_CAP_EXCEPTION_PAYLOAD:
4507 	case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
4508 	case KVM_CAP_SET_GUEST_DEBUG:
4509 	case KVM_CAP_LAST_CPU:
4510 	case KVM_CAP_X86_USER_SPACE_MSR:
4511 	case KVM_CAP_X86_MSR_FILTER:
4512 	case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
4513 #ifdef CONFIG_X86_SGX_KVM
4514 	case KVM_CAP_SGX_ATTRIBUTE:
4515 #endif
4516 	case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
4517 	case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
4518 	case KVM_CAP_SREGS2:
4519 	case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
4520 	case KVM_CAP_VCPU_ATTRIBUTES:
4521 	case KVM_CAP_SYS_ATTRIBUTES:
4522 	case KVM_CAP_VAPIC:
4523 	case KVM_CAP_ENABLE_CAP:
4524 	case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
4525 	case KVM_CAP_IRQFD_RESAMPLE:
4526 		r = 1;
4527 		break;
4528 	case KVM_CAP_EXIT_HYPERCALL:
4529 		r = KVM_EXIT_HYPERCALL_VALID_MASK;
4530 		break;
4531 	case KVM_CAP_SET_GUEST_DEBUG2:
4532 		return KVM_GUESTDBG_VALID_MASK;
4533 #ifdef CONFIG_KVM_XEN
4534 	case KVM_CAP_XEN_HVM:
4535 		r = KVM_XEN_HVM_CONFIG_HYPERCALL_MSR |
4536 		    KVM_XEN_HVM_CONFIG_INTERCEPT_HCALL |
4537 		    KVM_XEN_HVM_CONFIG_SHARED_INFO |
4538 		    KVM_XEN_HVM_CONFIG_EVTCHN_2LEVEL |
4539 		    KVM_XEN_HVM_CONFIG_EVTCHN_SEND;
4540 		if (sched_info_on())
4541 			r |= KVM_XEN_HVM_CONFIG_RUNSTATE |
4542 			     KVM_XEN_HVM_CONFIG_RUNSTATE_UPDATE_FLAG;
4543 		break;
4544 #endif
4545 	case KVM_CAP_SYNC_REGS:
4546 		r = KVM_SYNC_X86_VALID_FIELDS;
4547 		break;
4548 	case KVM_CAP_ADJUST_CLOCK:
4549 		r = KVM_CLOCK_VALID_FLAGS;
4550 		break;
4551 	case KVM_CAP_X86_DISABLE_EXITS:
4552 		r = KVM_X86_DISABLE_EXITS_PAUSE;
4553 
4554 		if (!mitigate_smt_rsb) {
4555 			r |= KVM_X86_DISABLE_EXITS_HLT |
4556 			     KVM_X86_DISABLE_EXITS_CSTATE;
4557 
4558 			if (kvm_can_mwait_in_guest())
4559 				r |= KVM_X86_DISABLE_EXITS_MWAIT;
4560 		}
4561 		break;
4562 	case KVM_CAP_X86_SMM:
4563 		if (!IS_ENABLED(CONFIG_KVM_SMM))
4564 			break;
4565 
4566 		/* SMBASE is usually relocated above 1M on modern chipsets,
4567 		 * and SMM handlers might indeed rely on 4G segment limits,
4568 		 * so do not report SMM to be available if real mode is
4569 		 * emulated via vm86 mode.  Still, do not go to great lengths
4570 		 * to avoid userspace's usage of the feature, because it is a
4571 		 * fringe case that is not enabled except via specific settings
4572 		 * of the module parameters.
4573 		 */
4574 		r = static_call(kvm_x86_has_emulated_msr)(kvm, MSR_IA32_SMBASE);
4575 		break;
4576 	case KVM_CAP_NR_VCPUS:
4577 		r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
4578 		break;
4579 	case KVM_CAP_MAX_VCPUS:
4580 		r = KVM_MAX_VCPUS;
4581 		break;
4582 	case KVM_CAP_MAX_VCPU_ID:
4583 		r = KVM_MAX_VCPU_IDS;
4584 		break;
4585 	case KVM_CAP_PV_MMU:	/* obsolete */
4586 		r = 0;
4587 		break;
4588 	case KVM_CAP_MCE:
4589 		r = KVM_MAX_MCE_BANKS;
4590 		break;
4591 	case KVM_CAP_XCRS:
4592 		r = boot_cpu_has(X86_FEATURE_XSAVE);
4593 		break;
4594 	case KVM_CAP_TSC_CONTROL:
4595 	case KVM_CAP_VM_TSC_CONTROL:
4596 		r = kvm_caps.has_tsc_control;
4597 		break;
4598 	case KVM_CAP_X2APIC_API:
4599 		r = KVM_X2APIC_API_VALID_FLAGS;
4600 		break;
4601 	case KVM_CAP_NESTED_STATE:
4602 		r = kvm_x86_ops.nested_ops->get_state ?
4603 			kvm_x86_ops.nested_ops->get_state(NULL, NULL, 0) : 0;
4604 		break;
4605 	case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
4606 		r = kvm_x86_ops.enable_l2_tlb_flush != NULL;
4607 		break;
4608 	case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
4609 		r = kvm_x86_ops.nested_ops->enable_evmcs != NULL;
4610 		break;
4611 	case KVM_CAP_SMALLER_MAXPHYADDR:
4612 		r = (int) allow_smaller_maxphyaddr;
4613 		break;
4614 	case KVM_CAP_STEAL_TIME:
4615 		r = sched_info_on();
4616 		break;
4617 	case KVM_CAP_X86_BUS_LOCK_EXIT:
4618 		if (kvm_caps.has_bus_lock_exit)
4619 			r = KVM_BUS_LOCK_DETECTION_OFF |
4620 			    KVM_BUS_LOCK_DETECTION_EXIT;
4621 		else
4622 			r = 0;
4623 		break;
4624 	case KVM_CAP_XSAVE2: {
4625 		r = xstate_required_size(kvm_get_filtered_xcr0(), false);
4626 		if (r < sizeof(struct kvm_xsave))
4627 			r = sizeof(struct kvm_xsave);
4628 		break;
4629 	}
4630 	case KVM_CAP_PMU_CAPABILITY:
4631 		r = enable_pmu ? KVM_CAP_PMU_VALID_MASK : 0;
4632 		break;
4633 	case KVM_CAP_DISABLE_QUIRKS2:
4634 		r = KVM_X86_VALID_QUIRKS;
4635 		break;
4636 	case KVM_CAP_X86_NOTIFY_VMEXIT:
4637 		r = kvm_caps.has_notify_vmexit;
4638 		break;
4639 	default:
4640 		break;
4641 	}
4642 	return r;
4643 }
4644 
kvm_get_attr_addr(struct kvm_device_attr * attr)4645 static inline void __user *kvm_get_attr_addr(struct kvm_device_attr *attr)
4646 {
4647 	void __user *uaddr = (void __user*)(unsigned long)attr->addr;
4648 
4649 	if ((u64)(unsigned long)uaddr != attr->addr)
4650 		return ERR_PTR_USR(-EFAULT);
4651 	return uaddr;
4652 }
4653 
kvm_x86_dev_get_attr(struct kvm_device_attr * attr)4654 static int kvm_x86_dev_get_attr(struct kvm_device_attr *attr)
4655 {
4656 	u64 __user *uaddr = kvm_get_attr_addr(attr);
4657 
4658 	if (attr->group)
4659 		return -ENXIO;
4660 
4661 	if (IS_ERR(uaddr))
4662 		return PTR_ERR(uaddr);
4663 
4664 	switch (attr->attr) {
4665 	case KVM_X86_XCOMP_GUEST_SUPP:
4666 		if (put_user(kvm_caps.supported_xcr0, uaddr))
4667 			return -EFAULT;
4668 		return 0;
4669 	default:
4670 		return -ENXIO;
4671 	}
4672 }
4673 
kvm_x86_dev_has_attr(struct kvm_device_attr * attr)4674 static int kvm_x86_dev_has_attr(struct kvm_device_attr *attr)
4675 {
4676 	if (attr->group)
4677 		return -ENXIO;
4678 
4679 	switch (attr->attr) {
4680 	case KVM_X86_XCOMP_GUEST_SUPP:
4681 		return 0;
4682 	default:
4683 		return -ENXIO;
4684 	}
4685 }
4686 
kvm_arch_dev_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)4687 long kvm_arch_dev_ioctl(struct file *filp,
4688 			unsigned int ioctl, unsigned long arg)
4689 {
4690 	void __user *argp = (void __user *)arg;
4691 	long r;
4692 
4693 	switch (ioctl) {
4694 	case KVM_GET_MSR_INDEX_LIST: {
4695 		struct kvm_msr_list __user *user_msr_list = argp;
4696 		struct kvm_msr_list msr_list;
4697 		unsigned n;
4698 
4699 		r = -EFAULT;
4700 		if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4701 			goto out;
4702 		n = msr_list.nmsrs;
4703 		msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
4704 		if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4705 			goto out;
4706 		r = -E2BIG;
4707 		if (n < msr_list.nmsrs)
4708 			goto out;
4709 		r = -EFAULT;
4710 		if (copy_to_user(user_msr_list->indices, &msrs_to_save,
4711 				 num_msrs_to_save * sizeof(u32)))
4712 			goto out;
4713 		if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
4714 				 &emulated_msrs,
4715 				 num_emulated_msrs * sizeof(u32)))
4716 			goto out;
4717 		r = 0;
4718 		break;
4719 	}
4720 	case KVM_GET_SUPPORTED_CPUID:
4721 	case KVM_GET_EMULATED_CPUID: {
4722 		struct kvm_cpuid2 __user *cpuid_arg = argp;
4723 		struct kvm_cpuid2 cpuid;
4724 
4725 		r = -EFAULT;
4726 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
4727 			goto out;
4728 
4729 		r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
4730 					    ioctl);
4731 		if (r)
4732 			goto out;
4733 
4734 		r = -EFAULT;
4735 		if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
4736 			goto out;
4737 		r = 0;
4738 		break;
4739 	}
4740 	case KVM_X86_GET_MCE_CAP_SUPPORTED:
4741 		r = -EFAULT;
4742 		if (copy_to_user(argp, &kvm_caps.supported_mce_cap,
4743 				 sizeof(kvm_caps.supported_mce_cap)))
4744 			goto out;
4745 		r = 0;
4746 		break;
4747 	case KVM_GET_MSR_FEATURE_INDEX_LIST: {
4748 		struct kvm_msr_list __user *user_msr_list = argp;
4749 		struct kvm_msr_list msr_list;
4750 		unsigned int n;
4751 
4752 		r = -EFAULT;
4753 		if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
4754 			goto out;
4755 		n = msr_list.nmsrs;
4756 		msr_list.nmsrs = num_msr_based_features;
4757 		if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
4758 			goto out;
4759 		r = -E2BIG;
4760 		if (n < msr_list.nmsrs)
4761 			goto out;
4762 		r = -EFAULT;
4763 		if (copy_to_user(user_msr_list->indices, &msr_based_features,
4764 				 num_msr_based_features * sizeof(u32)))
4765 			goto out;
4766 		r = 0;
4767 		break;
4768 	}
4769 	case KVM_GET_MSRS:
4770 		r = msr_io(NULL, argp, do_get_msr_feature, 1);
4771 		break;
4772 	case KVM_GET_SUPPORTED_HV_CPUID:
4773 		r = kvm_ioctl_get_supported_hv_cpuid(NULL, argp);
4774 		break;
4775 	case KVM_GET_DEVICE_ATTR: {
4776 		struct kvm_device_attr attr;
4777 		r = -EFAULT;
4778 		if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4779 			break;
4780 		r = kvm_x86_dev_get_attr(&attr);
4781 		break;
4782 	}
4783 	case KVM_HAS_DEVICE_ATTR: {
4784 		struct kvm_device_attr attr;
4785 		r = -EFAULT;
4786 		if (copy_from_user(&attr, (void __user *)arg, sizeof(attr)))
4787 			break;
4788 		r = kvm_x86_dev_has_attr(&attr);
4789 		break;
4790 	}
4791 	default:
4792 		r = -EINVAL;
4793 		break;
4794 	}
4795 out:
4796 	return r;
4797 }
4798 
wbinvd_ipi(void * garbage)4799 static void wbinvd_ipi(void *garbage)
4800 {
4801 	wbinvd();
4802 }
4803 
need_emulate_wbinvd(struct kvm_vcpu * vcpu)4804 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
4805 {
4806 	return kvm_arch_has_noncoherent_dma(vcpu->kvm);
4807 }
4808 
kvm_arch_vcpu_load(struct kvm_vcpu * vcpu,int cpu)4809 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
4810 {
4811 	/* Address WBINVD may be executed by guest */
4812 	if (need_emulate_wbinvd(vcpu)) {
4813 		if (static_call(kvm_x86_has_wbinvd_exit)())
4814 			cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4815 		else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
4816 			smp_call_function_single(vcpu->cpu,
4817 					wbinvd_ipi, NULL, 1);
4818 	}
4819 
4820 	static_call(kvm_x86_vcpu_load)(vcpu, cpu);
4821 
4822 	/* Save host pkru register if supported */
4823 	vcpu->arch.host_pkru = read_pkru();
4824 
4825 	/* Apply any externally detected TSC adjustments (due to suspend) */
4826 	if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
4827 		adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
4828 		vcpu->arch.tsc_offset_adjustment = 0;
4829 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
4830 	}
4831 
4832 	if (unlikely(vcpu->cpu != cpu) || kvm_check_tsc_unstable()) {
4833 		s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4834 				rdtsc() - vcpu->arch.last_host_tsc;
4835 		if (tsc_delta < 0)
4836 			mark_tsc_unstable("KVM discovered backwards TSC");
4837 
4838 		if (kvm_check_tsc_unstable()) {
4839 			u64 offset = kvm_compute_l1_tsc_offset(vcpu,
4840 						vcpu->arch.last_guest_tsc);
4841 			kvm_vcpu_write_tsc_offset(vcpu, offset);
4842 			vcpu->arch.tsc_catchup = 1;
4843 		}
4844 
4845 		if (kvm_lapic_hv_timer_in_use(vcpu))
4846 			kvm_lapic_restart_hv_timer(vcpu);
4847 
4848 		/*
4849 		 * On a host with synchronized TSC, there is no need to update
4850 		 * kvmclock on vcpu->cpu migration
4851 		 */
4852 		if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
4853 			kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
4854 		if (vcpu->cpu != cpu)
4855 			kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
4856 		vcpu->cpu = cpu;
4857 	}
4858 
4859 	kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
4860 }
4861 
kvm_steal_time_set_preempted(struct kvm_vcpu * vcpu)4862 static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
4863 {
4864 	struct gfn_to_hva_cache *ghc = &vcpu->arch.st.cache;
4865 	struct kvm_steal_time __user *st;
4866 	struct kvm_memslots *slots;
4867 	static const u8 preempted = KVM_VCPU_PREEMPTED;
4868 	gpa_t gpa = vcpu->arch.st.msr_val & KVM_STEAL_VALID_BITS;
4869 
4870 	/*
4871 	 * The vCPU can be marked preempted if and only if the VM-Exit was on
4872 	 * an instruction boundary and will not trigger guest emulation of any
4873 	 * kind (see vcpu_run).  Vendor specific code controls (conservatively)
4874 	 * when this is true, for example allowing the vCPU to be marked
4875 	 * preempted if and only if the VM-Exit was due to a host interrupt.
4876 	 */
4877 	if (!vcpu->arch.at_instruction_boundary) {
4878 		vcpu->stat.preemption_other++;
4879 		return;
4880 	}
4881 
4882 	vcpu->stat.preemption_reported++;
4883 	if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
4884 		return;
4885 
4886 	if (vcpu->arch.st.preempted)
4887 		return;
4888 
4889 	/* This happens on process exit */
4890 	if (unlikely(current->mm != vcpu->kvm->mm))
4891 		return;
4892 
4893 	slots = kvm_memslots(vcpu->kvm);
4894 
4895 	if (unlikely(slots->generation != ghc->generation ||
4896 		     gpa != ghc->gpa ||
4897 		     kvm_is_error_hva(ghc->hva) || !ghc->memslot))
4898 		return;
4899 
4900 	st = (struct kvm_steal_time __user *)ghc->hva;
4901 	BUILD_BUG_ON(sizeof(st->preempted) != sizeof(preempted));
4902 
4903 	if (!copy_to_user_nofault(&st->preempted, &preempted, sizeof(preempted)))
4904 		vcpu->arch.st.preempted = KVM_VCPU_PREEMPTED;
4905 
4906 	mark_page_dirty_in_slot(vcpu->kvm, ghc->memslot, gpa_to_gfn(ghc->gpa));
4907 }
4908 
kvm_arch_vcpu_put(struct kvm_vcpu * vcpu)4909 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
4910 {
4911 	int idx;
4912 
4913 	if (vcpu->preempted) {
4914 		if (!vcpu->arch.guest_state_protected)
4915 			vcpu->arch.preempted_in_kernel = !static_call(kvm_x86_get_cpl)(vcpu);
4916 
4917 		/*
4918 		 * Take the srcu lock as memslots will be accessed to check the gfn
4919 		 * cache generation against the memslots generation.
4920 		 */
4921 		idx = srcu_read_lock(&vcpu->kvm->srcu);
4922 		if (kvm_xen_msr_enabled(vcpu->kvm))
4923 			kvm_xen_runstate_set_preempted(vcpu);
4924 		else
4925 			kvm_steal_time_set_preempted(vcpu);
4926 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
4927 	}
4928 
4929 	static_call(kvm_x86_vcpu_put)(vcpu);
4930 	vcpu->arch.last_host_tsc = rdtsc();
4931 }
4932 
kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu * vcpu,struct kvm_lapic_state * s)4933 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
4934 				    struct kvm_lapic_state *s)
4935 {
4936 	static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
4937 
4938 	return kvm_apic_get_state(vcpu, s);
4939 }
4940 
kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu * vcpu,struct kvm_lapic_state * s)4941 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
4942 				    struct kvm_lapic_state *s)
4943 {
4944 	int r;
4945 
4946 	r = kvm_apic_set_state(vcpu, s);
4947 	if (r)
4948 		return r;
4949 	update_cr8_intercept(vcpu);
4950 
4951 	return 0;
4952 }
4953 
kvm_cpu_accept_dm_intr(struct kvm_vcpu * vcpu)4954 static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
4955 {
4956 	/*
4957 	 * We can accept userspace's request for interrupt injection
4958 	 * as long as we have a place to store the interrupt number.
4959 	 * The actual injection will happen when the CPU is able to
4960 	 * deliver the interrupt.
4961 	 */
4962 	if (kvm_cpu_has_extint(vcpu))
4963 		return false;
4964 
4965 	/* Acknowledging ExtINT does not happen if LINT0 is masked.  */
4966 	return (!lapic_in_kernel(vcpu) ||
4967 		kvm_apic_accept_pic_intr(vcpu));
4968 }
4969 
kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu * vcpu)4970 static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
4971 {
4972 	/*
4973 	 * Do not cause an interrupt window exit if an exception
4974 	 * is pending or an event needs reinjection; userspace
4975 	 * might want to inject the interrupt manually using KVM_SET_REGS
4976 	 * or KVM_SET_SREGS.  For that to work, we must be at an
4977 	 * instruction boundary and with no events half-injected.
4978 	 */
4979 	return (kvm_arch_interrupt_allowed(vcpu) &&
4980 		kvm_cpu_accept_dm_intr(vcpu) &&
4981 		!kvm_event_needs_reinjection(vcpu) &&
4982 		!kvm_is_exception_pending(vcpu));
4983 }
4984 
kvm_vcpu_ioctl_interrupt(struct kvm_vcpu * vcpu,struct kvm_interrupt * irq)4985 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
4986 				    struct kvm_interrupt *irq)
4987 {
4988 	if (irq->irq >= KVM_NR_INTERRUPTS)
4989 		return -EINVAL;
4990 
4991 	if (!irqchip_in_kernel(vcpu->kvm)) {
4992 		kvm_queue_interrupt(vcpu, irq->irq, false);
4993 		kvm_make_request(KVM_REQ_EVENT, vcpu);
4994 		return 0;
4995 	}
4996 
4997 	/*
4998 	 * With in-kernel LAPIC, we only use this to inject EXTINT, so
4999 	 * fail for in-kernel 8259.
5000 	 */
5001 	if (pic_in_kernel(vcpu->kvm))
5002 		return -ENXIO;
5003 
5004 	if (vcpu->arch.pending_external_vector != -1)
5005 		return -EEXIST;
5006 
5007 	vcpu->arch.pending_external_vector = irq->irq;
5008 	kvm_make_request(KVM_REQ_EVENT, vcpu);
5009 	return 0;
5010 }
5011 
kvm_vcpu_ioctl_nmi(struct kvm_vcpu * vcpu)5012 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
5013 {
5014 	kvm_inject_nmi(vcpu);
5015 
5016 	return 0;
5017 }
5018 
vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu * vcpu,struct kvm_tpr_access_ctl * tac)5019 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
5020 					   struct kvm_tpr_access_ctl *tac)
5021 {
5022 	if (tac->flags)
5023 		return -EINVAL;
5024 	vcpu->arch.tpr_access_reporting = !!tac->enabled;
5025 	return 0;
5026 }
5027 
kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu * vcpu,u64 mcg_cap)5028 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
5029 					u64 mcg_cap)
5030 {
5031 	int r;
5032 	unsigned bank_num = mcg_cap & 0xff, bank;
5033 
5034 	r = -EINVAL;
5035 	if (!bank_num || bank_num > KVM_MAX_MCE_BANKS)
5036 		goto out;
5037 	if (mcg_cap & ~(kvm_caps.supported_mce_cap | 0xff | 0xff0000))
5038 		goto out;
5039 	r = 0;
5040 	vcpu->arch.mcg_cap = mcg_cap;
5041 	/* Init IA32_MCG_CTL to all 1s */
5042 	if (mcg_cap & MCG_CTL_P)
5043 		vcpu->arch.mcg_ctl = ~(u64)0;
5044 	/* Init IA32_MCi_CTL to all 1s, IA32_MCi_CTL2 to all 0s */
5045 	for (bank = 0; bank < bank_num; bank++) {
5046 		vcpu->arch.mce_banks[bank*4] = ~(u64)0;
5047 		if (mcg_cap & MCG_CMCI_P)
5048 			vcpu->arch.mci_ctl2_banks[bank] = 0;
5049 	}
5050 
5051 	kvm_apic_after_set_mcg_cap(vcpu);
5052 
5053 	static_call(kvm_x86_setup_mce)(vcpu);
5054 out:
5055 	return r;
5056 }
5057 
5058 /*
5059  * Validate this is an UCNA (uncorrectable no action) error by checking the
5060  * MCG_STATUS and MCi_STATUS registers:
5061  * - none of the bits for Machine Check Exceptions are set
5062  * - both the VAL (valid) and UC (uncorrectable) bits are set
5063  * MCI_STATUS_PCC - Processor Context Corrupted
5064  * MCI_STATUS_S - Signaled as a Machine Check Exception
5065  * MCI_STATUS_AR - Software recoverable Action Required
5066  */
is_ucna(struct kvm_x86_mce * mce)5067 static bool is_ucna(struct kvm_x86_mce *mce)
5068 {
5069 	return	!mce->mcg_status &&
5070 		!(mce->status & (MCI_STATUS_PCC | MCI_STATUS_S | MCI_STATUS_AR)) &&
5071 		(mce->status & MCI_STATUS_VAL) &&
5072 		(mce->status & MCI_STATUS_UC);
5073 }
5074 
kvm_vcpu_x86_set_ucna(struct kvm_vcpu * vcpu,struct kvm_x86_mce * mce,u64 * banks)5075 static int kvm_vcpu_x86_set_ucna(struct kvm_vcpu *vcpu, struct kvm_x86_mce *mce, u64* banks)
5076 {
5077 	u64 mcg_cap = vcpu->arch.mcg_cap;
5078 
5079 	banks[1] = mce->status;
5080 	banks[2] = mce->addr;
5081 	banks[3] = mce->misc;
5082 	vcpu->arch.mcg_status = mce->mcg_status;
5083 
5084 	if (!(mcg_cap & MCG_CMCI_P) ||
5085 	    !(vcpu->arch.mci_ctl2_banks[mce->bank] & MCI_CTL2_CMCI_EN))
5086 		return 0;
5087 
5088 	if (lapic_in_kernel(vcpu))
5089 		kvm_apic_local_deliver(vcpu->arch.apic, APIC_LVTCMCI);
5090 
5091 	return 0;
5092 }
5093 
kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu * vcpu,struct kvm_x86_mce * mce)5094 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
5095 				      struct kvm_x86_mce *mce)
5096 {
5097 	u64 mcg_cap = vcpu->arch.mcg_cap;
5098 	unsigned bank_num = mcg_cap & 0xff;
5099 	u64 *banks = vcpu->arch.mce_banks;
5100 
5101 	if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
5102 		return -EINVAL;
5103 
5104 	banks += array_index_nospec(4 * mce->bank, 4 * bank_num);
5105 
5106 	if (is_ucna(mce))
5107 		return kvm_vcpu_x86_set_ucna(vcpu, mce, banks);
5108 
5109 	/*
5110 	 * if IA32_MCG_CTL is not all 1s, the uncorrected error
5111 	 * reporting is disabled
5112 	 */
5113 	if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
5114 	    vcpu->arch.mcg_ctl != ~(u64)0)
5115 		return 0;
5116 	/*
5117 	 * if IA32_MCi_CTL is not all 1s, the uncorrected error
5118 	 * reporting is disabled for the bank
5119 	 */
5120 	if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
5121 		return 0;
5122 	if (mce->status & MCI_STATUS_UC) {
5123 		if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
5124 		    !kvm_is_cr4_bit_set(vcpu, X86_CR4_MCE)) {
5125 			kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5126 			return 0;
5127 		}
5128 		if (banks[1] & MCI_STATUS_VAL)
5129 			mce->status |= MCI_STATUS_OVER;
5130 		banks[2] = mce->addr;
5131 		banks[3] = mce->misc;
5132 		vcpu->arch.mcg_status = mce->mcg_status;
5133 		banks[1] = mce->status;
5134 		kvm_queue_exception(vcpu, MC_VECTOR);
5135 	} else if (!(banks[1] & MCI_STATUS_VAL)
5136 		   || !(banks[1] & MCI_STATUS_UC)) {
5137 		if (banks[1] & MCI_STATUS_VAL)
5138 			mce->status |= MCI_STATUS_OVER;
5139 		banks[2] = mce->addr;
5140 		banks[3] = mce->misc;
5141 		banks[1] = mce->status;
5142 	} else
5143 		banks[1] |= MCI_STATUS_OVER;
5144 	return 0;
5145 }
5146 
kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu * vcpu,struct kvm_vcpu_events * events)5147 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
5148 					       struct kvm_vcpu_events *events)
5149 {
5150 	struct kvm_queued_exception *ex;
5151 
5152 	process_nmi(vcpu);
5153 
5154 #ifdef CONFIG_KVM_SMM
5155 	if (kvm_check_request(KVM_REQ_SMI, vcpu))
5156 		process_smi(vcpu);
5157 #endif
5158 
5159 	/*
5160 	 * KVM's ABI only allows for one exception to be migrated.  Luckily,
5161 	 * the only time there can be two queued exceptions is if there's a
5162 	 * non-exiting _injected_ exception, and a pending exiting exception.
5163 	 * In that case, ignore the VM-Exiting exception as it's an extension
5164 	 * of the injected exception.
5165 	 */
5166 	if (vcpu->arch.exception_vmexit.pending &&
5167 	    !vcpu->arch.exception.pending &&
5168 	    !vcpu->arch.exception.injected)
5169 		ex = &vcpu->arch.exception_vmexit;
5170 	else
5171 		ex = &vcpu->arch.exception;
5172 
5173 	/*
5174 	 * In guest mode, payload delivery should be deferred if the exception
5175 	 * will be intercepted by L1, e.g. KVM should not modifying CR2 if L1
5176 	 * intercepts #PF, ditto for DR6 and #DBs.  If the per-VM capability,
5177 	 * KVM_CAP_EXCEPTION_PAYLOAD, is not set, userspace may or may not
5178 	 * propagate the payload and so it cannot be safely deferred.  Deliver
5179 	 * the payload if the capability hasn't been requested.
5180 	 */
5181 	if (!vcpu->kvm->arch.exception_payload_enabled &&
5182 	    ex->pending && ex->has_payload)
5183 		kvm_deliver_exception_payload(vcpu, ex);
5184 
5185 	memset(events, 0, sizeof(*events));
5186 
5187 	/*
5188 	 * The API doesn't provide the instruction length for software
5189 	 * exceptions, so don't report them. As long as the guest RIP
5190 	 * isn't advanced, we should expect to encounter the exception
5191 	 * again.
5192 	 */
5193 	if (!kvm_exception_is_soft(ex->vector)) {
5194 		events->exception.injected = ex->injected;
5195 		events->exception.pending = ex->pending;
5196 		/*
5197 		 * For ABI compatibility, deliberately conflate
5198 		 * pending and injected exceptions when
5199 		 * KVM_CAP_EXCEPTION_PAYLOAD isn't enabled.
5200 		 */
5201 		if (!vcpu->kvm->arch.exception_payload_enabled)
5202 			events->exception.injected |= ex->pending;
5203 	}
5204 	events->exception.nr = ex->vector;
5205 	events->exception.has_error_code = ex->has_error_code;
5206 	events->exception.error_code = ex->error_code;
5207 	events->exception_has_payload = ex->has_payload;
5208 	events->exception_payload = ex->payload;
5209 
5210 	events->interrupt.injected =
5211 		vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft;
5212 	events->interrupt.nr = vcpu->arch.interrupt.nr;
5213 	events->interrupt.shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
5214 
5215 	events->nmi.injected = vcpu->arch.nmi_injected;
5216 	events->nmi.pending = kvm_get_nr_pending_nmis(vcpu);
5217 	events->nmi.masked = static_call(kvm_x86_get_nmi_mask)(vcpu);
5218 
5219 	/* events->sipi_vector is never valid when reporting to user space */
5220 
5221 #ifdef CONFIG_KVM_SMM
5222 	events->smi.smm = is_smm(vcpu);
5223 	events->smi.pending = vcpu->arch.smi_pending;
5224 	events->smi.smm_inside_nmi =
5225 		!!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
5226 #endif
5227 	events->smi.latched_init = kvm_lapic_latched_init(vcpu);
5228 
5229 	events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
5230 			 | KVM_VCPUEVENT_VALID_SHADOW
5231 			 | KVM_VCPUEVENT_VALID_SMM);
5232 	if (vcpu->kvm->arch.exception_payload_enabled)
5233 		events->flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
5234 	if (vcpu->kvm->arch.triple_fault_event) {
5235 		events->triple_fault.pending = kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5236 		events->flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
5237 	}
5238 }
5239 
kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu * vcpu,struct kvm_vcpu_events * events)5240 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
5241 					      struct kvm_vcpu_events *events)
5242 {
5243 	if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
5244 			      | KVM_VCPUEVENT_VALID_SIPI_VECTOR
5245 			      | KVM_VCPUEVENT_VALID_SHADOW
5246 			      | KVM_VCPUEVENT_VALID_SMM
5247 			      | KVM_VCPUEVENT_VALID_PAYLOAD
5248 			      | KVM_VCPUEVENT_VALID_TRIPLE_FAULT))
5249 		return -EINVAL;
5250 
5251 	if (events->flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
5252 		if (!vcpu->kvm->arch.exception_payload_enabled)
5253 			return -EINVAL;
5254 		if (events->exception.pending)
5255 			events->exception.injected = 0;
5256 		else
5257 			events->exception_has_payload = 0;
5258 	} else {
5259 		events->exception.pending = 0;
5260 		events->exception_has_payload = 0;
5261 	}
5262 
5263 	if ((events->exception.injected || events->exception.pending) &&
5264 	    (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR))
5265 		return -EINVAL;
5266 
5267 	/* INITs are latched while in SMM */
5268 	if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
5269 	    (events->smi.smm || events->smi.pending) &&
5270 	    vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
5271 		return -EINVAL;
5272 
5273 	process_nmi(vcpu);
5274 
5275 	/*
5276 	 * Flag that userspace is stuffing an exception, the next KVM_RUN will
5277 	 * morph the exception to a VM-Exit if appropriate.  Do this only for
5278 	 * pending exceptions, already-injected exceptions are not subject to
5279 	 * intercpetion.  Note, userspace that conflates pending and injected
5280 	 * is hosed, and will incorrectly convert an injected exception into a
5281 	 * pending exception, which in turn may cause a spurious VM-Exit.
5282 	 */
5283 	vcpu->arch.exception_from_userspace = events->exception.pending;
5284 
5285 	vcpu->arch.exception_vmexit.pending = false;
5286 
5287 	vcpu->arch.exception.injected = events->exception.injected;
5288 	vcpu->arch.exception.pending = events->exception.pending;
5289 	vcpu->arch.exception.vector = events->exception.nr;
5290 	vcpu->arch.exception.has_error_code = events->exception.has_error_code;
5291 	vcpu->arch.exception.error_code = events->exception.error_code;
5292 	vcpu->arch.exception.has_payload = events->exception_has_payload;
5293 	vcpu->arch.exception.payload = events->exception_payload;
5294 
5295 	vcpu->arch.interrupt.injected = events->interrupt.injected;
5296 	vcpu->arch.interrupt.nr = events->interrupt.nr;
5297 	vcpu->arch.interrupt.soft = events->interrupt.soft;
5298 	if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
5299 		static_call(kvm_x86_set_interrupt_shadow)(vcpu,
5300 						events->interrupt.shadow);
5301 
5302 	vcpu->arch.nmi_injected = events->nmi.injected;
5303 	if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING) {
5304 		vcpu->arch.nmi_pending = 0;
5305 		atomic_set(&vcpu->arch.nmi_queued, events->nmi.pending);
5306 		if (events->nmi.pending)
5307 			kvm_make_request(KVM_REQ_NMI, vcpu);
5308 	}
5309 	static_call(kvm_x86_set_nmi_mask)(vcpu, events->nmi.masked);
5310 
5311 	if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
5312 	    lapic_in_kernel(vcpu))
5313 		vcpu->arch.apic->sipi_vector = events->sipi_vector;
5314 
5315 	if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
5316 #ifdef CONFIG_KVM_SMM
5317 		if (!!(vcpu->arch.hflags & HF_SMM_MASK) != events->smi.smm) {
5318 			kvm_leave_nested(vcpu);
5319 			kvm_smm_changed(vcpu, events->smi.smm);
5320 		}
5321 
5322 		vcpu->arch.smi_pending = events->smi.pending;
5323 
5324 		if (events->smi.smm) {
5325 			if (events->smi.smm_inside_nmi)
5326 				vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
5327 			else
5328 				vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
5329 		}
5330 
5331 #else
5332 		if (events->smi.smm || events->smi.pending ||
5333 		    events->smi.smm_inside_nmi)
5334 			return -EINVAL;
5335 #endif
5336 
5337 		if (lapic_in_kernel(vcpu)) {
5338 			if (events->smi.latched_init)
5339 				set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5340 			else
5341 				clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
5342 		}
5343 	}
5344 
5345 	if (events->flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
5346 		if (!vcpu->kvm->arch.triple_fault_event)
5347 			return -EINVAL;
5348 		if (events->triple_fault.pending)
5349 			kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5350 		else
5351 			kvm_clear_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5352 	}
5353 
5354 	kvm_make_request(KVM_REQ_EVENT, vcpu);
5355 
5356 	return 0;
5357 }
5358 
kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu * vcpu,struct kvm_debugregs * dbgregs)5359 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
5360 					     struct kvm_debugregs *dbgregs)
5361 {
5362 	unsigned long val;
5363 
5364 	memset(dbgregs, 0, sizeof(*dbgregs));
5365 	memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
5366 	kvm_get_dr(vcpu, 6, &val);
5367 	dbgregs->dr6 = val;
5368 	dbgregs->dr7 = vcpu->arch.dr7;
5369 }
5370 
kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu * vcpu,struct kvm_debugregs * dbgregs)5371 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
5372 					    struct kvm_debugregs *dbgregs)
5373 {
5374 	if (dbgregs->flags)
5375 		return -EINVAL;
5376 
5377 	if (!kvm_dr6_valid(dbgregs->dr6))
5378 		return -EINVAL;
5379 	if (!kvm_dr7_valid(dbgregs->dr7))
5380 		return -EINVAL;
5381 
5382 	memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
5383 	kvm_update_dr0123(vcpu);
5384 	vcpu->arch.dr6 = dbgregs->dr6;
5385 	vcpu->arch.dr7 = dbgregs->dr7;
5386 	kvm_update_dr7(vcpu);
5387 
5388 	return 0;
5389 }
5390 
5391 
kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu * vcpu,u8 * state,unsigned int size)5392 static void kvm_vcpu_ioctl_x86_get_xsave2(struct kvm_vcpu *vcpu,
5393 					  u8 *state, unsigned int size)
5394 {
5395 	/*
5396 	 * Only copy state for features that are enabled for the guest.  The
5397 	 * state itself isn't problematic, but setting bits in the header for
5398 	 * features that are supported in *this* host but not exposed to the
5399 	 * guest can result in KVM_SET_XSAVE failing when live migrating to a
5400 	 * compatible host without the features that are NOT exposed to the
5401 	 * guest.
5402 	 *
5403 	 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
5404 	 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
5405 	 * supported by the host.
5406 	 */
5407 	u64 supported_xcr0 = vcpu->arch.guest_supported_xcr0 |
5408 			     XFEATURE_MASK_FPSSE;
5409 
5410 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5411 		return;
5412 
5413 	fpu_copy_guest_fpstate_to_uabi(&vcpu->arch.guest_fpu, state, size,
5414 				       supported_xcr0, vcpu->arch.pkru);
5415 }
5416 
kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu * vcpu,struct kvm_xsave * guest_xsave)5417 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
5418 					 struct kvm_xsave *guest_xsave)
5419 {
5420 	return kvm_vcpu_ioctl_x86_get_xsave2(vcpu, (void *)guest_xsave->region,
5421 					     sizeof(guest_xsave->region));
5422 }
5423 
kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu * vcpu,struct kvm_xsave * guest_xsave)5424 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
5425 					struct kvm_xsave *guest_xsave)
5426 {
5427 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
5428 		return 0;
5429 
5430 	return fpu_copy_uabi_to_guest_fpstate(&vcpu->arch.guest_fpu,
5431 					      guest_xsave->region,
5432 					      kvm_caps.supported_xcr0,
5433 					      &vcpu->arch.pkru);
5434 }
5435 
kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu * vcpu,struct kvm_xcrs * guest_xcrs)5436 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
5437 					struct kvm_xcrs *guest_xcrs)
5438 {
5439 	if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
5440 		guest_xcrs->nr_xcrs = 0;
5441 		return;
5442 	}
5443 
5444 	guest_xcrs->nr_xcrs = 1;
5445 	guest_xcrs->flags = 0;
5446 	guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
5447 	guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
5448 }
5449 
kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu * vcpu,struct kvm_xcrs * guest_xcrs)5450 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
5451 				       struct kvm_xcrs *guest_xcrs)
5452 {
5453 	int i, r = 0;
5454 
5455 	if (!boot_cpu_has(X86_FEATURE_XSAVE))
5456 		return -EINVAL;
5457 
5458 	if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
5459 		return -EINVAL;
5460 
5461 	for (i = 0; i < guest_xcrs->nr_xcrs; i++)
5462 		/* Only support XCR0 currently */
5463 		if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
5464 			r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
5465 				guest_xcrs->xcrs[i].value);
5466 			break;
5467 		}
5468 	if (r)
5469 		r = -EINVAL;
5470 	return r;
5471 }
5472 
5473 /*
5474  * kvm_set_guest_paused() indicates to the guest kernel that it has been
5475  * stopped by the hypervisor.  This function will be called from the host only.
5476  * EINVAL is returned when the host attempts to set the flag for a guest that
5477  * does not support pv clocks.
5478  */
kvm_set_guest_paused(struct kvm_vcpu * vcpu)5479 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
5480 {
5481 	if (!vcpu->arch.pv_time.active)
5482 		return -EINVAL;
5483 	vcpu->arch.pvclock_set_guest_stopped_request = true;
5484 	kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5485 	return 0;
5486 }
5487 
kvm_arch_tsc_has_attr(struct kvm_vcpu * vcpu,struct kvm_device_attr * attr)5488 static int kvm_arch_tsc_has_attr(struct kvm_vcpu *vcpu,
5489 				 struct kvm_device_attr *attr)
5490 {
5491 	int r;
5492 
5493 	switch (attr->attr) {
5494 	case KVM_VCPU_TSC_OFFSET:
5495 		r = 0;
5496 		break;
5497 	default:
5498 		r = -ENXIO;
5499 	}
5500 
5501 	return r;
5502 }
5503 
kvm_arch_tsc_get_attr(struct kvm_vcpu * vcpu,struct kvm_device_attr * attr)5504 static int kvm_arch_tsc_get_attr(struct kvm_vcpu *vcpu,
5505 				 struct kvm_device_attr *attr)
5506 {
5507 	u64 __user *uaddr = kvm_get_attr_addr(attr);
5508 	int r;
5509 
5510 	if (IS_ERR(uaddr))
5511 		return PTR_ERR(uaddr);
5512 
5513 	switch (attr->attr) {
5514 	case KVM_VCPU_TSC_OFFSET:
5515 		r = -EFAULT;
5516 		if (put_user(vcpu->arch.l1_tsc_offset, uaddr))
5517 			break;
5518 		r = 0;
5519 		break;
5520 	default:
5521 		r = -ENXIO;
5522 	}
5523 
5524 	return r;
5525 }
5526 
kvm_arch_tsc_set_attr(struct kvm_vcpu * vcpu,struct kvm_device_attr * attr)5527 static int kvm_arch_tsc_set_attr(struct kvm_vcpu *vcpu,
5528 				 struct kvm_device_attr *attr)
5529 {
5530 	u64 __user *uaddr = kvm_get_attr_addr(attr);
5531 	struct kvm *kvm = vcpu->kvm;
5532 	int r;
5533 
5534 	if (IS_ERR(uaddr))
5535 		return PTR_ERR(uaddr);
5536 
5537 	switch (attr->attr) {
5538 	case KVM_VCPU_TSC_OFFSET: {
5539 		u64 offset, tsc, ns;
5540 		unsigned long flags;
5541 		bool matched;
5542 
5543 		r = -EFAULT;
5544 		if (get_user(offset, uaddr))
5545 			break;
5546 
5547 		raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
5548 
5549 		matched = (vcpu->arch.virtual_tsc_khz &&
5550 			   kvm->arch.last_tsc_khz == vcpu->arch.virtual_tsc_khz &&
5551 			   kvm->arch.last_tsc_offset == offset);
5552 
5553 		tsc = kvm_scale_tsc(rdtsc(), vcpu->arch.l1_tsc_scaling_ratio) + offset;
5554 		ns = get_kvmclock_base_ns();
5555 
5556 		__kvm_synchronize_tsc(vcpu, offset, tsc, ns, matched);
5557 		raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
5558 
5559 		r = 0;
5560 		break;
5561 	}
5562 	default:
5563 		r = -ENXIO;
5564 	}
5565 
5566 	return r;
5567 }
5568 
kvm_vcpu_ioctl_device_attr(struct kvm_vcpu * vcpu,unsigned int ioctl,void __user * argp)5569 static int kvm_vcpu_ioctl_device_attr(struct kvm_vcpu *vcpu,
5570 				      unsigned int ioctl,
5571 				      void __user *argp)
5572 {
5573 	struct kvm_device_attr attr;
5574 	int r;
5575 
5576 	if (copy_from_user(&attr, argp, sizeof(attr)))
5577 		return -EFAULT;
5578 
5579 	if (attr.group != KVM_VCPU_TSC_CTRL)
5580 		return -ENXIO;
5581 
5582 	switch (ioctl) {
5583 	case KVM_HAS_DEVICE_ATTR:
5584 		r = kvm_arch_tsc_has_attr(vcpu, &attr);
5585 		break;
5586 	case KVM_GET_DEVICE_ATTR:
5587 		r = kvm_arch_tsc_get_attr(vcpu, &attr);
5588 		break;
5589 	case KVM_SET_DEVICE_ATTR:
5590 		r = kvm_arch_tsc_set_attr(vcpu, &attr);
5591 		break;
5592 	}
5593 
5594 	return r;
5595 }
5596 
kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu * vcpu,struct kvm_enable_cap * cap)5597 static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
5598 				     struct kvm_enable_cap *cap)
5599 {
5600 	int r;
5601 	uint16_t vmcs_version;
5602 	void __user *user_ptr;
5603 
5604 	if (cap->flags)
5605 		return -EINVAL;
5606 
5607 	switch (cap->cap) {
5608 	case KVM_CAP_HYPERV_SYNIC2:
5609 		if (cap->args[0])
5610 			return -EINVAL;
5611 		fallthrough;
5612 
5613 	case KVM_CAP_HYPERV_SYNIC:
5614 		if (!irqchip_in_kernel(vcpu->kvm))
5615 			return -EINVAL;
5616 		return kvm_hv_activate_synic(vcpu, cap->cap ==
5617 					     KVM_CAP_HYPERV_SYNIC2);
5618 	case KVM_CAP_HYPERV_ENLIGHTENED_VMCS:
5619 		if (!kvm_x86_ops.nested_ops->enable_evmcs)
5620 			return -ENOTTY;
5621 		r = kvm_x86_ops.nested_ops->enable_evmcs(vcpu, &vmcs_version);
5622 		if (!r) {
5623 			user_ptr = (void __user *)(uintptr_t)cap->args[0];
5624 			if (copy_to_user(user_ptr, &vmcs_version,
5625 					 sizeof(vmcs_version)))
5626 				r = -EFAULT;
5627 		}
5628 		return r;
5629 	case KVM_CAP_HYPERV_DIRECT_TLBFLUSH:
5630 		if (!kvm_x86_ops.enable_l2_tlb_flush)
5631 			return -ENOTTY;
5632 
5633 		return static_call(kvm_x86_enable_l2_tlb_flush)(vcpu);
5634 
5635 	case KVM_CAP_HYPERV_ENFORCE_CPUID:
5636 		return kvm_hv_set_enforce_cpuid(vcpu, cap->args[0]);
5637 
5638 	case KVM_CAP_ENFORCE_PV_FEATURE_CPUID:
5639 		vcpu->arch.pv_cpuid.enforce = cap->args[0];
5640 		if (vcpu->arch.pv_cpuid.enforce)
5641 			kvm_update_pv_runtime(vcpu);
5642 
5643 		return 0;
5644 	default:
5645 		return -EINVAL;
5646 	}
5647 }
5648 
kvm_arch_vcpu_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)5649 long kvm_arch_vcpu_ioctl(struct file *filp,
5650 			 unsigned int ioctl, unsigned long arg)
5651 {
5652 	struct kvm_vcpu *vcpu = filp->private_data;
5653 	void __user *argp = (void __user *)arg;
5654 	int r;
5655 	union {
5656 		struct kvm_sregs2 *sregs2;
5657 		struct kvm_lapic_state *lapic;
5658 		struct kvm_xsave *xsave;
5659 		struct kvm_xcrs *xcrs;
5660 		void *buffer;
5661 	} u;
5662 
5663 	vcpu_load(vcpu);
5664 
5665 	u.buffer = NULL;
5666 	switch (ioctl) {
5667 	case KVM_GET_LAPIC: {
5668 		r = -EINVAL;
5669 		if (!lapic_in_kernel(vcpu))
5670 			goto out;
5671 		u.lapic = kzalloc(sizeof(struct kvm_lapic_state),
5672 				GFP_KERNEL_ACCOUNT);
5673 
5674 		r = -ENOMEM;
5675 		if (!u.lapic)
5676 			goto out;
5677 		r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
5678 		if (r)
5679 			goto out;
5680 		r = -EFAULT;
5681 		if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
5682 			goto out;
5683 		r = 0;
5684 		break;
5685 	}
5686 	case KVM_SET_LAPIC: {
5687 		r = -EINVAL;
5688 		if (!lapic_in_kernel(vcpu))
5689 			goto out;
5690 		u.lapic = memdup_user(argp, sizeof(*u.lapic));
5691 		if (IS_ERR(u.lapic)) {
5692 			r = PTR_ERR(u.lapic);
5693 			goto out_nofree;
5694 		}
5695 
5696 		r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
5697 		break;
5698 	}
5699 	case KVM_INTERRUPT: {
5700 		struct kvm_interrupt irq;
5701 
5702 		r = -EFAULT;
5703 		if (copy_from_user(&irq, argp, sizeof(irq)))
5704 			goto out;
5705 		r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
5706 		break;
5707 	}
5708 	case KVM_NMI: {
5709 		r = kvm_vcpu_ioctl_nmi(vcpu);
5710 		break;
5711 	}
5712 	case KVM_SMI: {
5713 		r = kvm_inject_smi(vcpu);
5714 		break;
5715 	}
5716 	case KVM_SET_CPUID: {
5717 		struct kvm_cpuid __user *cpuid_arg = argp;
5718 		struct kvm_cpuid cpuid;
5719 
5720 		r = -EFAULT;
5721 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5722 			goto out;
5723 		r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
5724 		break;
5725 	}
5726 	case KVM_SET_CPUID2: {
5727 		struct kvm_cpuid2 __user *cpuid_arg = argp;
5728 		struct kvm_cpuid2 cpuid;
5729 
5730 		r = -EFAULT;
5731 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5732 			goto out;
5733 		r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
5734 					      cpuid_arg->entries);
5735 		break;
5736 	}
5737 	case KVM_GET_CPUID2: {
5738 		struct kvm_cpuid2 __user *cpuid_arg = argp;
5739 		struct kvm_cpuid2 cpuid;
5740 
5741 		r = -EFAULT;
5742 		if (copy_from_user(&cpuid, cpuid_arg, sizeof(cpuid)))
5743 			goto out;
5744 		r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
5745 					      cpuid_arg->entries);
5746 		if (r)
5747 			goto out;
5748 		r = -EFAULT;
5749 		if (copy_to_user(cpuid_arg, &cpuid, sizeof(cpuid)))
5750 			goto out;
5751 		r = 0;
5752 		break;
5753 	}
5754 	case KVM_GET_MSRS: {
5755 		int idx = srcu_read_lock(&vcpu->kvm->srcu);
5756 		r = msr_io(vcpu, argp, do_get_msr, 1);
5757 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
5758 		break;
5759 	}
5760 	case KVM_SET_MSRS: {
5761 		int idx = srcu_read_lock(&vcpu->kvm->srcu);
5762 		r = msr_io(vcpu, argp, do_set_msr, 0);
5763 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
5764 		break;
5765 	}
5766 	case KVM_TPR_ACCESS_REPORTING: {
5767 		struct kvm_tpr_access_ctl tac;
5768 
5769 		r = -EFAULT;
5770 		if (copy_from_user(&tac, argp, sizeof(tac)))
5771 			goto out;
5772 		r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
5773 		if (r)
5774 			goto out;
5775 		r = -EFAULT;
5776 		if (copy_to_user(argp, &tac, sizeof(tac)))
5777 			goto out;
5778 		r = 0;
5779 		break;
5780 	};
5781 	case KVM_SET_VAPIC_ADDR: {
5782 		struct kvm_vapic_addr va;
5783 		int idx;
5784 
5785 		r = -EINVAL;
5786 		if (!lapic_in_kernel(vcpu))
5787 			goto out;
5788 		r = -EFAULT;
5789 		if (copy_from_user(&va, argp, sizeof(va)))
5790 			goto out;
5791 		idx = srcu_read_lock(&vcpu->kvm->srcu);
5792 		r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
5793 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
5794 		break;
5795 	}
5796 	case KVM_X86_SETUP_MCE: {
5797 		u64 mcg_cap;
5798 
5799 		r = -EFAULT;
5800 		if (copy_from_user(&mcg_cap, argp, sizeof(mcg_cap)))
5801 			goto out;
5802 		r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
5803 		break;
5804 	}
5805 	case KVM_X86_SET_MCE: {
5806 		struct kvm_x86_mce mce;
5807 
5808 		r = -EFAULT;
5809 		if (copy_from_user(&mce, argp, sizeof(mce)))
5810 			goto out;
5811 		r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
5812 		break;
5813 	}
5814 	case KVM_GET_VCPU_EVENTS: {
5815 		struct kvm_vcpu_events events;
5816 
5817 		kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
5818 
5819 		r = -EFAULT;
5820 		if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
5821 			break;
5822 		r = 0;
5823 		break;
5824 	}
5825 	case KVM_SET_VCPU_EVENTS: {
5826 		struct kvm_vcpu_events events;
5827 
5828 		r = -EFAULT;
5829 		if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
5830 			break;
5831 
5832 		kvm_vcpu_srcu_read_lock(vcpu);
5833 		r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
5834 		kvm_vcpu_srcu_read_unlock(vcpu);
5835 		break;
5836 	}
5837 	case KVM_GET_DEBUGREGS: {
5838 		struct kvm_debugregs dbgregs;
5839 
5840 		kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
5841 
5842 		r = -EFAULT;
5843 		if (copy_to_user(argp, &dbgregs,
5844 				 sizeof(struct kvm_debugregs)))
5845 			break;
5846 		r = 0;
5847 		break;
5848 	}
5849 	case KVM_SET_DEBUGREGS: {
5850 		struct kvm_debugregs dbgregs;
5851 
5852 		r = -EFAULT;
5853 		if (copy_from_user(&dbgregs, argp,
5854 				   sizeof(struct kvm_debugregs)))
5855 			break;
5856 
5857 		r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
5858 		break;
5859 	}
5860 	case KVM_GET_XSAVE: {
5861 		r = -EINVAL;
5862 		if (vcpu->arch.guest_fpu.uabi_size > sizeof(struct kvm_xsave))
5863 			break;
5864 
5865 		u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL_ACCOUNT);
5866 		r = -ENOMEM;
5867 		if (!u.xsave)
5868 			break;
5869 
5870 		kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
5871 
5872 		r = -EFAULT;
5873 		if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
5874 			break;
5875 		r = 0;
5876 		break;
5877 	}
5878 	case KVM_SET_XSAVE: {
5879 		int size = vcpu->arch.guest_fpu.uabi_size;
5880 
5881 		u.xsave = memdup_user(argp, size);
5882 		if (IS_ERR(u.xsave)) {
5883 			r = PTR_ERR(u.xsave);
5884 			goto out_nofree;
5885 		}
5886 
5887 		r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
5888 		break;
5889 	}
5890 
5891 	case KVM_GET_XSAVE2: {
5892 		int size = vcpu->arch.guest_fpu.uabi_size;
5893 
5894 		u.xsave = kzalloc(size, GFP_KERNEL_ACCOUNT);
5895 		r = -ENOMEM;
5896 		if (!u.xsave)
5897 			break;
5898 
5899 		kvm_vcpu_ioctl_x86_get_xsave2(vcpu, u.buffer, size);
5900 
5901 		r = -EFAULT;
5902 		if (copy_to_user(argp, u.xsave, size))
5903 			break;
5904 
5905 		r = 0;
5906 		break;
5907 	}
5908 
5909 	case KVM_GET_XCRS: {
5910 		u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL_ACCOUNT);
5911 		r = -ENOMEM;
5912 		if (!u.xcrs)
5913 			break;
5914 
5915 		kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
5916 
5917 		r = -EFAULT;
5918 		if (copy_to_user(argp, u.xcrs,
5919 				 sizeof(struct kvm_xcrs)))
5920 			break;
5921 		r = 0;
5922 		break;
5923 	}
5924 	case KVM_SET_XCRS: {
5925 		u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
5926 		if (IS_ERR(u.xcrs)) {
5927 			r = PTR_ERR(u.xcrs);
5928 			goto out_nofree;
5929 		}
5930 
5931 		r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
5932 		break;
5933 	}
5934 	case KVM_SET_TSC_KHZ: {
5935 		u32 user_tsc_khz;
5936 
5937 		r = -EINVAL;
5938 		user_tsc_khz = (u32)arg;
5939 
5940 		if (kvm_caps.has_tsc_control &&
5941 		    user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
5942 			goto out;
5943 
5944 		if (user_tsc_khz == 0)
5945 			user_tsc_khz = tsc_khz;
5946 
5947 		if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
5948 			r = 0;
5949 
5950 		goto out;
5951 	}
5952 	case KVM_GET_TSC_KHZ: {
5953 		r = vcpu->arch.virtual_tsc_khz;
5954 		goto out;
5955 	}
5956 	case KVM_KVMCLOCK_CTRL: {
5957 		r = kvm_set_guest_paused(vcpu);
5958 		goto out;
5959 	}
5960 	case KVM_ENABLE_CAP: {
5961 		struct kvm_enable_cap cap;
5962 
5963 		r = -EFAULT;
5964 		if (copy_from_user(&cap, argp, sizeof(cap)))
5965 			goto out;
5966 		r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
5967 		break;
5968 	}
5969 	case KVM_GET_NESTED_STATE: {
5970 		struct kvm_nested_state __user *user_kvm_nested_state = argp;
5971 		u32 user_data_size;
5972 
5973 		r = -EINVAL;
5974 		if (!kvm_x86_ops.nested_ops->get_state)
5975 			break;
5976 
5977 		BUILD_BUG_ON(sizeof(user_data_size) != sizeof(user_kvm_nested_state->size));
5978 		r = -EFAULT;
5979 		if (get_user(user_data_size, &user_kvm_nested_state->size))
5980 			break;
5981 
5982 		r = kvm_x86_ops.nested_ops->get_state(vcpu, user_kvm_nested_state,
5983 						     user_data_size);
5984 		if (r < 0)
5985 			break;
5986 
5987 		if (r > user_data_size) {
5988 			if (put_user(r, &user_kvm_nested_state->size))
5989 				r = -EFAULT;
5990 			else
5991 				r = -E2BIG;
5992 			break;
5993 		}
5994 
5995 		r = 0;
5996 		break;
5997 	}
5998 	case KVM_SET_NESTED_STATE: {
5999 		struct kvm_nested_state __user *user_kvm_nested_state = argp;
6000 		struct kvm_nested_state kvm_state;
6001 		int idx;
6002 
6003 		r = -EINVAL;
6004 		if (!kvm_x86_ops.nested_ops->set_state)
6005 			break;
6006 
6007 		r = -EFAULT;
6008 		if (copy_from_user(&kvm_state, user_kvm_nested_state, sizeof(kvm_state)))
6009 			break;
6010 
6011 		r = -EINVAL;
6012 		if (kvm_state.size < sizeof(kvm_state))
6013 			break;
6014 
6015 		if (kvm_state.flags &
6016 		    ~(KVM_STATE_NESTED_RUN_PENDING | KVM_STATE_NESTED_GUEST_MODE
6017 		      | KVM_STATE_NESTED_EVMCS | KVM_STATE_NESTED_MTF_PENDING
6018 		      | KVM_STATE_NESTED_GIF_SET))
6019 			break;
6020 
6021 		/* nested_run_pending implies guest_mode.  */
6022 		if ((kvm_state.flags & KVM_STATE_NESTED_RUN_PENDING)
6023 		    && !(kvm_state.flags & KVM_STATE_NESTED_GUEST_MODE))
6024 			break;
6025 
6026 		idx = srcu_read_lock(&vcpu->kvm->srcu);
6027 		r = kvm_x86_ops.nested_ops->set_state(vcpu, user_kvm_nested_state, &kvm_state);
6028 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
6029 		break;
6030 	}
6031 	case KVM_GET_SUPPORTED_HV_CPUID:
6032 		r = kvm_ioctl_get_supported_hv_cpuid(vcpu, argp);
6033 		break;
6034 #ifdef CONFIG_KVM_XEN
6035 	case KVM_XEN_VCPU_GET_ATTR: {
6036 		struct kvm_xen_vcpu_attr xva;
6037 
6038 		r = -EFAULT;
6039 		if (copy_from_user(&xva, argp, sizeof(xva)))
6040 			goto out;
6041 		r = kvm_xen_vcpu_get_attr(vcpu, &xva);
6042 		if (!r && copy_to_user(argp, &xva, sizeof(xva)))
6043 			r = -EFAULT;
6044 		break;
6045 	}
6046 	case KVM_XEN_VCPU_SET_ATTR: {
6047 		struct kvm_xen_vcpu_attr xva;
6048 
6049 		r = -EFAULT;
6050 		if (copy_from_user(&xva, argp, sizeof(xva)))
6051 			goto out;
6052 		r = kvm_xen_vcpu_set_attr(vcpu, &xva);
6053 		break;
6054 	}
6055 #endif
6056 	case KVM_GET_SREGS2: {
6057 		u.sregs2 = kzalloc(sizeof(struct kvm_sregs2), GFP_KERNEL);
6058 		r = -ENOMEM;
6059 		if (!u.sregs2)
6060 			goto out;
6061 		__get_sregs2(vcpu, u.sregs2);
6062 		r = -EFAULT;
6063 		if (copy_to_user(argp, u.sregs2, sizeof(struct kvm_sregs2)))
6064 			goto out;
6065 		r = 0;
6066 		break;
6067 	}
6068 	case KVM_SET_SREGS2: {
6069 		u.sregs2 = memdup_user(argp, sizeof(struct kvm_sregs2));
6070 		if (IS_ERR(u.sregs2)) {
6071 			r = PTR_ERR(u.sregs2);
6072 			u.sregs2 = NULL;
6073 			goto out;
6074 		}
6075 		r = __set_sregs2(vcpu, u.sregs2);
6076 		break;
6077 	}
6078 	case KVM_HAS_DEVICE_ATTR:
6079 	case KVM_GET_DEVICE_ATTR:
6080 	case KVM_SET_DEVICE_ATTR:
6081 		r = kvm_vcpu_ioctl_device_attr(vcpu, ioctl, argp);
6082 		break;
6083 	default:
6084 		r = -EINVAL;
6085 	}
6086 out:
6087 	kfree(u.buffer);
6088 out_nofree:
6089 	vcpu_put(vcpu);
6090 	return r;
6091 }
6092 
kvm_arch_vcpu_fault(struct kvm_vcpu * vcpu,struct vm_fault * vmf)6093 vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
6094 {
6095 	return VM_FAULT_SIGBUS;
6096 }
6097 
kvm_vm_ioctl_set_tss_addr(struct kvm * kvm,unsigned long addr)6098 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
6099 {
6100 	int ret;
6101 
6102 	if (addr > (unsigned int)(-3 * PAGE_SIZE))
6103 		return -EINVAL;
6104 	ret = static_call(kvm_x86_set_tss_addr)(kvm, addr);
6105 	return ret;
6106 }
6107 
kvm_vm_ioctl_set_identity_map_addr(struct kvm * kvm,u64 ident_addr)6108 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
6109 					      u64 ident_addr)
6110 {
6111 	return static_call(kvm_x86_set_identity_map_addr)(kvm, ident_addr);
6112 }
6113 
kvm_vm_ioctl_set_nr_mmu_pages(struct kvm * kvm,unsigned long kvm_nr_mmu_pages)6114 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
6115 					 unsigned long kvm_nr_mmu_pages)
6116 {
6117 	if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
6118 		return -EINVAL;
6119 
6120 	mutex_lock(&kvm->slots_lock);
6121 
6122 	kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
6123 	kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
6124 
6125 	mutex_unlock(&kvm->slots_lock);
6126 	return 0;
6127 }
6128 
kvm_vm_ioctl_get_irqchip(struct kvm * kvm,struct kvm_irqchip * chip)6129 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6130 {
6131 	struct kvm_pic *pic = kvm->arch.vpic;
6132 	int r;
6133 
6134 	r = 0;
6135 	switch (chip->chip_id) {
6136 	case KVM_IRQCHIP_PIC_MASTER:
6137 		memcpy(&chip->chip.pic, &pic->pics[0],
6138 			sizeof(struct kvm_pic_state));
6139 		break;
6140 	case KVM_IRQCHIP_PIC_SLAVE:
6141 		memcpy(&chip->chip.pic, &pic->pics[1],
6142 			sizeof(struct kvm_pic_state));
6143 		break;
6144 	case KVM_IRQCHIP_IOAPIC:
6145 		kvm_get_ioapic(kvm, &chip->chip.ioapic);
6146 		break;
6147 	default:
6148 		r = -EINVAL;
6149 		break;
6150 	}
6151 	return r;
6152 }
6153 
kvm_vm_ioctl_set_irqchip(struct kvm * kvm,struct kvm_irqchip * chip)6154 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
6155 {
6156 	struct kvm_pic *pic = kvm->arch.vpic;
6157 	int r;
6158 
6159 	r = 0;
6160 	switch (chip->chip_id) {
6161 	case KVM_IRQCHIP_PIC_MASTER:
6162 		spin_lock(&pic->lock);
6163 		memcpy(&pic->pics[0], &chip->chip.pic,
6164 			sizeof(struct kvm_pic_state));
6165 		spin_unlock(&pic->lock);
6166 		break;
6167 	case KVM_IRQCHIP_PIC_SLAVE:
6168 		spin_lock(&pic->lock);
6169 		memcpy(&pic->pics[1], &chip->chip.pic,
6170 			sizeof(struct kvm_pic_state));
6171 		spin_unlock(&pic->lock);
6172 		break;
6173 	case KVM_IRQCHIP_IOAPIC:
6174 		kvm_set_ioapic(kvm, &chip->chip.ioapic);
6175 		break;
6176 	default:
6177 		r = -EINVAL;
6178 		break;
6179 	}
6180 	kvm_pic_update_irq(pic);
6181 	return r;
6182 }
6183 
kvm_vm_ioctl_get_pit(struct kvm * kvm,struct kvm_pit_state * ps)6184 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6185 {
6186 	struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
6187 
6188 	BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
6189 
6190 	mutex_lock(&kps->lock);
6191 	memcpy(ps, &kps->channels, sizeof(*ps));
6192 	mutex_unlock(&kps->lock);
6193 	return 0;
6194 }
6195 
kvm_vm_ioctl_set_pit(struct kvm * kvm,struct kvm_pit_state * ps)6196 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
6197 {
6198 	int i;
6199 	struct kvm_pit *pit = kvm->arch.vpit;
6200 
6201 	mutex_lock(&pit->pit_state.lock);
6202 	memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
6203 	for (i = 0; i < 3; i++)
6204 		kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
6205 	mutex_unlock(&pit->pit_state.lock);
6206 	return 0;
6207 }
6208 
kvm_vm_ioctl_get_pit2(struct kvm * kvm,struct kvm_pit_state2 * ps)6209 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6210 {
6211 	mutex_lock(&kvm->arch.vpit->pit_state.lock);
6212 	memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
6213 		sizeof(ps->channels));
6214 	ps->flags = kvm->arch.vpit->pit_state.flags;
6215 	mutex_unlock(&kvm->arch.vpit->pit_state.lock);
6216 	memset(&ps->reserved, 0, sizeof(ps->reserved));
6217 	return 0;
6218 }
6219 
kvm_vm_ioctl_set_pit2(struct kvm * kvm,struct kvm_pit_state2 * ps)6220 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
6221 {
6222 	int start = 0;
6223 	int i;
6224 	u32 prev_legacy, cur_legacy;
6225 	struct kvm_pit *pit = kvm->arch.vpit;
6226 
6227 	mutex_lock(&pit->pit_state.lock);
6228 	prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
6229 	cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
6230 	if (!prev_legacy && cur_legacy)
6231 		start = 1;
6232 	memcpy(&pit->pit_state.channels, &ps->channels,
6233 	       sizeof(pit->pit_state.channels));
6234 	pit->pit_state.flags = ps->flags;
6235 	for (i = 0; i < 3; i++)
6236 		kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
6237 				   start && i == 0);
6238 	mutex_unlock(&pit->pit_state.lock);
6239 	return 0;
6240 }
6241 
kvm_vm_ioctl_reinject(struct kvm * kvm,struct kvm_reinject_control * control)6242 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
6243 				 struct kvm_reinject_control *control)
6244 {
6245 	struct kvm_pit *pit = kvm->arch.vpit;
6246 
6247 	/* pit->pit_state.lock was overloaded to prevent userspace from getting
6248 	 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
6249 	 * ioctls in parallel.  Use a separate lock if that ioctl isn't rare.
6250 	 */
6251 	mutex_lock(&pit->pit_state.lock);
6252 	kvm_pit_set_reinject(pit, control->pit_reinject);
6253 	mutex_unlock(&pit->pit_state.lock);
6254 
6255 	return 0;
6256 }
6257 
kvm_arch_sync_dirty_log(struct kvm * kvm,struct kvm_memory_slot * memslot)6258 void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
6259 {
6260 
6261 	/*
6262 	 * Flush all CPUs' dirty log buffers to the  dirty_bitmap.  Called
6263 	 * before reporting dirty_bitmap to userspace.  KVM flushes the buffers
6264 	 * on all VM-Exits, thus we only need to kick running vCPUs to force a
6265 	 * VM-Exit.
6266 	 */
6267 	struct kvm_vcpu *vcpu;
6268 	unsigned long i;
6269 
6270 	kvm_for_each_vcpu(i, vcpu, kvm)
6271 		kvm_vcpu_kick(vcpu);
6272 }
6273 
kvm_vm_ioctl_irq_line(struct kvm * kvm,struct kvm_irq_level * irq_event,bool line_status)6274 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
6275 			bool line_status)
6276 {
6277 	if (!irqchip_in_kernel(kvm))
6278 		return -ENXIO;
6279 
6280 	irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
6281 					irq_event->irq, irq_event->level,
6282 					line_status);
6283 	return 0;
6284 }
6285 
kvm_vm_ioctl_enable_cap(struct kvm * kvm,struct kvm_enable_cap * cap)6286 int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
6287 			    struct kvm_enable_cap *cap)
6288 {
6289 	int r;
6290 
6291 	if (cap->flags)
6292 		return -EINVAL;
6293 
6294 	switch (cap->cap) {
6295 	case KVM_CAP_DISABLE_QUIRKS2:
6296 		r = -EINVAL;
6297 		if (cap->args[0] & ~KVM_X86_VALID_QUIRKS)
6298 			break;
6299 		fallthrough;
6300 	case KVM_CAP_DISABLE_QUIRKS:
6301 		kvm->arch.disabled_quirks = cap->args[0];
6302 		r = 0;
6303 		break;
6304 	case KVM_CAP_SPLIT_IRQCHIP: {
6305 		mutex_lock(&kvm->lock);
6306 		r = -EINVAL;
6307 		if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
6308 			goto split_irqchip_unlock;
6309 		r = -EEXIST;
6310 		if (irqchip_in_kernel(kvm))
6311 			goto split_irqchip_unlock;
6312 		if (kvm->created_vcpus)
6313 			goto split_irqchip_unlock;
6314 		r = kvm_setup_empty_irq_routing(kvm);
6315 		if (r)
6316 			goto split_irqchip_unlock;
6317 		/* Pairs with irqchip_in_kernel. */
6318 		smp_wmb();
6319 		kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
6320 		kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
6321 		kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6322 		r = 0;
6323 split_irqchip_unlock:
6324 		mutex_unlock(&kvm->lock);
6325 		break;
6326 	}
6327 	case KVM_CAP_X2APIC_API:
6328 		r = -EINVAL;
6329 		if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
6330 			break;
6331 
6332 		if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
6333 			kvm->arch.x2apic_format = true;
6334 		if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
6335 			kvm->arch.x2apic_broadcast_quirk_disabled = true;
6336 
6337 		r = 0;
6338 		break;
6339 	case KVM_CAP_X86_DISABLE_EXITS:
6340 		r = -EINVAL;
6341 		if (cap->args[0] & ~KVM_X86_DISABLE_VALID_EXITS)
6342 			break;
6343 
6344 		if (cap->args[0] & KVM_X86_DISABLE_EXITS_PAUSE)
6345 			kvm->arch.pause_in_guest = true;
6346 
6347 #define SMT_RSB_MSG "This processor is affected by the Cross-Thread Return Predictions vulnerability. " \
6348 		    "KVM_CAP_X86_DISABLE_EXITS should only be used with SMT disabled or trusted guests."
6349 
6350 		if (!mitigate_smt_rsb) {
6351 			if (boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible() &&
6352 			    (cap->args[0] & ~KVM_X86_DISABLE_EXITS_PAUSE))
6353 				pr_warn_once(SMT_RSB_MSG);
6354 
6355 			if ((cap->args[0] & KVM_X86_DISABLE_EXITS_MWAIT) &&
6356 			    kvm_can_mwait_in_guest())
6357 				kvm->arch.mwait_in_guest = true;
6358 			if (cap->args[0] & KVM_X86_DISABLE_EXITS_HLT)
6359 				kvm->arch.hlt_in_guest = true;
6360 			if (cap->args[0] & KVM_X86_DISABLE_EXITS_CSTATE)
6361 				kvm->arch.cstate_in_guest = true;
6362 		}
6363 
6364 		r = 0;
6365 		break;
6366 	case KVM_CAP_MSR_PLATFORM_INFO:
6367 		kvm->arch.guest_can_read_msr_platform_info = cap->args[0];
6368 		r = 0;
6369 		break;
6370 	case KVM_CAP_EXCEPTION_PAYLOAD:
6371 		kvm->arch.exception_payload_enabled = cap->args[0];
6372 		r = 0;
6373 		break;
6374 	case KVM_CAP_X86_TRIPLE_FAULT_EVENT:
6375 		kvm->arch.triple_fault_event = cap->args[0];
6376 		r = 0;
6377 		break;
6378 	case KVM_CAP_X86_USER_SPACE_MSR:
6379 		r = -EINVAL;
6380 		if (cap->args[0] & ~KVM_MSR_EXIT_REASON_VALID_MASK)
6381 			break;
6382 		kvm->arch.user_space_msr_mask = cap->args[0];
6383 		r = 0;
6384 		break;
6385 	case KVM_CAP_X86_BUS_LOCK_EXIT:
6386 		r = -EINVAL;
6387 		if (cap->args[0] & ~KVM_BUS_LOCK_DETECTION_VALID_MODE)
6388 			break;
6389 
6390 		if ((cap->args[0] & KVM_BUS_LOCK_DETECTION_OFF) &&
6391 		    (cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT))
6392 			break;
6393 
6394 		if (kvm_caps.has_bus_lock_exit &&
6395 		    cap->args[0] & KVM_BUS_LOCK_DETECTION_EXIT)
6396 			kvm->arch.bus_lock_detection_enabled = true;
6397 		r = 0;
6398 		break;
6399 #ifdef CONFIG_X86_SGX_KVM
6400 	case KVM_CAP_SGX_ATTRIBUTE: {
6401 		unsigned long allowed_attributes = 0;
6402 
6403 		r = sgx_set_attribute(&allowed_attributes, cap->args[0]);
6404 		if (r)
6405 			break;
6406 
6407 		/* KVM only supports the PROVISIONKEY privileged attribute. */
6408 		if ((allowed_attributes & SGX_ATTR_PROVISIONKEY) &&
6409 		    !(allowed_attributes & ~SGX_ATTR_PROVISIONKEY))
6410 			kvm->arch.sgx_provisioning_allowed = true;
6411 		else
6412 			r = -EINVAL;
6413 		break;
6414 	}
6415 #endif
6416 	case KVM_CAP_VM_COPY_ENC_CONTEXT_FROM:
6417 		r = -EINVAL;
6418 		if (!kvm_x86_ops.vm_copy_enc_context_from)
6419 			break;
6420 
6421 		r = static_call(kvm_x86_vm_copy_enc_context_from)(kvm, cap->args[0]);
6422 		break;
6423 	case KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM:
6424 		r = -EINVAL;
6425 		if (!kvm_x86_ops.vm_move_enc_context_from)
6426 			break;
6427 
6428 		r = static_call(kvm_x86_vm_move_enc_context_from)(kvm, cap->args[0]);
6429 		break;
6430 	case KVM_CAP_EXIT_HYPERCALL:
6431 		if (cap->args[0] & ~KVM_EXIT_HYPERCALL_VALID_MASK) {
6432 			r = -EINVAL;
6433 			break;
6434 		}
6435 		kvm->arch.hypercall_exit_enabled = cap->args[0];
6436 		r = 0;
6437 		break;
6438 	case KVM_CAP_EXIT_ON_EMULATION_FAILURE:
6439 		r = -EINVAL;
6440 		if (cap->args[0] & ~1)
6441 			break;
6442 		kvm->arch.exit_on_emulation_error = cap->args[0];
6443 		r = 0;
6444 		break;
6445 	case KVM_CAP_PMU_CAPABILITY:
6446 		r = -EINVAL;
6447 		if (!enable_pmu || (cap->args[0] & ~KVM_CAP_PMU_VALID_MASK))
6448 			break;
6449 
6450 		mutex_lock(&kvm->lock);
6451 		if (!kvm->created_vcpus) {
6452 			kvm->arch.enable_pmu = !(cap->args[0] & KVM_PMU_CAP_DISABLE);
6453 			r = 0;
6454 		}
6455 		mutex_unlock(&kvm->lock);
6456 		break;
6457 	case KVM_CAP_MAX_VCPU_ID:
6458 		r = -EINVAL;
6459 		if (cap->args[0] > KVM_MAX_VCPU_IDS)
6460 			break;
6461 
6462 		mutex_lock(&kvm->lock);
6463 		if (kvm->arch.max_vcpu_ids == cap->args[0]) {
6464 			r = 0;
6465 		} else if (!kvm->arch.max_vcpu_ids) {
6466 			kvm->arch.max_vcpu_ids = cap->args[0];
6467 			r = 0;
6468 		}
6469 		mutex_unlock(&kvm->lock);
6470 		break;
6471 	case KVM_CAP_X86_NOTIFY_VMEXIT:
6472 		r = -EINVAL;
6473 		if ((u32)cap->args[0] & ~KVM_X86_NOTIFY_VMEXIT_VALID_BITS)
6474 			break;
6475 		if (!kvm_caps.has_notify_vmexit)
6476 			break;
6477 		if (!((u32)cap->args[0] & KVM_X86_NOTIFY_VMEXIT_ENABLED))
6478 			break;
6479 		mutex_lock(&kvm->lock);
6480 		if (!kvm->created_vcpus) {
6481 			kvm->arch.notify_window = cap->args[0] >> 32;
6482 			kvm->arch.notify_vmexit_flags = (u32)cap->args[0];
6483 			r = 0;
6484 		}
6485 		mutex_unlock(&kvm->lock);
6486 		break;
6487 	case KVM_CAP_VM_DISABLE_NX_HUGE_PAGES:
6488 		r = -EINVAL;
6489 
6490 		/*
6491 		 * Since the risk of disabling NX hugepages is a guest crashing
6492 		 * the system, ensure the userspace process has permission to
6493 		 * reboot the system.
6494 		 *
6495 		 * Note that unlike the reboot() syscall, the process must have
6496 		 * this capability in the root namespace because exposing
6497 		 * /dev/kvm into a container does not limit the scope of the
6498 		 * iTLB multihit bug to that container. In other words,
6499 		 * this must use capable(), not ns_capable().
6500 		 */
6501 		if (!capable(CAP_SYS_BOOT)) {
6502 			r = -EPERM;
6503 			break;
6504 		}
6505 
6506 		if (cap->args[0])
6507 			break;
6508 
6509 		mutex_lock(&kvm->lock);
6510 		if (!kvm->created_vcpus) {
6511 			kvm->arch.disable_nx_huge_pages = true;
6512 			r = 0;
6513 		}
6514 		mutex_unlock(&kvm->lock);
6515 		break;
6516 	default:
6517 		r = -EINVAL;
6518 		break;
6519 	}
6520 	return r;
6521 }
6522 
kvm_alloc_msr_filter(bool default_allow)6523 static struct kvm_x86_msr_filter *kvm_alloc_msr_filter(bool default_allow)
6524 {
6525 	struct kvm_x86_msr_filter *msr_filter;
6526 
6527 	msr_filter = kzalloc(sizeof(*msr_filter), GFP_KERNEL_ACCOUNT);
6528 	if (!msr_filter)
6529 		return NULL;
6530 
6531 	msr_filter->default_allow = default_allow;
6532 	return msr_filter;
6533 }
6534 
kvm_free_msr_filter(struct kvm_x86_msr_filter * msr_filter)6535 static void kvm_free_msr_filter(struct kvm_x86_msr_filter *msr_filter)
6536 {
6537 	u32 i;
6538 
6539 	if (!msr_filter)
6540 		return;
6541 
6542 	for (i = 0; i < msr_filter->count; i++)
6543 		kfree(msr_filter->ranges[i].bitmap);
6544 
6545 	kfree(msr_filter);
6546 }
6547 
kvm_add_msr_filter(struct kvm_x86_msr_filter * msr_filter,struct kvm_msr_filter_range * user_range)6548 static int kvm_add_msr_filter(struct kvm_x86_msr_filter *msr_filter,
6549 			      struct kvm_msr_filter_range *user_range)
6550 {
6551 	unsigned long *bitmap;
6552 	size_t bitmap_size;
6553 
6554 	if (!user_range->nmsrs)
6555 		return 0;
6556 
6557 	if (user_range->flags & ~KVM_MSR_FILTER_RANGE_VALID_MASK)
6558 		return -EINVAL;
6559 
6560 	if (!user_range->flags)
6561 		return -EINVAL;
6562 
6563 	bitmap_size = BITS_TO_LONGS(user_range->nmsrs) * sizeof(long);
6564 	if (!bitmap_size || bitmap_size > KVM_MSR_FILTER_MAX_BITMAP_SIZE)
6565 		return -EINVAL;
6566 
6567 	bitmap = memdup_user((__user u8*)user_range->bitmap, bitmap_size);
6568 	if (IS_ERR(bitmap))
6569 		return PTR_ERR(bitmap);
6570 
6571 	msr_filter->ranges[msr_filter->count] = (struct msr_bitmap_range) {
6572 		.flags = user_range->flags,
6573 		.base = user_range->base,
6574 		.nmsrs = user_range->nmsrs,
6575 		.bitmap = bitmap,
6576 	};
6577 
6578 	msr_filter->count++;
6579 	return 0;
6580 }
6581 
kvm_vm_ioctl_set_msr_filter(struct kvm * kvm,struct kvm_msr_filter * filter)6582 static int kvm_vm_ioctl_set_msr_filter(struct kvm *kvm,
6583 				       struct kvm_msr_filter *filter)
6584 {
6585 	struct kvm_x86_msr_filter *new_filter, *old_filter;
6586 	bool default_allow;
6587 	bool empty = true;
6588 	int r;
6589 	u32 i;
6590 
6591 	if (filter->flags & ~KVM_MSR_FILTER_VALID_MASK)
6592 		return -EINVAL;
6593 
6594 	for (i = 0; i < ARRAY_SIZE(filter->ranges); i++)
6595 		empty &= !filter->ranges[i].nmsrs;
6596 
6597 	default_allow = !(filter->flags & KVM_MSR_FILTER_DEFAULT_DENY);
6598 	if (empty && !default_allow)
6599 		return -EINVAL;
6600 
6601 	new_filter = kvm_alloc_msr_filter(default_allow);
6602 	if (!new_filter)
6603 		return -ENOMEM;
6604 
6605 	for (i = 0; i < ARRAY_SIZE(filter->ranges); i++) {
6606 		r = kvm_add_msr_filter(new_filter, &filter->ranges[i]);
6607 		if (r) {
6608 			kvm_free_msr_filter(new_filter);
6609 			return r;
6610 		}
6611 	}
6612 
6613 	mutex_lock(&kvm->lock);
6614 	old_filter = rcu_replace_pointer(kvm->arch.msr_filter, new_filter,
6615 					 mutex_is_locked(&kvm->lock));
6616 	mutex_unlock(&kvm->lock);
6617 	synchronize_srcu(&kvm->srcu);
6618 
6619 	kvm_free_msr_filter(old_filter);
6620 
6621 	kvm_make_all_cpus_request(kvm, KVM_REQ_MSR_FILTER_CHANGED);
6622 
6623 	return 0;
6624 }
6625 
6626 #ifdef CONFIG_KVM_COMPAT
6627 /* for KVM_X86_SET_MSR_FILTER */
6628 struct kvm_msr_filter_range_compat {
6629 	__u32 flags;
6630 	__u32 nmsrs;
6631 	__u32 base;
6632 	__u32 bitmap;
6633 };
6634 
6635 struct kvm_msr_filter_compat {
6636 	__u32 flags;
6637 	struct kvm_msr_filter_range_compat ranges[KVM_MSR_FILTER_MAX_RANGES];
6638 };
6639 
6640 #define KVM_X86_SET_MSR_FILTER_COMPAT _IOW(KVMIO, 0xc6, struct kvm_msr_filter_compat)
6641 
kvm_arch_vm_compat_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)6642 long kvm_arch_vm_compat_ioctl(struct file *filp, unsigned int ioctl,
6643 			      unsigned long arg)
6644 {
6645 	void __user *argp = (void __user *)arg;
6646 	struct kvm *kvm = filp->private_data;
6647 	long r = -ENOTTY;
6648 
6649 	switch (ioctl) {
6650 	case KVM_X86_SET_MSR_FILTER_COMPAT: {
6651 		struct kvm_msr_filter __user *user_msr_filter = argp;
6652 		struct kvm_msr_filter_compat filter_compat;
6653 		struct kvm_msr_filter filter;
6654 		int i;
6655 
6656 		if (copy_from_user(&filter_compat, user_msr_filter,
6657 				   sizeof(filter_compat)))
6658 			return -EFAULT;
6659 
6660 		filter.flags = filter_compat.flags;
6661 		for (i = 0; i < ARRAY_SIZE(filter.ranges); i++) {
6662 			struct kvm_msr_filter_range_compat *cr;
6663 
6664 			cr = &filter_compat.ranges[i];
6665 			filter.ranges[i] = (struct kvm_msr_filter_range) {
6666 				.flags = cr->flags,
6667 				.nmsrs = cr->nmsrs,
6668 				.base = cr->base,
6669 				.bitmap = (__u8 *)(ulong)cr->bitmap,
6670 			};
6671 		}
6672 
6673 		r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
6674 		break;
6675 	}
6676 	}
6677 
6678 	return r;
6679 }
6680 #endif
6681 
6682 #ifdef CONFIG_HAVE_KVM_PM_NOTIFIER
kvm_arch_suspend_notifier(struct kvm * kvm)6683 static int kvm_arch_suspend_notifier(struct kvm *kvm)
6684 {
6685 	struct kvm_vcpu *vcpu;
6686 	unsigned long i;
6687 	int ret = 0;
6688 
6689 	mutex_lock(&kvm->lock);
6690 	kvm_for_each_vcpu(i, vcpu, kvm) {
6691 		if (!vcpu->arch.pv_time.active)
6692 			continue;
6693 
6694 		ret = kvm_set_guest_paused(vcpu);
6695 		if (ret) {
6696 			kvm_err("Failed to pause guest VCPU%d: %d\n",
6697 				vcpu->vcpu_id, ret);
6698 			break;
6699 		}
6700 	}
6701 	mutex_unlock(&kvm->lock);
6702 
6703 	return ret ? NOTIFY_BAD : NOTIFY_DONE;
6704 }
6705 
kvm_arch_pm_notifier(struct kvm * kvm,unsigned long state)6706 int kvm_arch_pm_notifier(struct kvm *kvm, unsigned long state)
6707 {
6708 	switch (state) {
6709 	case PM_HIBERNATION_PREPARE:
6710 	case PM_SUSPEND_PREPARE:
6711 		return kvm_arch_suspend_notifier(kvm);
6712 	}
6713 
6714 	return NOTIFY_DONE;
6715 }
6716 #endif /* CONFIG_HAVE_KVM_PM_NOTIFIER */
6717 
kvm_vm_ioctl_get_clock(struct kvm * kvm,void __user * argp)6718 static int kvm_vm_ioctl_get_clock(struct kvm *kvm, void __user *argp)
6719 {
6720 	struct kvm_clock_data data = { 0 };
6721 
6722 	get_kvmclock(kvm, &data);
6723 	if (copy_to_user(argp, &data, sizeof(data)))
6724 		return -EFAULT;
6725 
6726 	return 0;
6727 }
6728 
kvm_vm_ioctl_set_clock(struct kvm * kvm,void __user * argp)6729 static int kvm_vm_ioctl_set_clock(struct kvm *kvm, void __user *argp)
6730 {
6731 	struct kvm_arch *ka = &kvm->arch;
6732 	struct kvm_clock_data data;
6733 	u64 now_raw_ns;
6734 
6735 	if (copy_from_user(&data, argp, sizeof(data)))
6736 		return -EFAULT;
6737 
6738 	/*
6739 	 * Only KVM_CLOCK_REALTIME is used, but allow passing the
6740 	 * result of KVM_GET_CLOCK back to KVM_SET_CLOCK.
6741 	 */
6742 	if (data.flags & ~KVM_CLOCK_VALID_FLAGS)
6743 		return -EINVAL;
6744 
6745 	kvm_hv_request_tsc_page_update(kvm);
6746 	kvm_start_pvclock_update(kvm);
6747 	pvclock_update_vm_gtod_copy(kvm);
6748 
6749 	/*
6750 	 * This pairs with kvm_guest_time_update(): when masterclock is
6751 	 * in use, we use master_kernel_ns + kvmclock_offset to set
6752 	 * unsigned 'system_time' so if we use get_kvmclock_ns() (which
6753 	 * is slightly ahead) here we risk going negative on unsigned
6754 	 * 'system_time' when 'data.clock' is very small.
6755 	 */
6756 	if (data.flags & KVM_CLOCK_REALTIME) {
6757 		u64 now_real_ns = ktime_get_real_ns();
6758 
6759 		/*
6760 		 * Avoid stepping the kvmclock backwards.
6761 		 */
6762 		if (now_real_ns > data.realtime)
6763 			data.clock += now_real_ns - data.realtime;
6764 	}
6765 
6766 	if (ka->use_master_clock)
6767 		now_raw_ns = ka->master_kernel_ns;
6768 	else
6769 		now_raw_ns = get_kvmclock_base_ns();
6770 	ka->kvmclock_offset = data.clock - now_raw_ns;
6771 	kvm_end_pvclock_update(kvm);
6772 	return 0;
6773 }
6774 
kvm_arch_vm_ioctl(struct file * filp,unsigned int ioctl,unsigned long arg)6775 int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
6776 {
6777 	struct kvm *kvm = filp->private_data;
6778 	void __user *argp = (void __user *)arg;
6779 	int r = -ENOTTY;
6780 	/*
6781 	 * This union makes it completely explicit to gcc-3.x
6782 	 * that these two variables' stack usage should be
6783 	 * combined, not added together.
6784 	 */
6785 	union {
6786 		struct kvm_pit_state ps;
6787 		struct kvm_pit_state2 ps2;
6788 		struct kvm_pit_config pit_config;
6789 	} u;
6790 
6791 	switch (ioctl) {
6792 	case KVM_SET_TSS_ADDR:
6793 		r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
6794 		break;
6795 	case KVM_SET_IDENTITY_MAP_ADDR: {
6796 		u64 ident_addr;
6797 
6798 		mutex_lock(&kvm->lock);
6799 		r = -EINVAL;
6800 		if (kvm->created_vcpus)
6801 			goto set_identity_unlock;
6802 		r = -EFAULT;
6803 		if (copy_from_user(&ident_addr, argp, sizeof(ident_addr)))
6804 			goto set_identity_unlock;
6805 		r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
6806 set_identity_unlock:
6807 		mutex_unlock(&kvm->lock);
6808 		break;
6809 	}
6810 	case KVM_SET_NR_MMU_PAGES:
6811 		r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
6812 		break;
6813 	case KVM_CREATE_IRQCHIP: {
6814 		mutex_lock(&kvm->lock);
6815 
6816 		r = -EEXIST;
6817 		if (irqchip_in_kernel(kvm))
6818 			goto create_irqchip_unlock;
6819 
6820 		r = -EINVAL;
6821 		if (kvm->created_vcpus)
6822 			goto create_irqchip_unlock;
6823 
6824 		r = kvm_pic_init(kvm);
6825 		if (r)
6826 			goto create_irqchip_unlock;
6827 
6828 		r = kvm_ioapic_init(kvm);
6829 		if (r) {
6830 			kvm_pic_destroy(kvm);
6831 			goto create_irqchip_unlock;
6832 		}
6833 
6834 		r = kvm_setup_default_irq_routing(kvm);
6835 		if (r) {
6836 			kvm_ioapic_destroy(kvm);
6837 			kvm_pic_destroy(kvm);
6838 			goto create_irqchip_unlock;
6839 		}
6840 		/* Write kvm->irq_routing before enabling irqchip_in_kernel. */
6841 		smp_wmb();
6842 		kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
6843 		kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_ABSENT);
6844 	create_irqchip_unlock:
6845 		mutex_unlock(&kvm->lock);
6846 		break;
6847 	}
6848 	case KVM_CREATE_PIT:
6849 		u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
6850 		goto create_pit;
6851 	case KVM_CREATE_PIT2:
6852 		r = -EFAULT;
6853 		if (copy_from_user(&u.pit_config, argp,
6854 				   sizeof(struct kvm_pit_config)))
6855 			goto out;
6856 	create_pit:
6857 		mutex_lock(&kvm->lock);
6858 		r = -EEXIST;
6859 		if (kvm->arch.vpit)
6860 			goto create_pit_unlock;
6861 		r = -ENOMEM;
6862 		kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
6863 		if (kvm->arch.vpit)
6864 			r = 0;
6865 	create_pit_unlock:
6866 		mutex_unlock(&kvm->lock);
6867 		break;
6868 	case KVM_GET_IRQCHIP: {
6869 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6870 		struct kvm_irqchip *chip;
6871 
6872 		chip = memdup_user(argp, sizeof(*chip));
6873 		if (IS_ERR(chip)) {
6874 			r = PTR_ERR(chip);
6875 			goto out;
6876 		}
6877 
6878 		r = -ENXIO;
6879 		if (!irqchip_kernel(kvm))
6880 			goto get_irqchip_out;
6881 		r = kvm_vm_ioctl_get_irqchip(kvm, chip);
6882 		if (r)
6883 			goto get_irqchip_out;
6884 		r = -EFAULT;
6885 		if (copy_to_user(argp, chip, sizeof(*chip)))
6886 			goto get_irqchip_out;
6887 		r = 0;
6888 	get_irqchip_out:
6889 		kfree(chip);
6890 		break;
6891 	}
6892 	case KVM_SET_IRQCHIP: {
6893 		/* 0: PIC master, 1: PIC slave, 2: IOAPIC */
6894 		struct kvm_irqchip *chip;
6895 
6896 		chip = memdup_user(argp, sizeof(*chip));
6897 		if (IS_ERR(chip)) {
6898 			r = PTR_ERR(chip);
6899 			goto out;
6900 		}
6901 
6902 		r = -ENXIO;
6903 		if (!irqchip_kernel(kvm))
6904 			goto set_irqchip_out;
6905 		r = kvm_vm_ioctl_set_irqchip(kvm, chip);
6906 	set_irqchip_out:
6907 		kfree(chip);
6908 		break;
6909 	}
6910 	case KVM_GET_PIT: {
6911 		r = -EFAULT;
6912 		if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
6913 			goto out;
6914 		r = -ENXIO;
6915 		if (!kvm->arch.vpit)
6916 			goto out;
6917 		r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
6918 		if (r)
6919 			goto out;
6920 		r = -EFAULT;
6921 		if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
6922 			goto out;
6923 		r = 0;
6924 		break;
6925 	}
6926 	case KVM_SET_PIT: {
6927 		r = -EFAULT;
6928 		if (copy_from_user(&u.ps, argp, sizeof(u.ps)))
6929 			goto out;
6930 		mutex_lock(&kvm->lock);
6931 		r = -ENXIO;
6932 		if (!kvm->arch.vpit)
6933 			goto set_pit_out;
6934 		r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
6935 set_pit_out:
6936 		mutex_unlock(&kvm->lock);
6937 		break;
6938 	}
6939 	case KVM_GET_PIT2: {
6940 		r = -ENXIO;
6941 		if (!kvm->arch.vpit)
6942 			goto out;
6943 		r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
6944 		if (r)
6945 			goto out;
6946 		r = -EFAULT;
6947 		if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
6948 			goto out;
6949 		r = 0;
6950 		break;
6951 	}
6952 	case KVM_SET_PIT2: {
6953 		r = -EFAULT;
6954 		if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
6955 			goto out;
6956 		mutex_lock(&kvm->lock);
6957 		r = -ENXIO;
6958 		if (!kvm->arch.vpit)
6959 			goto set_pit2_out;
6960 		r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
6961 set_pit2_out:
6962 		mutex_unlock(&kvm->lock);
6963 		break;
6964 	}
6965 	case KVM_REINJECT_CONTROL: {
6966 		struct kvm_reinject_control control;
6967 		r =  -EFAULT;
6968 		if (copy_from_user(&control, argp, sizeof(control)))
6969 			goto out;
6970 		r = -ENXIO;
6971 		if (!kvm->arch.vpit)
6972 			goto out;
6973 		r = kvm_vm_ioctl_reinject(kvm, &control);
6974 		break;
6975 	}
6976 	case KVM_SET_BOOT_CPU_ID:
6977 		r = 0;
6978 		mutex_lock(&kvm->lock);
6979 		if (kvm->created_vcpus)
6980 			r = -EBUSY;
6981 		else
6982 			kvm->arch.bsp_vcpu_id = arg;
6983 		mutex_unlock(&kvm->lock);
6984 		break;
6985 #ifdef CONFIG_KVM_XEN
6986 	case KVM_XEN_HVM_CONFIG: {
6987 		struct kvm_xen_hvm_config xhc;
6988 		r = -EFAULT;
6989 		if (copy_from_user(&xhc, argp, sizeof(xhc)))
6990 			goto out;
6991 		r = kvm_xen_hvm_config(kvm, &xhc);
6992 		break;
6993 	}
6994 	case KVM_XEN_HVM_GET_ATTR: {
6995 		struct kvm_xen_hvm_attr xha;
6996 
6997 		r = -EFAULT;
6998 		if (copy_from_user(&xha, argp, sizeof(xha)))
6999 			goto out;
7000 		r = kvm_xen_hvm_get_attr(kvm, &xha);
7001 		if (!r && copy_to_user(argp, &xha, sizeof(xha)))
7002 			r = -EFAULT;
7003 		break;
7004 	}
7005 	case KVM_XEN_HVM_SET_ATTR: {
7006 		struct kvm_xen_hvm_attr xha;
7007 
7008 		r = -EFAULT;
7009 		if (copy_from_user(&xha, argp, sizeof(xha)))
7010 			goto out;
7011 		r = kvm_xen_hvm_set_attr(kvm, &xha);
7012 		break;
7013 	}
7014 	case KVM_XEN_HVM_EVTCHN_SEND: {
7015 		struct kvm_irq_routing_xen_evtchn uxe;
7016 
7017 		r = -EFAULT;
7018 		if (copy_from_user(&uxe, argp, sizeof(uxe)))
7019 			goto out;
7020 		r = kvm_xen_hvm_evtchn_send(kvm, &uxe);
7021 		break;
7022 	}
7023 #endif
7024 	case KVM_SET_CLOCK:
7025 		r = kvm_vm_ioctl_set_clock(kvm, argp);
7026 		break;
7027 	case KVM_GET_CLOCK:
7028 		r = kvm_vm_ioctl_get_clock(kvm, argp);
7029 		break;
7030 	case KVM_SET_TSC_KHZ: {
7031 		u32 user_tsc_khz;
7032 
7033 		r = -EINVAL;
7034 		user_tsc_khz = (u32)arg;
7035 
7036 		if (kvm_caps.has_tsc_control &&
7037 		    user_tsc_khz >= kvm_caps.max_guest_tsc_khz)
7038 			goto out;
7039 
7040 		if (user_tsc_khz == 0)
7041 			user_tsc_khz = tsc_khz;
7042 
7043 		WRITE_ONCE(kvm->arch.default_tsc_khz, user_tsc_khz);
7044 		r = 0;
7045 
7046 		goto out;
7047 	}
7048 	case KVM_GET_TSC_KHZ: {
7049 		r = READ_ONCE(kvm->arch.default_tsc_khz);
7050 		goto out;
7051 	}
7052 	case KVM_MEMORY_ENCRYPT_OP: {
7053 		r = -ENOTTY;
7054 		if (!kvm_x86_ops.mem_enc_ioctl)
7055 			goto out;
7056 
7057 		r = static_call(kvm_x86_mem_enc_ioctl)(kvm, argp);
7058 		break;
7059 	}
7060 	case KVM_MEMORY_ENCRYPT_REG_REGION: {
7061 		struct kvm_enc_region region;
7062 
7063 		r = -EFAULT;
7064 		if (copy_from_user(&region, argp, sizeof(region)))
7065 			goto out;
7066 
7067 		r = -ENOTTY;
7068 		if (!kvm_x86_ops.mem_enc_register_region)
7069 			goto out;
7070 
7071 		r = static_call(kvm_x86_mem_enc_register_region)(kvm, &region);
7072 		break;
7073 	}
7074 	case KVM_MEMORY_ENCRYPT_UNREG_REGION: {
7075 		struct kvm_enc_region region;
7076 
7077 		r = -EFAULT;
7078 		if (copy_from_user(&region, argp, sizeof(region)))
7079 			goto out;
7080 
7081 		r = -ENOTTY;
7082 		if (!kvm_x86_ops.mem_enc_unregister_region)
7083 			goto out;
7084 
7085 		r = static_call(kvm_x86_mem_enc_unregister_region)(kvm, &region);
7086 		break;
7087 	}
7088 	case KVM_HYPERV_EVENTFD: {
7089 		struct kvm_hyperv_eventfd hvevfd;
7090 
7091 		r = -EFAULT;
7092 		if (copy_from_user(&hvevfd, argp, sizeof(hvevfd)))
7093 			goto out;
7094 		r = kvm_vm_ioctl_hv_eventfd(kvm, &hvevfd);
7095 		break;
7096 	}
7097 	case KVM_SET_PMU_EVENT_FILTER:
7098 		r = kvm_vm_ioctl_set_pmu_event_filter(kvm, argp);
7099 		break;
7100 	case KVM_X86_SET_MSR_FILTER: {
7101 		struct kvm_msr_filter __user *user_msr_filter = argp;
7102 		struct kvm_msr_filter filter;
7103 
7104 		if (copy_from_user(&filter, user_msr_filter, sizeof(filter)))
7105 			return -EFAULT;
7106 
7107 		r = kvm_vm_ioctl_set_msr_filter(kvm, &filter);
7108 		break;
7109 	}
7110 	default:
7111 		r = -ENOTTY;
7112 	}
7113 out:
7114 	return r;
7115 }
7116 
kvm_probe_feature_msr(u32 msr_index)7117 static void kvm_probe_feature_msr(u32 msr_index)
7118 {
7119 	struct kvm_msr_entry msr = {
7120 		.index = msr_index,
7121 	};
7122 
7123 	if (kvm_get_msr_feature(&msr))
7124 		return;
7125 
7126 	msr_based_features[num_msr_based_features++] = msr_index;
7127 }
7128 
kvm_probe_msr_to_save(u32 msr_index)7129 static void kvm_probe_msr_to_save(u32 msr_index)
7130 {
7131 	u32 dummy[2];
7132 
7133 	if (rdmsr_safe(msr_index, &dummy[0], &dummy[1]))
7134 		return;
7135 
7136 	/*
7137 	 * Even MSRs that are valid in the host may not be exposed to guests in
7138 	 * some cases.
7139 	 */
7140 	switch (msr_index) {
7141 	case MSR_IA32_BNDCFGS:
7142 		if (!kvm_mpx_supported())
7143 			return;
7144 		break;
7145 	case MSR_TSC_AUX:
7146 		if (!kvm_cpu_cap_has(X86_FEATURE_RDTSCP) &&
7147 		    !kvm_cpu_cap_has(X86_FEATURE_RDPID))
7148 			return;
7149 		break;
7150 	case MSR_IA32_UMWAIT_CONTROL:
7151 		if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG))
7152 			return;
7153 		break;
7154 	case MSR_IA32_RTIT_CTL:
7155 	case MSR_IA32_RTIT_STATUS:
7156 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT))
7157 			return;
7158 		break;
7159 	case MSR_IA32_RTIT_CR3_MATCH:
7160 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7161 		    !intel_pt_validate_hw_cap(PT_CAP_cr3_filtering))
7162 			return;
7163 		break;
7164 	case MSR_IA32_RTIT_OUTPUT_BASE:
7165 	case MSR_IA32_RTIT_OUTPUT_MASK:
7166 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7167 		    (!intel_pt_validate_hw_cap(PT_CAP_topa_output) &&
7168 		     !intel_pt_validate_hw_cap(PT_CAP_single_range_output)))
7169 			return;
7170 		break;
7171 	case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
7172 		if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT) ||
7173 		    (msr_index - MSR_IA32_RTIT_ADDR0_A >=
7174 		     intel_pt_validate_hw_cap(PT_CAP_num_address_ranges) * 2))
7175 			return;
7176 		break;
7177 	case MSR_ARCH_PERFMON_PERFCTR0 ... MSR_ARCH_PERFMON_PERFCTR_MAX:
7178 		if (msr_index - MSR_ARCH_PERFMON_PERFCTR0 >=
7179 		    kvm_pmu_cap.num_counters_gp)
7180 			return;
7181 		break;
7182 	case MSR_ARCH_PERFMON_EVENTSEL0 ... MSR_ARCH_PERFMON_EVENTSEL_MAX:
7183 		if (msr_index - MSR_ARCH_PERFMON_EVENTSEL0 >=
7184 		    kvm_pmu_cap.num_counters_gp)
7185 			return;
7186 		break;
7187 	case MSR_ARCH_PERFMON_FIXED_CTR0 ... MSR_ARCH_PERFMON_FIXED_CTR_MAX:
7188 		if (msr_index - MSR_ARCH_PERFMON_FIXED_CTR0 >=
7189 		    kvm_pmu_cap.num_counters_fixed)
7190 			return;
7191 		break;
7192 	case MSR_AMD64_PERF_CNTR_GLOBAL_CTL:
7193 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
7194 	case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR:
7195 		if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2))
7196 			return;
7197 		break;
7198 	case MSR_IA32_XFD:
7199 	case MSR_IA32_XFD_ERR:
7200 		if (!kvm_cpu_cap_has(X86_FEATURE_XFD))
7201 			return;
7202 		break;
7203 	case MSR_IA32_TSX_CTRL:
7204 		if (!(kvm_get_arch_capabilities() & ARCH_CAP_TSX_CTRL_MSR))
7205 			return;
7206 		break;
7207 	default:
7208 		break;
7209 	}
7210 
7211 	msrs_to_save[num_msrs_to_save++] = msr_index;
7212 }
7213 
kvm_init_msr_lists(void)7214 static void kvm_init_msr_lists(void)
7215 {
7216 	unsigned i;
7217 
7218 	BUILD_BUG_ON_MSG(KVM_PMC_MAX_FIXED != 3,
7219 			 "Please update the fixed PMCs in msrs_to_save_pmu[]");
7220 
7221 	num_msrs_to_save = 0;
7222 	num_emulated_msrs = 0;
7223 	num_msr_based_features = 0;
7224 
7225 	for (i = 0; i < ARRAY_SIZE(msrs_to_save_base); i++)
7226 		kvm_probe_msr_to_save(msrs_to_save_base[i]);
7227 
7228 	if (enable_pmu) {
7229 		for (i = 0; i < ARRAY_SIZE(msrs_to_save_pmu); i++)
7230 			kvm_probe_msr_to_save(msrs_to_save_pmu[i]);
7231 	}
7232 
7233 	for (i = 0; i < ARRAY_SIZE(emulated_msrs_all); i++) {
7234 		if (!static_call(kvm_x86_has_emulated_msr)(NULL, emulated_msrs_all[i]))
7235 			continue;
7236 
7237 		emulated_msrs[num_emulated_msrs++] = emulated_msrs_all[i];
7238 	}
7239 
7240 	for (i = KVM_FIRST_EMULATED_VMX_MSR; i <= KVM_LAST_EMULATED_VMX_MSR; i++)
7241 		kvm_probe_feature_msr(i);
7242 
7243 	for (i = 0; i < ARRAY_SIZE(msr_based_features_all_except_vmx); i++)
7244 		kvm_probe_feature_msr(msr_based_features_all_except_vmx[i]);
7245 }
7246 
vcpu_mmio_write(struct kvm_vcpu * vcpu,gpa_t addr,int len,const void * v)7247 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
7248 			   const void *v)
7249 {
7250 	int handled = 0;
7251 	int n;
7252 
7253 	do {
7254 		n = min(len, 8);
7255 		if (!(lapic_in_kernel(vcpu) &&
7256 		      !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
7257 		    && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
7258 			break;
7259 		handled += n;
7260 		addr += n;
7261 		len -= n;
7262 		v += n;
7263 	} while (len);
7264 
7265 	return handled;
7266 }
7267 
vcpu_mmio_read(struct kvm_vcpu * vcpu,gpa_t addr,int len,void * v)7268 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
7269 {
7270 	int handled = 0;
7271 	int n;
7272 
7273 	do {
7274 		n = min(len, 8);
7275 		if (!(lapic_in_kernel(vcpu) &&
7276 		      !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
7277 					 addr, n, v))
7278 		    && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
7279 			break;
7280 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
7281 		handled += n;
7282 		addr += n;
7283 		len -= n;
7284 		v += n;
7285 	} while (len);
7286 
7287 	return handled;
7288 }
7289 
kvm_set_segment(struct kvm_vcpu * vcpu,struct kvm_segment * var,int seg)7290 void kvm_set_segment(struct kvm_vcpu *vcpu,
7291 		     struct kvm_segment *var, int seg)
7292 {
7293 	static_call(kvm_x86_set_segment)(vcpu, var, seg);
7294 }
7295 
kvm_get_segment(struct kvm_vcpu * vcpu,struct kvm_segment * var,int seg)7296 void kvm_get_segment(struct kvm_vcpu *vcpu,
7297 		     struct kvm_segment *var, int seg)
7298 {
7299 	static_call(kvm_x86_get_segment)(vcpu, var, seg);
7300 }
7301 
translate_nested_gpa(struct kvm_vcpu * vcpu,gpa_t gpa,u64 access,struct x86_exception * exception)7302 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u64 access,
7303 			   struct x86_exception *exception)
7304 {
7305 	struct kvm_mmu *mmu = vcpu->arch.mmu;
7306 	gpa_t t_gpa;
7307 
7308 	BUG_ON(!mmu_is_nested(vcpu));
7309 
7310 	/* NPT walks are always user-walks */
7311 	access |= PFERR_USER_MASK;
7312 	t_gpa  = mmu->gva_to_gpa(vcpu, mmu, gpa, access, exception);
7313 
7314 	return t_gpa;
7315 }
7316 
kvm_mmu_gva_to_gpa_read(struct kvm_vcpu * vcpu,gva_t gva,struct x86_exception * exception)7317 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
7318 			      struct x86_exception *exception)
7319 {
7320 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7321 
7322 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7323 	return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7324 }
7325 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_read);
7326 
kvm_mmu_gva_to_gpa_write(struct kvm_vcpu * vcpu,gva_t gva,struct x86_exception * exception)7327 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
7328 			       struct x86_exception *exception)
7329 {
7330 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7331 
7332 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7333 	access |= PFERR_WRITE_MASK;
7334 	return mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7335 }
7336 EXPORT_SYMBOL_GPL(kvm_mmu_gva_to_gpa_write);
7337 
7338 /* uses this to access any guest's mapped memory without checking CPL */
kvm_mmu_gva_to_gpa_system(struct kvm_vcpu * vcpu,gva_t gva,struct x86_exception * exception)7339 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
7340 				struct x86_exception *exception)
7341 {
7342 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7343 
7344 	return mmu->gva_to_gpa(vcpu, mmu, gva, 0, exception);
7345 }
7346 
kvm_read_guest_virt_helper(gva_t addr,void * val,unsigned int bytes,struct kvm_vcpu * vcpu,u64 access,struct x86_exception * exception)7347 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7348 				      struct kvm_vcpu *vcpu, u64 access,
7349 				      struct x86_exception *exception)
7350 {
7351 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7352 	void *data = val;
7353 	int r = X86EMUL_CONTINUE;
7354 
7355 	while (bytes) {
7356 		gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7357 		unsigned offset = addr & (PAGE_SIZE-1);
7358 		unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
7359 		int ret;
7360 
7361 		if (gpa == INVALID_GPA)
7362 			return X86EMUL_PROPAGATE_FAULT;
7363 		ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
7364 					       offset, toread);
7365 		if (ret < 0) {
7366 			r = X86EMUL_IO_NEEDED;
7367 			goto out;
7368 		}
7369 
7370 		bytes -= toread;
7371 		data += toread;
7372 		addr += toread;
7373 	}
7374 out:
7375 	return r;
7376 }
7377 
7378 /* used for instruction fetching */
kvm_fetch_guest_virt(struct x86_emulate_ctxt * ctxt,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception)7379 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
7380 				gva_t addr, void *val, unsigned int bytes,
7381 				struct x86_exception *exception)
7382 {
7383 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7384 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7385 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7386 	unsigned offset;
7387 	int ret;
7388 
7389 	/* Inline kvm_read_guest_virt_helper for speed.  */
7390 	gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access|PFERR_FETCH_MASK,
7391 				    exception);
7392 	if (unlikely(gpa == INVALID_GPA))
7393 		return X86EMUL_PROPAGATE_FAULT;
7394 
7395 	offset = addr & (PAGE_SIZE-1);
7396 	if (WARN_ON(offset + bytes > PAGE_SIZE))
7397 		bytes = (unsigned)PAGE_SIZE - offset;
7398 	ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
7399 				       offset, bytes);
7400 	if (unlikely(ret < 0))
7401 		return X86EMUL_IO_NEEDED;
7402 
7403 	return X86EMUL_CONTINUE;
7404 }
7405 
kvm_read_guest_virt(struct kvm_vcpu * vcpu,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception)7406 int kvm_read_guest_virt(struct kvm_vcpu *vcpu,
7407 			       gva_t addr, void *val, unsigned int bytes,
7408 			       struct x86_exception *exception)
7409 {
7410 	u64 access = (static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0;
7411 
7412 	/*
7413 	 * FIXME: this should call handle_emulation_failure if X86EMUL_IO_NEEDED
7414 	 * is returned, but our callers are not ready for that and they blindly
7415 	 * call kvm_inject_page_fault.  Ensure that they at least do not leak
7416 	 * uninitialized kernel stack memory into cr2 and error code.
7417 	 */
7418 	memset(exception, 0, sizeof(*exception));
7419 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
7420 					  exception);
7421 }
7422 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
7423 
emulator_read_std(struct x86_emulate_ctxt * ctxt,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception,bool system)7424 static int emulator_read_std(struct x86_emulate_ctxt *ctxt,
7425 			     gva_t addr, void *val, unsigned int bytes,
7426 			     struct x86_exception *exception, bool system)
7427 {
7428 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7429 	u64 access = 0;
7430 
7431 	if (system)
7432 		access |= PFERR_IMPLICIT_ACCESS;
7433 	else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7434 		access |= PFERR_USER_MASK;
7435 
7436 	return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access, exception);
7437 }
7438 
kvm_write_guest_virt_helper(gva_t addr,void * val,unsigned int bytes,struct kvm_vcpu * vcpu,u64 access,struct x86_exception * exception)7439 static int kvm_write_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
7440 				      struct kvm_vcpu *vcpu, u64 access,
7441 				      struct x86_exception *exception)
7442 {
7443 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7444 	void *data = val;
7445 	int r = X86EMUL_CONTINUE;
7446 
7447 	while (bytes) {
7448 		gpa_t gpa = mmu->gva_to_gpa(vcpu, mmu, addr, access, exception);
7449 		unsigned offset = addr & (PAGE_SIZE-1);
7450 		unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
7451 		int ret;
7452 
7453 		if (gpa == INVALID_GPA)
7454 			return X86EMUL_PROPAGATE_FAULT;
7455 		ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
7456 		if (ret < 0) {
7457 			r = X86EMUL_IO_NEEDED;
7458 			goto out;
7459 		}
7460 
7461 		bytes -= towrite;
7462 		data += towrite;
7463 		addr += towrite;
7464 	}
7465 out:
7466 	return r;
7467 }
7468 
emulator_write_std(struct x86_emulate_ctxt * ctxt,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception,bool system)7469 static int emulator_write_std(struct x86_emulate_ctxt *ctxt, gva_t addr, void *val,
7470 			      unsigned int bytes, struct x86_exception *exception,
7471 			      bool system)
7472 {
7473 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7474 	u64 access = PFERR_WRITE_MASK;
7475 
7476 	if (system)
7477 		access |= PFERR_IMPLICIT_ACCESS;
7478 	else if (static_call(kvm_x86_get_cpl)(vcpu) == 3)
7479 		access |= PFERR_USER_MASK;
7480 
7481 	return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7482 					   access, exception);
7483 }
7484 
kvm_write_guest_virt_system(struct kvm_vcpu * vcpu,gva_t addr,void * val,unsigned int bytes,struct x86_exception * exception)7485 int kvm_write_guest_virt_system(struct kvm_vcpu *vcpu, gva_t addr, void *val,
7486 				unsigned int bytes, struct x86_exception *exception)
7487 {
7488 	/* kvm_write_guest_virt_system can pull in tons of pages. */
7489 	vcpu->arch.l1tf_flush_l1d = true;
7490 
7491 	return kvm_write_guest_virt_helper(addr, val, bytes, vcpu,
7492 					   PFERR_WRITE_MASK, exception);
7493 }
7494 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
7495 
kvm_can_emulate_insn(struct kvm_vcpu * vcpu,int emul_type,void * insn,int insn_len)7496 static int kvm_can_emulate_insn(struct kvm_vcpu *vcpu, int emul_type,
7497 				void *insn, int insn_len)
7498 {
7499 	return static_call(kvm_x86_can_emulate_instruction)(vcpu, emul_type,
7500 							    insn, insn_len);
7501 }
7502 
handle_ud(struct kvm_vcpu * vcpu)7503 int handle_ud(struct kvm_vcpu *vcpu)
7504 {
7505 	static const char kvm_emulate_prefix[] = { __KVM_EMULATE_PREFIX };
7506 	int fep_flags = READ_ONCE(force_emulation_prefix);
7507 	int emul_type = EMULTYPE_TRAP_UD;
7508 	char sig[5]; /* ud2; .ascii "kvm" */
7509 	struct x86_exception e;
7510 
7511 	if (unlikely(!kvm_can_emulate_insn(vcpu, emul_type, NULL, 0)))
7512 		return 1;
7513 
7514 	if (fep_flags &&
7515 	    kvm_read_guest_virt(vcpu, kvm_get_linear_rip(vcpu),
7516 				sig, sizeof(sig), &e) == 0 &&
7517 	    memcmp(sig, kvm_emulate_prefix, sizeof(sig)) == 0) {
7518 		if (fep_flags & KVM_FEP_CLEAR_RFLAGS_RF)
7519 			kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) & ~X86_EFLAGS_RF);
7520 		kvm_rip_write(vcpu, kvm_rip_read(vcpu) + sizeof(sig));
7521 		emul_type = EMULTYPE_TRAP_UD_FORCED;
7522 	}
7523 
7524 	return kvm_emulate_instruction(vcpu, emul_type);
7525 }
7526 EXPORT_SYMBOL_GPL(handle_ud);
7527 
vcpu_is_mmio_gpa(struct kvm_vcpu * vcpu,unsigned long gva,gpa_t gpa,bool write)7528 static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7529 			    gpa_t gpa, bool write)
7530 {
7531 	/* For APIC access vmexit */
7532 	if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7533 		return 1;
7534 
7535 	if (vcpu_match_mmio_gpa(vcpu, gpa)) {
7536 		trace_vcpu_match_mmio(gva, gpa, write, true);
7537 		return 1;
7538 	}
7539 
7540 	return 0;
7541 }
7542 
vcpu_mmio_gva_to_gpa(struct kvm_vcpu * vcpu,unsigned long gva,gpa_t * gpa,struct x86_exception * exception,bool write)7543 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
7544 				gpa_t *gpa, struct x86_exception *exception,
7545 				bool write)
7546 {
7547 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
7548 	u64 access = ((static_call(kvm_x86_get_cpl)(vcpu) == 3) ? PFERR_USER_MASK : 0)
7549 		| (write ? PFERR_WRITE_MASK : 0);
7550 
7551 	/*
7552 	 * currently PKRU is only applied to ept enabled guest so
7553 	 * there is no pkey in EPT page table for L1 guest or EPT
7554 	 * shadow page table for L2 guest.
7555 	 */
7556 	if (vcpu_match_mmio_gva(vcpu, gva) && (!is_paging(vcpu) ||
7557 	    !permission_fault(vcpu, vcpu->arch.walk_mmu,
7558 			      vcpu->arch.mmio_access, 0, access))) {
7559 		*gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
7560 					(gva & (PAGE_SIZE - 1));
7561 		trace_vcpu_match_mmio(gva, *gpa, write, false);
7562 		return 1;
7563 	}
7564 
7565 	*gpa = mmu->gva_to_gpa(vcpu, mmu, gva, access, exception);
7566 
7567 	if (*gpa == INVALID_GPA)
7568 		return -1;
7569 
7570 	return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
7571 }
7572 
emulator_write_phys(struct kvm_vcpu * vcpu,gpa_t gpa,const void * val,int bytes)7573 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
7574 			const void *val, int bytes)
7575 {
7576 	int ret;
7577 
7578 	ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
7579 	if (ret < 0)
7580 		return 0;
7581 	kvm_page_track_write(vcpu, gpa, val, bytes);
7582 	return 1;
7583 }
7584 
7585 struct read_write_emulator_ops {
7586 	int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
7587 				  int bytes);
7588 	int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
7589 				  void *val, int bytes);
7590 	int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7591 			       int bytes, void *val);
7592 	int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
7593 				    void *val, int bytes);
7594 	bool write;
7595 };
7596 
read_prepare(struct kvm_vcpu * vcpu,void * val,int bytes)7597 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
7598 {
7599 	if (vcpu->mmio_read_completed) {
7600 		trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
7601 			       vcpu->mmio_fragments[0].gpa, val);
7602 		vcpu->mmio_read_completed = 0;
7603 		return 1;
7604 	}
7605 
7606 	return 0;
7607 }
7608 
read_emulate(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7609 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7610 			void *val, int bytes)
7611 {
7612 	return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
7613 }
7614 
write_emulate(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7615 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
7616 			 void *val, int bytes)
7617 {
7618 	return emulator_write_phys(vcpu, gpa, val, bytes);
7619 }
7620 
write_mmio(struct kvm_vcpu * vcpu,gpa_t gpa,int bytes,void * val)7621 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
7622 {
7623 	trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
7624 	return vcpu_mmio_write(vcpu, gpa, bytes, val);
7625 }
7626 
read_exit_mmio(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7627 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7628 			  void *val, int bytes)
7629 {
7630 	trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
7631 	return X86EMUL_IO_NEEDED;
7632 }
7633 
write_exit_mmio(struct kvm_vcpu * vcpu,gpa_t gpa,void * val,int bytes)7634 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
7635 			   void *val, int bytes)
7636 {
7637 	struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
7638 
7639 	memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
7640 	return X86EMUL_CONTINUE;
7641 }
7642 
7643 static const struct read_write_emulator_ops read_emultor = {
7644 	.read_write_prepare = read_prepare,
7645 	.read_write_emulate = read_emulate,
7646 	.read_write_mmio = vcpu_mmio_read,
7647 	.read_write_exit_mmio = read_exit_mmio,
7648 };
7649 
7650 static const struct read_write_emulator_ops write_emultor = {
7651 	.read_write_emulate = write_emulate,
7652 	.read_write_mmio = write_mmio,
7653 	.read_write_exit_mmio = write_exit_mmio,
7654 	.write = true,
7655 };
7656 
emulator_read_write_onepage(unsigned long addr,void * val,unsigned int bytes,struct x86_exception * exception,struct kvm_vcpu * vcpu,const struct read_write_emulator_ops * ops)7657 static int emulator_read_write_onepage(unsigned long addr, void *val,
7658 				       unsigned int bytes,
7659 				       struct x86_exception *exception,
7660 				       struct kvm_vcpu *vcpu,
7661 				       const struct read_write_emulator_ops *ops)
7662 {
7663 	gpa_t gpa;
7664 	int handled, ret;
7665 	bool write = ops->write;
7666 	struct kvm_mmio_fragment *frag;
7667 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
7668 
7669 	/*
7670 	 * If the exit was due to a NPF we may already have a GPA.
7671 	 * If the GPA is present, use it to avoid the GVA to GPA table walk.
7672 	 * Note, this cannot be used on string operations since string
7673 	 * operation using rep will only have the initial GPA from the NPF
7674 	 * occurred.
7675 	 */
7676 	if (ctxt->gpa_available && emulator_can_use_gpa(ctxt) &&
7677 	    (addr & ~PAGE_MASK) == (ctxt->gpa_val & ~PAGE_MASK)) {
7678 		gpa = ctxt->gpa_val;
7679 		ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
7680 	} else {
7681 		ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
7682 		if (ret < 0)
7683 			return X86EMUL_PROPAGATE_FAULT;
7684 	}
7685 
7686 	if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
7687 		return X86EMUL_CONTINUE;
7688 
7689 	/*
7690 	 * Is this MMIO handled locally?
7691 	 */
7692 	handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
7693 	if (handled == bytes)
7694 		return X86EMUL_CONTINUE;
7695 
7696 	gpa += handled;
7697 	bytes -= handled;
7698 	val += handled;
7699 
7700 	WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
7701 	frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
7702 	frag->gpa = gpa;
7703 	frag->data = val;
7704 	frag->len = bytes;
7705 	return X86EMUL_CONTINUE;
7706 }
7707 
emulator_read_write(struct x86_emulate_ctxt * ctxt,unsigned long addr,void * val,unsigned int bytes,struct x86_exception * exception,const struct read_write_emulator_ops * ops)7708 static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
7709 			unsigned long addr,
7710 			void *val, unsigned int bytes,
7711 			struct x86_exception *exception,
7712 			const struct read_write_emulator_ops *ops)
7713 {
7714 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7715 	gpa_t gpa;
7716 	int rc;
7717 
7718 	if (ops->read_write_prepare &&
7719 		  ops->read_write_prepare(vcpu, val, bytes))
7720 		return X86EMUL_CONTINUE;
7721 
7722 	vcpu->mmio_nr_fragments = 0;
7723 
7724 	/* Crossing a page boundary? */
7725 	if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
7726 		int now;
7727 
7728 		now = -addr & ~PAGE_MASK;
7729 		rc = emulator_read_write_onepage(addr, val, now, exception,
7730 						 vcpu, ops);
7731 
7732 		if (rc != X86EMUL_CONTINUE)
7733 			return rc;
7734 		addr += now;
7735 		if (ctxt->mode != X86EMUL_MODE_PROT64)
7736 			addr = (u32)addr;
7737 		val += now;
7738 		bytes -= now;
7739 	}
7740 
7741 	rc = emulator_read_write_onepage(addr, val, bytes, exception,
7742 					 vcpu, ops);
7743 	if (rc != X86EMUL_CONTINUE)
7744 		return rc;
7745 
7746 	if (!vcpu->mmio_nr_fragments)
7747 		return rc;
7748 
7749 	gpa = vcpu->mmio_fragments[0].gpa;
7750 
7751 	vcpu->mmio_needed = 1;
7752 	vcpu->mmio_cur_fragment = 0;
7753 
7754 	vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
7755 	vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
7756 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
7757 	vcpu->run->mmio.phys_addr = gpa;
7758 
7759 	return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
7760 }
7761 
emulator_read_emulated(struct x86_emulate_ctxt * ctxt,unsigned long addr,void * val,unsigned int bytes,struct x86_exception * exception)7762 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
7763 				  unsigned long addr,
7764 				  void *val,
7765 				  unsigned int bytes,
7766 				  struct x86_exception *exception)
7767 {
7768 	return emulator_read_write(ctxt, addr, val, bytes,
7769 				   exception, &read_emultor);
7770 }
7771 
emulator_write_emulated(struct x86_emulate_ctxt * ctxt,unsigned long addr,const void * val,unsigned int bytes,struct x86_exception * exception)7772 static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
7773 			    unsigned long addr,
7774 			    const void *val,
7775 			    unsigned int bytes,
7776 			    struct x86_exception *exception)
7777 {
7778 	return emulator_read_write(ctxt, addr, (void *)val, bytes,
7779 				   exception, &write_emultor);
7780 }
7781 
7782 #define emulator_try_cmpxchg_user(t, ptr, old, new) \
7783 	(__try_cmpxchg_user((t __user *)(ptr), (t *)(old), *(t *)(new), efault ## t))
7784 
emulator_cmpxchg_emulated(struct x86_emulate_ctxt * ctxt,unsigned long addr,const void * old,const void * new,unsigned int bytes,struct x86_exception * exception)7785 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
7786 				     unsigned long addr,
7787 				     const void *old,
7788 				     const void *new,
7789 				     unsigned int bytes,
7790 				     struct x86_exception *exception)
7791 {
7792 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7793 	u64 page_line_mask;
7794 	unsigned long hva;
7795 	gpa_t gpa;
7796 	int r;
7797 
7798 	/* guests cmpxchg8b have to be emulated atomically */
7799 	if (bytes > 8 || (bytes & (bytes - 1)))
7800 		goto emul_write;
7801 
7802 	gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
7803 
7804 	if (gpa == INVALID_GPA ||
7805 	    (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
7806 		goto emul_write;
7807 
7808 	/*
7809 	 * Emulate the atomic as a straight write to avoid #AC if SLD is
7810 	 * enabled in the host and the access splits a cache line.
7811 	 */
7812 	if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
7813 		page_line_mask = ~(cache_line_size() - 1);
7814 	else
7815 		page_line_mask = PAGE_MASK;
7816 
7817 	if (((gpa + bytes - 1) & page_line_mask) != (gpa & page_line_mask))
7818 		goto emul_write;
7819 
7820 	hva = kvm_vcpu_gfn_to_hva(vcpu, gpa_to_gfn(gpa));
7821 	if (kvm_is_error_hva(hva))
7822 		goto emul_write;
7823 
7824 	hva += offset_in_page(gpa);
7825 
7826 	switch (bytes) {
7827 	case 1:
7828 		r = emulator_try_cmpxchg_user(u8, hva, old, new);
7829 		break;
7830 	case 2:
7831 		r = emulator_try_cmpxchg_user(u16, hva, old, new);
7832 		break;
7833 	case 4:
7834 		r = emulator_try_cmpxchg_user(u32, hva, old, new);
7835 		break;
7836 	case 8:
7837 		r = emulator_try_cmpxchg_user(u64, hva, old, new);
7838 		break;
7839 	default:
7840 		BUG();
7841 	}
7842 
7843 	if (r < 0)
7844 		return X86EMUL_UNHANDLEABLE;
7845 
7846 	/*
7847 	 * Mark the page dirty _before_ checking whether or not the CMPXCHG was
7848 	 * successful, as the old value is written back on failure.  Note, for
7849 	 * live migration, this is unnecessarily conservative as CMPXCHG writes
7850 	 * back the original value and the access is atomic, but KVM's ABI is
7851 	 * that all writes are dirty logged, regardless of the value written.
7852 	 */
7853 	kvm_vcpu_mark_page_dirty(vcpu, gpa_to_gfn(gpa));
7854 
7855 	if (r)
7856 		return X86EMUL_CMPXCHG_FAILED;
7857 
7858 	kvm_page_track_write(vcpu, gpa, new, bytes);
7859 
7860 	return X86EMUL_CONTINUE;
7861 
7862 emul_write:
7863 	pr_warn_once("emulating exchange as write\n");
7864 
7865 	return emulator_write_emulated(ctxt, addr, new, bytes, exception);
7866 }
7867 
emulator_pio_in_out(struct kvm_vcpu * vcpu,int size,unsigned short port,void * data,unsigned int count,bool in)7868 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
7869 			       unsigned short port, void *data,
7870 			       unsigned int count, bool in)
7871 {
7872 	unsigned i;
7873 	int r;
7874 
7875 	WARN_ON_ONCE(vcpu->arch.pio.count);
7876 	for (i = 0; i < count; i++) {
7877 		if (in)
7878 			r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, port, size, data);
7879 		else
7880 			r = kvm_io_bus_write(vcpu, KVM_PIO_BUS, port, size, data);
7881 
7882 		if (r) {
7883 			if (i == 0)
7884 				goto userspace_io;
7885 
7886 			/*
7887 			 * Userspace must have unregistered the device while PIO
7888 			 * was running.  Drop writes / read as 0.
7889 			 */
7890 			if (in)
7891 				memset(data, 0, size * (count - i));
7892 			break;
7893 		}
7894 
7895 		data += size;
7896 	}
7897 	return 1;
7898 
7899 userspace_io:
7900 	vcpu->arch.pio.port = port;
7901 	vcpu->arch.pio.in = in;
7902 	vcpu->arch.pio.count = count;
7903 	vcpu->arch.pio.size = size;
7904 
7905 	if (in)
7906 		memset(vcpu->arch.pio_data, 0, size * count);
7907 	else
7908 		memcpy(vcpu->arch.pio_data, data, size * count);
7909 
7910 	vcpu->run->exit_reason = KVM_EXIT_IO;
7911 	vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
7912 	vcpu->run->io.size = size;
7913 	vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
7914 	vcpu->run->io.count = count;
7915 	vcpu->run->io.port = port;
7916 	return 0;
7917 }
7918 
emulator_pio_in(struct kvm_vcpu * vcpu,int size,unsigned short port,void * val,unsigned int count)7919 static int emulator_pio_in(struct kvm_vcpu *vcpu, int size,
7920       			   unsigned short port, void *val, unsigned int count)
7921 {
7922 	int r = emulator_pio_in_out(vcpu, size, port, val, count, true);
7923 	if (r)
7924 		trace_kvm_pio(KVM_PIO_IN, port, size, count, val);
7925 
7926 	return r;
7927 }
7928 
complete_emulator_pio_in(struct kvm_vcpu * vcpu,void * val)7929 static void complete_emulator_pio_in(struct kvm_vcpu *vcpu, void *val)
7930 {
7931 	int size = vcpu->arch.pio.size;
7932 	unsigned int count = vcpu->arch.pio.count;
7933 	memcpy(val, vcpu->arch.pio_data, size * count);
7934 	trace_kvm_pio(KVM_PIO_IN, vcpu->arch.pio.port, size, count, vcpu->arch.pio_data);
7935 	vcpu->arch.pio.count = 0;
7936 }
7937 
emulator_pio_in_emulated(struct x86_emulate_ctxt * ctxt,int size,unsigned short port,void * val,unsigned int count)7938 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
7939 				    int size, unsigned short port, void *val,
7940 				    unsigned int count)
7941 {
7942 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
7943 	if (vcpu->arch.pio.count) {
7944 		/*
7945 		 * Complete a previous iteration that required userspace I/O.
7946 		 * Note, @count isn't guaranteed to match pio.count as userspace
7947 		 * can modify ECX before rerunning the vCPU.  Ignore any such
7948 		 * shenanigans as KVM doesn't support modifying the rep count,
7949 		 * and the emulator ensures @count doesn't overflow the buffer.
7950 		 */
7951 		complete_emulator_pio_in(vcpu, val);
7952 		return 1;
7953 	}
7954 
7955 	return emulator_pio_in(vcpu, size, port, val, count);
7956 }
7957 
emulator_pio_out(struct kvm_vcpu * vcpu,int size,unsigned short port,const void * val,unsigned int count)7958 static int emulator_pio_out(struct kvm_vcpu *vcpu, int size,
7959 			    unsigned short port, const void *val,
7960 			    unsigned int count)
7961 {
7962 	trace_kvm_pio(KVM_PIO_OUT, port, size, count, val);
7963 	return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
7964 }
7965 
emulator_pio_out_emulated(struct x86_emulate_ctxt * ctxt,int size,unsigned short port,const void * val,unsigned int count)7966 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
7967 				     int size, unsigned short port,
7968 				     const void *val, unsigned int count)
7969 {
7970 	return emulator_pio_out(emul_to_vcpu(ctxt), size, port, val, count);
7971 }
7972 
get_segment_base(struct kvm_vcpu * vcpu,int seg)7973 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
7974 {
7975 	return static_call(kvm_x86_get_segment_base)(vcpu, seg);
7976 }
7977 
emulator_invlpg(struct x86_emulate_ctxt * ctxt,ulong address)7978 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
7979 {
7980 	kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
7981 }
7982 
kvm_emulate_wbinvd_noskip(struct kvm_vcpu * vcpu)7983 static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
7984 {
7985 	if (!need_emulate_wbinvd(vcpu))
7986 		return X86EMUL_CONTINUE;
7987 
7988 	if (static_call(kvm_x86_has_wbinvd_exit)()) {
7989 		int cpu = get_cpu();
7990 
7991 		cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
7992 		on_each_cpu_mask(vcpu->arch.wbinvd_dirty_mask,
7993 				wbinvd_ipi, NULL, 1);
7994 		put_cpu();
7995 		cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
7996 	} else
7997 		wbinvd();
7998 	return X86EMUL_CONTINUE;
7999 }
8000 
kvm_emulate_wbinvd(struct kvm_vcpu * vcpu)8001 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
8002 {
8003 	kvm_emulate_wbinvd_noskip(vcpu);
8004 	return kvm_skip_emulated_instruction(vcpu);
8005 }
8006 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
8007 
8008 
8009 
emulator_wbinvd(struct x86_emulate_ctxt * ctxt)8010 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
8011 {
8012 	kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
8013 }
8014 
emulator_get_dr(struct x86_emulate_ctxt * ctxt,int dr,unsigned long * dest)8015 static void emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
8016 			    unsigned long *dest)
8017 {
8018 	kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
8019 }
8020 
emulator_set_dr(struct x86_emulate_ctxt * ctxt,int dr,unsigned long value)8021 static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
8022 			   unsigned long value)
8023 {
8024 
8025 	return kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
8026 }
8027 
mk_cr_64(u64 curr_cr,u32 new_val)8028 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
8029 {
8030 	return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
8031 }
8032 
emulator_get_cr(struct x86_emulate_ctxt * ctxt,int cr)8033 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
8034 {
8035 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8036 	unsigned long value;
8037 
8038 	switch (cr) {
8039 	case 0:
8040 		value = kvm_read_cr0(vcpu);
8041 		break;
8042 	case 2:
8043 		value = vcpu->arch.cr2;
8044 		break;
8045 	case 3:
8046 		value = kvm_read_cr3(vcpu);
8047 		break;
8048 	case 4:
8049 		value = kvm_read_cr4(vcpu);
8050 		break;
8051 	case 8:
8052 		value = kvm_get_cr8(vcpu);
8053 		break;
8054 	default:
8055 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
8056 		return 0;
8057 	}
8058 
8059 	return value;
8060 }
8061 
emulator_set_cr(struct x86_emulate_ctxt * ctxt,int cr,ulong val)8062 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
8063 {
8064 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8065 	int res = 0;
8066 
8067 	switch (cr) {
8068 	case 0:
8069 		res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
8070 		break;
8071 	case 2:
8072 		vcpu->arch.cr2 = val;
8073 		break;
8074 	case 3:
8075 		res = kvm_set_cr3(vcpu, val);
8076 		break;
8077 	case 4:
8078 		res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
8079 		break;
8080 	case 8:
8081 		res = kvm_set_cr8(vcpu, val);
8082 		break;
8083 	default:
8084 		kvm_err("%s: unexpected cr %u\n", __func__, cr);
8085 		res = -1;
8086 	}
8087 
8088 	return res;
8089 }
8090 
emulator_get_cpl(struct x86_emulate_ctxt * ctxt)8091 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
8092 {
8093 	return static_call(kvm_x86_get_cpl)(emul_to_vcpu(ctxt));
8094 }
8095 
emulator_get_gdt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8096 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8097 {
8098 	static_call(kvm_x86_get_gdt)(emul_to_vcpu(ctxt), dt);
8099 }
8100 
emulator_get_idt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8101 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8102 {
8103 	static_call(kvm_x86_get_idt)(emul_to_vcpu(ctxt), dt);
8104 }
8105 
emulator_set_gdt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8106 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8107 {
8108 	static_call(kvm_x86_set_gdt)(emul_to_vcpu(ctxt), dt);
8109 }
8110 
emulator_set_idt(struct x86_emulate_ctxt * ctxt,struct desc_ptr * dt)8111 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
8112 {
8113 	static_call(kvm_x86_set_idt)(emul_to_vcpu(ctxt), dt);
8114 }
8115 
emulator_get_cached_segment_base(struct x86_emulate_ctxt * ctxt,int seg)8116 static unsigned long emulator_get_cached_segment_base(
8117 	struct x86_emulate_ctxt *ctxt, int seg)
8118 {
8119 	return get_segment_base(emul_to_vcpu(ctxt), seg);
8120 }
8121 
emulator_get_segment(struct x86_emulate_ctxt * ctxt,u16 * selector,struct desc_struct * desc,u32 * base3,int seg)8122 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
8123 				 struct desc_struct *desc, u32 *base3,
8124 				 int seg)
8125 {
8126 	struct kvm_segment var;
8127 
8128 	kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
8129 	*selector = var.selector;
8130 
8131 	if (var.unusable) {
8132 		memset(desc, 0, sizeof(*desc));
8133 		if (base3)
8134 			*base3 = 0;
8135 		return false;
8136 	}
8137 
8138 	if (var.g)
8139 		var.limit >>= 12;
8140 	set_desc_limit(desc, var.limit);
8141 	set_desc_base(desc, (unsigned long)var.base);
8142 #ifdef CONFIG_X86_64
8143 	if (base3)
8144 		*base3 = var.base >> 32;
8145 #endif
8146 	desc->type = var.type;
8147 	desc->s = var.s;
8148 	desc->dpl = var.dpl;
8149 	desc->p = var.present;
8150 	desc->avl = var.avl;
8151 	desc->l = var.l;
8152 	desc->d = var.db;
8153 	desc->g = var.g;
8154 
8155 	return true;
8156 }
8157 
emulator_set_segment(struct x86_emulate_ctxt * ctxt,u16 selector,struct desc_struct * desc,u32 base3,int seg)8158 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
8159 				 struct desc_struct *desc, u32 base3,
8160 				 int seg)
8161 {
8162 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8163 	struct kvm_segment var;
8164 
8165 	var.selector = selector;
8166 	var.base = get_desc_base(desc);
8167 #ifdef CONFIG_X86_64
8168 	var.base |= ((u64)base3) << 32;
8169 #endif
8170 	var.limit = get_desc_limit(desc);
8171 	if (desc->g)
8172 		var.limit = (var.limit << 12) | 0xfff;
8173 	var.type = desc->type;
8174 	var.dpl = desc->dpl;
8175 	var.db = desc->d;
8176 	var.s = desc->s;
8177 	var.l = desc->l;
8178 	var.g = desc->g;
8179 	var.avl = desc->avl;
8180 	var.present = desc->p;
8181 	var.unusable = !var.present;
8182 	var.padding = 0;
8183 
8184 	kvm_set_segment(vcpu, &var, seg);
8185 	return;
8186 }
8187 
emulator_get_msr_with_filter(struct x86_emulate_ctxt * ctxt,u32 msr_index,u64 * pdata)8188 static int emulator_get_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8189 					u32 msr_index, u64 *pdata)
8190 {
8191 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8192 	int r;
8193 
8194 	r = kvm_get_msr_with_filter(vcpu, msr_index, pdata);
8195 	if (r < 0)
8196 		return X86EMUL_UNHANDLEABLE;
8197 
8198 	if (r) {
8199 		if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_RDMSR, 0,
8200 				       complete_emulated_rdmsr, r))
8201 			return X86EMUL_IO_NEEDED;
8202 
8203 		trace_kvm_msr_read_ex(msr_index);
8204 		return X86EMUL_PROPAGATE_FAULT;
8205 	}
8206 
8207 	trace_kvm_msr_read(msr_index, *pdata);
8208 	return X86EMUL_CONTINUE;
8209 }
8210 
emulator_set_msr_with_filter(struct x86_emulate_ctxt * ctxt,u32 msr_index,u64 data)8211 static int emulator_set_msr_with_filter(struct x86_emulate_ctxt *ctxt,
8212 					u32 msr_index, u64 data)
8213 {
8214 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8215 	int r;
8216 
8217 	r = kvm_set_msr_with_filter(vcpu, msr_index, data);
8218 	if (r < 0)
8219 		return X86EMUL_UNHANDLEABLE;
8220 
8221 	if (r) {
8222 		if (kvm_msr_user_space(vcpu, msr_index, KVM_EXIT_X86_WRMSR, data,
8223 				       complete_emulated_msr_access, r))
8224 			return X86EMUL_IO_NEEDED;
8225 
8226 		trace_kvm_msr_write_ex(msr_index, data);
8227 		return X86EMUL_PROPAGATE_FAULT;
8228 	}
8229 
8230 	trace_kvm_msr_write(msr_index, data);
8231 	return X86EMUL_CONTINUE;
8232 }
8233 
emulator_get_msr(struct x86_emulate_ctxt * ctxt,u32 msr_index,u64 * pdata)8234 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
8235 			    u32 msr_index, u64 *pdata)
8236 {
8237 	return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
8238 }
8239 
emulator_check_pmc(struct x86_emulate_ctxt * ctxt,u32 pmc)8240 static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
8241 			      u32 pmc)
8242 {
8243 	if (kvm_pmu_is_valid_rdpmc_ecx(emul_to_vcpu(ctxt), pmc))
8244 		return 0;
8245 	return -EINVAL;
8246 }
8247 
emulator_read_pmc(struct x86_emulate_ctxt * ctxt,u32 pmc,u64 * pdata)8248 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
8249 			     u32 pmc, u64 *pdata)
8250 {
8251 	return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
8252 }
8253 
emulator_halt(struct x86_emulate_ctxt * ctxt)8254 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
8255 {
8256 	emul_to_vcpu(ctxt)->arch.halt_request = 1;
8257 }
8258 
emulator_intercept(struct x86_emulate_ctxt * ctxt,struct x86_instruction_info * info,enum x86_intercept_stage stage)8259 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8260 			      struct x86_instruction_info *info,
8261 			      enum x86_intercept_stage stage)
8262 {
8263 	return static_call(kvm_x86_check_intercept)(emul_to_vcpu(ctxt), info, stage,
8264 					    &ctxt->exception);
8265 }
8266 
emulator_get_cpuid(struct x86_emulate_ctxt * ctxt,u32 * eax,u32 * ebx,u32 * ecx,u32 * edx,bool exact_only)8267 static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
8268 			      u32 *eax, u32 *ebx, u32 *ecx, u32 *edx,
8269 			      bool exact_only)
8270 {
8271 	return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, exact_only);
8272 }
8273 
emulator_guest_has_movbe(struct x86_emulate_ctxt * ctxt)8274 static bool emulator_guest_has_movbe(struct x86_emulate_ctxt *ctxt)
8275 {
8276 	return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_MOVBE);
8277 }
8278 
emulator_guest_has_fxsr(struct x86_emulate_ctxt * ctxt)8279 static bool emulator_guest_has_fxsr(struct x86_emulate_ctxt *ctxt)
8280 {
8281 	return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_FXSR);
8282 }
8283 
emulator_guest_has_rdpid(struct x86_emulate_ctxt * ctxt)8284 static bool emulator_guest_has_rdpid(struct x86_emulate_ctxt *ctxt)
8285 {
8286 	return guest_cpuid_has(emul_to_vcpu(ctxt), X86_FEATURE_RDPID);
8287 }
8288 
emulator_read_gpr(struct x86_emulate_ctxt * ctxt,unsigned reg)8289 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
8290 {
8291 	return kvm_register_read_raw(emul_to_vcpu(ctxt), reg);
8292 }
8293 
emulator_write_gpr(struct x86_emulate_ctxt * ctxt,unsigned reg,ulong val)8294 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
8295 {
8296 	kvm_register_write_raw(emul_to_vcpu(ctxt), reg, val);
8297 }
8298 
emulator_set_nmi_mask(struct x86_emulate_ctxt * ctxt,bool masked)8299 static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
8300 {
8301 	static_call(kvm_x86_set_nmi_mask)(emul_to_vcpu(ctxt), masked);
8302 }
8303 
emulator_is_smm(struct x86_emulate_ctxt * ctxt)8304 static bool emulator_is_smm(struct x86_emulate_ctxt *ctxt)
8305 {
8306 	return is_smm(emul_to_vcpu(ctxt));
8307 }
8308 
emulator_is_guest_mode(struct x86_emulate_ctxt * ctxt)8309 static bool emulator_is_guest_mode(struct x86_emulate_ctxt *ctxt)
8310 {
8311 	return is_guest_mode(emul_to_vcpu(ctxt));
8312 }
8313 
8314 #ifndef CONFIG_KVM_SMM
emulator_leave_smm(struct x86_emulate_ctxt * ctxt)8315 static int emulator_leave_smm(struct x86_emulate_ctxt *ctxt)
8316 {
8317 	WARN_ON_ONCE(1);
8318 	return X86EMUL_UNHANDLEABLE;
8319 }
8320 #endif
8321 
emulator_triple_fault(struct x86_emulate_ctxt * ctxt)8322 static void emulator_triple_fault(struct x86_emulate_ctxt *ctxt)
8323 {
8324 	kvm_make_request(KVM_REQ_TRIPLE_FAULT, emul_to_vcpu(ctxt));
8325 }
8326 
emulator_set_xcr(struct x86_emulate_ctxt * ctxt,u32 index,u64 xcr)8327 static int emulator_set_xcr(struct x86_emulate_ctxt *ctxt, u32 index, u64 xcr)
8328 {
8329 	return __kvm_set_xcr(emul_to_vcpu(ctxt), index, xcr);
8330 }
8331 
emulator_vm_bugged(struct x86_emulate_ctxt * ctxt)8332 static void emulator_vm_bugged(struct x86_emulate_ctxt *ctxt)
8333 {
8334 	struct kvm *kvm = emul_to_vcpu(ctxt)->kvm;
8335 
8336 	if (!kvm->vm_bugged)
8337 		kvm_vm_bugged(kvm);
8338 }
8339 
8340 static const struct x86_emulate_ops emulate_ops = {
8341 	.vm_bugged           = emulator_vm_bugged,
8342 	.read_gpr            = emulator_read_gpr,
8343 	.write_gpr           = emulator_write_gpr,
8344 	.read_std            = emulator_read_std,
8345 	.write_std           = emulator_write_std,
8346 	.fetch               = kvm_fetch_guest_virt,
8347 	.read_emulated       = emulator_read_emulated,
8348 	.write_emulated      = emulator_write_emulated,
8349 	.cmpxchg_emulated    = emulator_cmpxchg_emulated,
8350 	.invlpg              = emulator_invlpg,
8351 	.pio_in_emulated     = emulator_pio_in_emulated,
8352 	.pio_out_emulated    = emulator_pio_out_emulated,
8353 	.get_segment         = emulator_get_segment,
8354 	.set_segment         = emulator_set_segment,
8355 	.get_cached_segment_base = emulator_get_cached_segment_base,
8356 	.get_gdt             = emulator_get_gdt,
8357 	.get_idt	     = emulator_get_idt,
8358 	.set_gdt             = emulator_set_gdt,
8359 	.set_idt	     = emulator_set_idt,
8360 	.get_cr              = emulator_get_cr,
8361 	.set_cr              = emulator_set_cr,
8362 	.cpl                 = emulator_get_cpl,
8363 	.get_dr              = emulator_get_dr,
8364 	.set_dr              = emulator_set_dr,
8365 	.set_msr_with_filter = emulator_set_msr_with_filter,
8366 	.get_msr_with_filter = emulator_get_msr_with_filter,
8367 	.get_msr             = emulator_get_msr,
8368 	.check_pmc	     = emulator_check_pmc,
8369 	.read_pmc            = emulator_read_pmc,
8370 	.halt                = emulator_halt,
8371 	.wbinvd              = emulator_wbinvd,
8372 	.fix_hypercall       = emulator_fix_hypercall,
8373 	.intercept           = emulator_intercept,
8374 	.get_cpuid           = emulator_get_cpuid,
8375 	.guest_has_movbe     = emulator_guest_has_movbe,
8376 	.guest_has_fxsr      = emulator_guest_has_fxsr,
8377 	.guest_has_rdpid     = emulator_guest_has_rdpid,
8378 	.set_nmi_mask        = emulator_set_nmi_mask,
8379 	.is_smm              = emulator_is_smm,
8380 	.is_guest_mode       = emulator_is_guest_mode,
8381 	.leave_smm           = emulator_leave_smm,
8382 	.triple_fault        = emulator_triple_fault,
8383 	.set_xcr             = emulator_set_xcr,
8384 };
8385 
toggle_interruptibility(struct kvm_vcpu * vcpu,u32 mask)8386 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
8387 {
8388 	u32 int_shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8389 	/*
8390 	 * an sti; sti; sequence only disable interrupts for the first
8391 	 * instruction. So, if the last instruction, be it emulated or
8392 	 * not, left the system with the INT_STI flag enabled, it
8393 	 * means that the last instruction is an sti. We should not
8394 	 * leave the flag on in this case. The same goes for mov ss
8395 	 */
8396 	if (int_shadow & mask)
8397 		mask = 0;
8398 	if (unlikely(int_shadow || mask)) {
8399 		static_call(kvm_x86_set_interrupt_shadow)(vcpu, mask);
8400 		if (!mask)
8401 			kvm_make_request(KVM_REQ_EVENT, vcpu);
8402 	}
8403 }
8404 
inject_emulated_exception(struct kvm_vcpu * vcpu)8405 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
8406 {
8407 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8408 
8409 	if (ctxt->exception.vector == PF_VECTOR)
8410 		kvm_inject_emulated_page_fault(vcpu, &ctxt->exception);
8411 	else if (ctxt->exception.error_code_valid)
8412 		kvm_queue_exception_e(vcpu, ctxt->exception.vector,
8413 				      ctxt->exception.error_code);
8414 	else
8415 		kvm_queue_exception(vcpu, ctxt->exception.vector);
8416 }
8417 
alloc_emulate_ctxt(struct kvm_vcpu * vcpu)8418 static struct x86_emulate_ctxt *alloc_emulate_ctxt(struct kvm_vcpu *vcpu)
8419 {
8420 	struct x86_emulate_ctxt *ctxt;
8421 
8422 	ctxt = kmem_cache_zalloc(x86_emulator_cache, GFP_KERNEL_ACCOUNT);
8423 	if (!ctxt) {
8424 		pr_err("failed to allocate vcpu's emulator\n");
8425 		return NULL;
8426 	}
8427 
8428 	ctxt->vcpu = vcpu;
8429 	ctxt->ops = &emulate_ops;
8430 	vcpu->arch.emulate_ctxt = ctxt;
8431 
8432 	return ctxt;
8433 }
8434 
init_emulate_ctxt(struct kvm_vcpu * vcpu)8435 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
8436 {
8437 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8438 	int cs_db, cs_l;
8439 
8440 	static_call(kvm_x86_get_cs_db_l_bits)(vcpu, &cs_db, &cs_l);
8441 
8442 	ctxt->gpa_available = false;
8443 	ctxt->eflags = kvm_get_rflags(vcpu);
8444 	ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
8445 
8446 	ctxt->eip = kvm_rip_read(vcpu);
8447 	ctxt->mode = (!is_protmode(vcpu))		? X86EMUL_MODE_REAL :
8448 		     (ctxt->eflags & X86_EFLAGS_VM)	? X86EMUL_MODE_VM86 :
8449 		     (cs_l && is_long_mode(vcpu))	? X86EMUL_MODE_PROT64 :
8450 		     cs_db				? X86EMUL_MODE_PROT32 :
8451 							  X86EMUL_MODE_PROT16;
8452 	ctxt->interruptibility = 0;
8453 	ctxt->have_exception = false;
8454 	ctxt->exception.vector = -1;
8455 	ctxt->perm_ok = false;
8456 
8457 	init_decode_cache(ctxt);
8458 	vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8459 }
8460 
kvm_inject_realmode_interrupt(struct kvm_vcpu * vcpu,int irq,int inc_eip)8461 void kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
8462 {
8463 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8464 	int ret;
8465 
8466 	init_emulate_ctxt(vcpu);
8467 
8468 	ctxt->op_bytes = 2;
8469 	ctxt->ad_bytes = 2;
8470 	ctxt->_eip = ctxt->eip + inc_eip;
8471 	ret = emulate_int_real(ctxt, irq);
8472 
8473 	if (ret != X86EMUL_CONTINUE) {
8474 		kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
8475 	} else {
8476 		ctxt->eip = ctxt->_eip;
8477 		kvm_rip_write(vcpu, ctxt->eip);
8478 		kvm_set_rflags(vcpu, ctxt->eflags);
8479 	}
8480 }
8481 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
8482 
prepare_emulation_failure_exit(struct kvm_vcpu * vcpu,u64 * data,u8 ndata,u8 * insn_bytes,u8 insn_size)8483 static void prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8484 					   u8 ndata, u8 *insn_bytes, u8 insn_size)
8485 {
8486 	struct kvm_run *run = vcpu->run;
8487 	u64 info[5];
8488 	u8 info_start;
8489 
8490 	/*
8491 	 * Zero the whole array used to retrieve the exit info, as casting to
8492 	 * u32 for select entries will leave some chunks uninitialized.
8493 	 */
8494 	memset(&info, 0, sizeof(info));
8495 
8496 	static_call(kvm_x86_get_exit_info)(vcpu, (u32 *)&info[0], &info[1],
8497 					   &info[2], (u32 *)&info[3],
8498 					   (u32 *)&info[4]);
8499 
8500 	run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8501 	run->emulation_failure.suberror = KVM_INTERNAL_ERROR_EMULATION;
8502 
8503 	/*
8504 	 * There's currently space for 13 entries, but 5 are used for the exit
8505 	 * reason and info.  Restrict to 4 to reduce the maintenance burden
8506 	 * when expanding kvm_run.emulation_failure in the future.
8507 	 */
8508 	if (WARN_ON_ONCE(ndata > 4))
8509 		ndata = 4;
8510 
8511 	/* Always include the flags as a 'data' entry. */
8512 	info_start = 1;
8513 	run->emulation_failure.flags = 0;
8514 
8515 	if (insn_size) {
8516 		BUILD_BUG_ON((sizeof(run->emulation_failure.insn_size) +
8517 			      sizeof(run->emulation_failure.insn_bytes) != 16));
8518 		info_start += 2;
8519 		run->emulation_failure.flags |=
8520 			KVM_INTERNAL_ERROR_EMULATION_FLAG_INSTRUCTION_BYTES;
8521 		run->emulation_failure.insn_size = insn_size;
8522 		memset(run->emulation_failure.insn_bytes, 0x90,
8523 		       sizeof(run->emulation_failure.insn_bytes));
8524 		memcpy(run->emulation_failure.insn_bytes, insn_bytes, insn_size);
8525 	}
8526 
8527 	memcpy(&run->internal.data[info_start], info, sizeof(info));
8528 	memcpy(&run->internal.data[info_start + ARRAY_SIZE(info)], data,
8529 	       ndata * sizeof(data[0]));
8530 
8531 	run->emulation_failure.ndata = info_start + ARRAY_SIZE(info) + ndata;
8532 }
8533 
prepare_emulation_ctxt_failure_exit(struct kvm_vcpu * vcpu)8534 static void prepare_emulation_ctxt_failure_exit(struct kvm_vcpu *vcpu)
8535 {
8536 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8537 
8538 	prepare_emulation_failure_exit(vcpu, NULL, 0, ctxt->fetch.data,
8539 				       ctxt->fetch.end - ctxt->fetch.data);
8540 }
8541 
__kvm_prepare_emulation_failure_exit(struct kvm_vcpu * vcpu,u64 * data,u8 ndata)8542 void __kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu, u64 *data,
8543 					  u8 ndata)
8544 {
8545 	prepare_emulation_failure_exit(vcpu, data, ndata, NULL, 0);
8546 }
8547 EXPORT_SYMBOL_GPL(__kvm_prepare_emulation_failure_exit);
8548 
kvm_prepare_emulation_failure_exit(struct kvm_vcpu * vcpu)8549 void kvm_prepare_emulation_failure_exit(struct kvm_vcpu *vcpu)
8550 {
8551 	__kvm_prepare_emulation_failure_exit(vcpu, NULL, 0);
8552 }
8553 EXPORT_SYMBOL_GPL(kvm_prepare_emulation_failure_exit);
8554 
handle_emulation_failure(struct kvm_vcpu * vcpu,int emulation_type)8555 static int handle_emulation_failure(struct kvm_vcpu *vcpu, int emulation_type)
8556 {
8557 	struct kvm *kvm = vcpu->kvm;
8558 
8559 	++vcpu->stat.insn_emulation_fail;
8560 	trace_kvm_emulate_insn_failed(vcpu);
8561 
8562 	if (emulation_type & EMULTYPE_VMWARE_GP) {
8563 		kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8564 		return 1;
8565 	}
8566 
8567 	if (kvm->arch.exit_on_emulation_error ||
8568 	    (emulation_type & EMULTYPE_SKIP)) {
8569 		prepare_emulation_ctxt_failure_exit(vcpu);
8570 		return 0;
8571 	}
8572 
8573 	kvm_queue_exception(vcpu, UD_VECTOR);
8574 
8575 	if (!is_guest_mode(vcpu) && static_call(kvm_x86_get_cpl)(vcpu) == 0) {
8576 		prepare_emulation_ctxt_failure_exit(vcpu);
8577 		return 0;
8578 	}
8579 
8580 	return 1;
8581 }
8582 
reexecute_instruction(struct kvm_vcpu * vcpu,gpa_t cr2_or_gpa,int emulation_type)8583 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8584 				  int emulation_type)
8585 {
8586 	gpa_t gpa = cr2_or_gpa;
8587 	kvm_pfn_t pfn;
8588 
8589 	if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8590 		return false;
8591 
8592 	if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8593 	    WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8594 		return false;
8595 
8596 	if (!vcpu->arch.mmu->root_role.direct) {
8597 		/*
8598 		 * Write permission should be allowed since only
8599 		 * write access need to be emulated.
8600 		 */
8601 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8602 
8603 		/*
8604 		 * If the mapping is invalid in guest, let cpu retry
8605 		 * it to generate fault.
8606 		 */
8607 		if (gpa == INVALID_GPA)
8608 			return true;
8609 	}
8610 
8611 	/*
8612 	 * Do not retry the unhandleable instruction if it faults on the
8613 	 * readonly host memory, otherwise it will goto a infinite loop:
8614 	 * retry instruction -> write #PF -> emulation fail -> retry
8615 	 * instruction -> ...
8616 	 */
8617 	pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
8618 
8619 	/*
8620 	 * If the instruction failed on the error pfn, it can not be fixed,
8621 	 * report the error to userspace.
8622 	 */
8623 	if (is_error_noslot_pfn(pfn))
8624 		return false;
8625 
8626 	kvm_release_pfn_clean(pfn);
8627 
8628 	/* The instructions are well-emulated on direct mmu. */
8629 	if (vcpu->arch.mmu->root_role.direct) {
8630 		unsigned int indirect_shadow_pages;
8631 
8632 		write_lock(&vcpu->kvm->mmu_lock);
8633 		indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
8634 		write_unlock(&vcpu->kvm->mmu_lock);
8635 
8636 		if (indirect_shadow_pages)
8637 			kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8638 
8639 		return true;
8640 	}
8641 
8642 	/*
8643 	 * if emulation was due to access to shadowed page table
8644 	 * and it failed try to unshadow page and re-enter the
8645 	 * guest to let CPU execute the instruction.
8646 	 */
8647 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8648 
8649 	/*
8650 	 * If the access faults on its page table, it can not
8651 	 * be fixed by unprotecting shadow page and it should
8652 	 * be reported to userspace.
8653 	 */
8654 	return !(emulation_type & EMULTYPE_WRITE_PF_TO_SP);
8655 }
8656 
retry_instruction(struct x86_emulate_ctxt * ctxt,gpa_t cr2_or_gpa,int emulation_type)8657 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
8658 			      gpa_t cr2_or_gpa,  int emulation_type)
8659 {
8660 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8661 	unsigned long last_retry_eip, last_retry_addr, gpa = cr2_or_gpa;
8662 
8663 	last_retry_eip = vcpu->arch.last_retry_eip;
8664 	last_retry_addr = vcpu->arch.last_retry_addr;
8665 
8666 	/*
8667 	 * If the emulation is caused by #PF and it is non-page_table
8668 	 * writing instruction, it means the VM-EXIT is caused by shadow
8669 	 * page protected, we can zap the shadow page and retry this
8670 	 * instruction directly.
8671 	 *
8672 	 * Note: if the guest uses a non-page-table modifying instruction
8673 	 * on the PDE that points to the instruction, then we will unmap
8674 	 * the instruction and go to an infinite loop. So, we cache the
8675 	 * last retried eip and the last fault address, if we meet the eip
8676 	 * and the address again, we can break out of the potential infinite
8677 	 * loop.
8678 	 */
8679 	vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
8680 
8681 	if (!(emulation_type & EMULTYPE_ALLOW_RETRY_PF))
8682 		return false;
8683 
8684 	if (WARN_ON_ONCE(is_guest_mode(vcpu)) ||
8685 	    WARN_ON_ONCE(!(emulation_type & EMULTYPE_PF)))
8686 		return false;
8687 
8688 	if (x86_page_table_writing_insn(ctxt))
8689 		return false;
8690 
8691 	if (ctxt->eip == last_retry_eip && last_retry_addr == cr2_or_gpa)
8692 		return false;
8693 
8694 	vcpu->arch.last_retry_eip = ctxt->eip;
8695 	vcpu->arch.last_retry_addr = cr2_or_gpa;
8696 
8697 	if (!vcpu->arch.mmu->root_role.direct)
8698 		gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2_or_gpa, NULL);
8699 
8700 	kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
8701 
8702 	return true;
8703 }
8704 
8705 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
8706 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
8707 
kvm_vcpu_check_hw_bp(unsigned long addr,u32 type,u32 dr7,unsigned long * db)8708 static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
8709 				unsigned long *db)
8710 {
8711 	u32 dr6 = 0;
8712 	int i;
8713 	u32 enable, rwlen;
8714 
8715 	enable = dr7;
8716 	rwlen = dr7 >> 16;
8717 	for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
8718 		if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
8719 			dr6 |= (1 << i);
8720 	return dr6;
8721 }
8722 
kvm_vcpu_do_singlestep(struct kvm_vcpu * vcpu)8723 static int kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu)
8724 {
8725 	struct kvm_run *kvm_run = vcpu->run;
8726 
8727 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
8728 		kvm_run->debug.arch.dr6 = DR6_BS | DR6_ACTIVE_LOW;
8729 		kvm_run->debug.arch.pc = kvm_get_linear_rip(vcpu);
8730 		kvm_run->debug.arch.exception = DB_VECTOR;
8731 		kvm_run->exit_reason = KVM_EXIT_DEBUG;
8732 		return 0;
8733 	}
8734 	kvm_queue_exception_p(vcpu, DB_VECTOR, DR6_BS);
8735 	return 1;
8736 }
8737 
kvm_skip_emulated_instruction(struct kvm_vcpu * vcpu)8738 int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
8739 {
8740 	unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
8741 	int r;
8742 
8743 	r = static_call(kvm_x86_skip_emulated_instruction)(vcpu);
8744 	if (unlikely(!r))
8745 		return 0;
8746 
8747 	kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
8748 
8749 	/*
8750 	 * rflags is the old, "raw" value of the flags.  The new value has
8751 	 * not been saved yet.
8752 	 *
8753 	 * This is correct even for TF set by the guest, because "the
8754 	 * processor will not generate this exception after the instruction
8755 	 * that sets the TF flag".
8756 	 */
8757 	if (unlikely(rflags & X86_EFLAGS_TF))
8758 		r = kvm_vcpu_do_singlestep(vcpu);
8759 	return r;
8760 }
8761 EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
8762 
kvm_is_code_breakpoint_inhibited(struct kvm_vcpu * vcpu)8763 static bool kvm_is_code_breakpoint_inhibited(struct kvm_vcpu *vcpu)
8764 {
8765 	u32 shadow;
8766 
8767 	if (kvm_get_rflags(vcpu) & X86_EFLAGS_RF)
8768 		return true;
8769 
8770 	/*
8771 	 * Intel CPUs inhibit code #DBs when MOV/POP SS blocking is active,
8772 	 * but AMD CPUs do not.  MOV/POP SS blocking is rare, check that first
8773 	 * to avoid the relatively expensive CPUID lookup.
8774 	 */
8775 	shadow = static_call(kvm_x86_get_interrupt_shadow)(vcpu);
8776 	return (shadow & KVM_X86_SHADOW_INT_MOV_SS) &&
8777 	       guest_cpuid_is_intel(vcpu);
8778 }
8779 
kvm_vcpu_check_code_breakpoint(struct kvm_vcpu * vcpu,int emulation_type,int * r)8780 static bool kvm_vcpu_check_code_breakpoint(struct kvm_vcpu *vcpu,
8781 					   int emulation_type, int *r)
8782 {
8783 	WARN_ON_ONCE(emulation_type & EMULTYPE_NO_DECODE);
8784 
8785 	/*
8786 	 * Do not check for code breakpoints if hardware has already done the
8787 	 * checks, as inferred from the emulation type.  On NO_DECODE and SKIP,
8788 	 * the instruction has passed all exception checks, and all intercepted
8789 	 * exceptions that trigger emulation have lower priority than code
8790 	 * breakpoints, i.e. the fact that the intercepted exception occurred
8791 	 * means any code breakpoints have already been serviced.
8792 	 *
8793 	 * Note, KVM needs to check for code #DBs on EMULTYPE_TRAP_UD_FORCED as
8794 	 * hardware has checked the RIP of the magic prefix, but not the RIP of
8795 	 * the instruction being emulated.  The intent of forced emulation is
8796 	 * to behave as if KVM intercepted the instruction without an exception
8797 	 * and without a prefix.
8798 	 */
8799 	if (emulation_type & (EMULTYPE_NO_DECODE | EMULTYPE_SKIP |
8800 			      EMULTYPE_TRAP_UD | EMULTYPE_VMWARE_GP | EMULTYPE_PF))
8801 		return false;
8802 
8803 	if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
8804 	    (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
8805 		struct kvm_run *kvm_run = vcpu->run;
8806 		unsigned long eip = kvm_get_linear_rip(vcpu);
8807 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8808 					   vcpu->arch.guest_debug_dr7,
8809 					   vcpu->arch.eff_db);
8810 
8811 		if (dr6 != 0) {
8812 			kvm_run->debug.arch.dr6 = dr6 | DR6_ACTIVE_LOW;
8813 			kvm_run->debug.arch.pc = eip;
8814 			kvm_run->debug.arch.exception = DB_VECTOR;
8815 			kvm_run->exit_reason = KVM_EXIT_DEBUG;
8816 			*r = 0;
8817 			return true;
8818 		}
8819 	}
8820 
8821 	if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
8822 	    !kvm_is_code_breakpoint_inhibited(vcpu)) {
8823 		unsigned long eip = kvm_get_linear_rip(vcpu);
8824 		u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
8825 					   vcpu->arch.dr7,
8826 					   vcpu->arch.db);
8827 
8828 		if (dr6 != 0) {
8829 			kvm_queue_exception_p(vcpu, DB_VECTOR, dr6);
8830 			*r = 1;
8831 			return true;
8832 		}
8833 	}
8834 
8835 	return false;
8836 }
8837 
is_vmware_backdoor_opcode(struct x86_emulate_ctxt * ctxt)8838 static bool is_vmware_backdoor_opcode(struct x86_emulate_ctxt *ctxt)
8839 {
8840 	switch (ctxt->opcode_len) {
8841 	case 1:
8842 		switch (ctxt->b) {
8843 		case 0xe4:	/* IN */
8844 		case 0xe5:
8845 		case 0xec:
8846 		case 0xed:
8847 		case 0xe6:	/* OUT */
8848 		case 0xe7:
8849 		case 0xee:
8850 		case 0xef:
8851 		case 0x6c:	/* INS */
8852 		case 0x6d:
8853 		case 0x6e:	/* OUTS */
8854 		case 0x6f:
8855 			return true;
8856 		}
8857 		break;
8858 	case 2:
8859 		switch (ctxt->b) {
8860 		case 0x33:	/* RDPMC */
8861 			return true;
8862 		}
8863 		break;
8864 	}
8865 
8866 	return false;
8867 }
8868 
8869 /*
8870  * Decode an instruction for emulation.  The caller is responsible for handling
8871  * code breakpoints.  Note, manually detecting code breakpoints is unnecessary
8872  * (and wrong) when emulating on an intercepted fault-like exception[*], as
8873  * code breakpoints have higher priority and thus have already been done by
8874  * hardware.
8875  *
8876  * [*] Except #MC, which is higher priority, but KVM should never emulate in
8877  *     response to a machine check.
8878  */
x86_decode_emulated_instruction(struct kvm_vcpu * vcpu,int emulation_type,void * insn,int insn_len)8879 int x86_decode_emulated_instruction(struct kvm_vcpu *vcpu, int emulation_type,
8880 				    void *insn, int insn_len)
8881 {
8882 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8883 	int r;
8884 
8885 	init_emulate_ctxt(vcpu);
8886 
8887 	r = x86_decode_insn(ctxt, insn, insn_len, emulation_type);
8888 
8889 	trace_kvm_emulate_insn_start(vcpu);
8890 	++vcpu->stat.insn_emulation;
8891 
8892 	return r;
8893 }
8894 EXPORT_SYMBOL_GPL(x86_decode_emulated_instruction);
8895 
x86_emulate_instruction(struct kvm_vcpu * vcpu,gpa_t cr2_or_gpa,int emulation_type,void * insn,int insn_len)8896 int x86_emulate_instruction(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
8897 			    int emulation_type, void *insn, int insn_len)
8898 {
8899 	int r;
8900 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
8901 	bool writeback = true;
8902 
8903 	if (unlikely(!kvm_can_emulate_insn(vcpu, emulation_type, insn, insn_len)))
8904 		return 1;
8905 
8906 	vcpu->arch.l1tf_flush_l1d = true;
8907 
8908 	if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8909 		kvm_clear_exception_queue(vcpu);
8910 
8911 		/*
8912 		 * Return immediately if RIP hits a code breakpoint, such #DBs
8913 		 * are fault-like and are higher priority than any faults on
8914 		 * the code fetch itself.
8915 		 */
8916 		if (kvm_vcpu_check_code_breakpoint(vcpu, emulation_type, &r))
8917 			return r;
8918 
8919 		r = x86_decode_emulated_instruction(vcpu, emulation_type,
8920 						    insn, insn_len);
8921 		if (r != EMULATION_OK)  {
8922 			if ((emulation_type & EMULTYPE_TRAP_UD) ||
8923 			    (emulation_type & EMULTYPE_TRAP_UD_FORCED)) {
8924 				kvm_queue_exception(vcpu, UD_VECTOR);
8925 				return 1;
8926 			}
8927 			if (reexecute_instruction(vcpu, cr2_or_gpa,
8928 						  emulation_type))
8929 				return 1;
8930 
8931 			if (ctxt->have_exception &&
8932 			    !(emulation_type & EMULTYPE_SKIP)) {
8933 				/*
8934 				 * #UD should result in just EMULATION_FAILED, and trap-like
8935 				 * exception should not be encountered during decode.
8936 				 */
8937 				WARN_ON_ONCE(ctxt->exception.vector == UD_VECTOR ||
8938 					     exception_type(ctxt->exception.vector) == EXCPT_TRAP);
8939 				inject_emulated_exception(vcpu);
8940 				return 1;
8941 			}
8942 			return handle_emulation_failure(vcpu, emulation_type);
8943 		}
8944 	}
8945 
8946 	if ((emulation_type & EMULTYPE_VMWARE_GP) &&
8947 	    !is_vmware_backdoor_opcode(ctxt)) {
8948 		kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
8949 		return 1;
8950 	}
8951 
8952 	/*
8953 	 * EMULTYPE_SKIP without EMULTYPE_COMPLETE_USER_EXIT is intended for
8954 	 * use *only* by vendor callbacks for kvm_skip_emulated_instruction().
8955 	 * The caller is responsible for updating interruptibility state and
8956 	 * injecting single-step #DBs.
8957 	 */
8958 	if (emulation_type & EMULTYPE_SKIP) {
8959 		if (ctxt->mode != X86EMUL_MODE_PROT64)
8960 			ctxt->eip = (u32)ctxt->_eip;
8961 		else
8962 			ctxt->eip = ctxt->_eip;
8963 
8964 		if (emulation_type & EMULTYPE_COMPLETE_USER_EXIT) {
8965 			r = 1;
8966 			goto writeback;
8967 		}
8968 
8969 		kvm_rip_write(vcpu, ctxt->eip);
8970 		if (ctxt->eflags & X86_EFLAGS_RF)
8971 			kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
8972 		return 1;
8973 	}
8974 
8975 	if (retry_instruction(ctxt, cr2_or_gpa, emulation_type))
8976 		return 1;
8977 
8978 	/* this is needed for vmware backdoor interface to work since it
8979 	   changes registers values  during IO operation */
8980 	if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
8981 		vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8982 		emulator_invalidate_register_cache(ctxt);
8983 	}
8984 
8985 restart:
8986 	if (emulation_type & EMULTYPE_PF) {
8987 		/* Save the faulting GPA (cr2) in the address field */
8988 		ctxt->exception.address = cr2_or_gpa;
8989 
8990 		/* With shadow page tables, cr2 contains a GVA or nGPA. */
8991 		if (vcpu->arch.mmu->root_role.direct) {
8992 			ctxt->gpa_available = true;
8993 			ctxt->gpa_val = cr2_or_gpa;
8994 		}
8995 	} else {
8996 		/* Sanitize the address out of an abundance of paranoia. */
8997 		ctxt->exception.address = 0;
8998 	}
8999 
9000 	r = x86_emulate_insn(ctxt);
9001 
9002 	if (r == EMULATION_INTERCEPTED)
9003 		return 1;
9004 
9005 	if (r == EMULATION_FAILED) {
9006 		if (reexecute_instruction(vcpu, cr2_or_gpa, emulation_type))
9007 			return 1;
9008 
9009 		return handle_emulation_failure(vcpu, emulation_type);
9010 	}
9011 
9012 	if (ctxt->have_exception) {
9013 		WARN_ON_ONCE(vcpu->mmio_needed && !vcpu->mmio_is_write);
9014 		vcpu->mmio_needed = false;
9015 		r = 1;
9016 		inject_emulated_exception(vcpu);
9017 	} else if (vcpu->arch.pio.count) {
9018 		if (!vcpu->arch.pio.in) {
9019 			/* FIXME: return into emulator if single-stepping.  */
9020 			vcpu->arch.pio.count = 0;
9021 		} else {
9022 			writeback = false;
9023 			vcpu->arch.complete_userspace_io = complete_emulated_pio;
9024 		}
9025 		r = 0;
9026 	} else if (vcpu->mmio_needed) {
9027 		++vcpu->stat.mmio_exits;
9028 
9029 		if (!vcpu->mmio_is_write)
9030 			writeback = false;
9031 		r = 0;
9032 		vcpu->arch.complete_userspace_io = complete_emulated_mmio;
9033 	} else if (vcpu->arch.complete_userspace_io) {
9034 		writeback = false;
9035 		r = 0;
9036 	} else if (r == EMULATION_RESTART)
9037 		goto restart;
9038 	else
9039 		r = 1;
9040 
9041 writeback:
9042 	if (writeback) {
9043 		unsigned long rflags = static_call(kvm_x86_get_rflags)(vcpu);
9044 		toggle_interruptibility(vcpu, ctxt->interruptibility);
9045 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9046 
9047 		/*
9048 		 * Note, EXCPT_DB is assumed to be fault-like as the emulator
9049 		 * only supports code breakpoints and general detect #DB, both
9050 		 * of which are fault-like.
9051 		 */
9052 		if (!ctxt->have_exception ||
9053 		    exception_type(ctxt->exception.vector) == EXCPT_TRAP) {
9054 			kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_INSTRUCTIONS);
9055 			if (ctxt->is_branch)
9056 				kvm_pmu_trigger_event(vcpu, PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
9057 			kvm_rip_write(vcpu, ctxt->eip);
9058 			if (r && (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
9059 				r = kvm_vcpu_do_singlestep(vcpu);
9060 			static_call_cond(kvm_x86_update_emulated_instruction)(vcpu);
9061 			__kvm_set_rflags(vcpu, ctxt->eflags);
9062 		}
9063 
9064 		/*
9065 		 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
9066 		 * do nothing, and it will be requested again as soon as
9067 		 * the shadow expires.  But we still need to check here,
9068 		 * because POPF has no interrupt shadow.
9069 		 */
9070 		if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
9071 			kvm_make_request(KVM_REQ_EVENT, vcpu);
9072 	} else
9073 		vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
9074 
9075 	return r;
9076 }
9077 
kvm_emulate_instruction(struct kvm_vcpu * vcpu,int emulation_type)9078 int kvm_emulate_instruction(struct kvm_vcpu *vcpu, int emulation_type)
9079 {
9080 	return x86_emulate_instruction(vcpu, 0, emulation_type, NULL, 0);
9081 }
9082 EXPORT_SYMBOL_GPL(kvm_emulate_instruction);
9083 
kvm_emulate_instruction_from_buffer(struct kvm_vcpu * vcpu,void * insn,int insn_len)9084 int kvm_emulate_instruction_from_buffer(struct kvm_vcpu *vcpu,
9085 					void *insn, int insn_len)
9086 {
9087 	return x86_emulate_instruction(vcpu, 0, 0, insn, insn_len);
9088 }
9089 EXPORT_SYMBOL_GPL(kvm_emulate_instruction_from_buffer);
9090 
complete_fast_pio_out_port_0x7e(struct kvm_vcpu * vcpu)9091 static int complete_fast_pio_out_port_0x7e(struct kvm_vcpu *vcpu)
9092 {
9093 	vcpu->arch.pio.count = 0;
9094 	return 1;
9095 }
9096 
complete_fast_pio_out(struct kvm_vcpu * vcpu)9097 static int complete_fast_pio_out(struct kvm_vcpu *vcpu)
9098 {
9099 	vcpu->arch.pio.count = 0;
9100 
9101 	if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip)))
9102 		return 1;
9103 
9104 	return kvm_skip_emulated_instruction(vcpu);
9105 }
9106 
kvm_fast_pio_out(struct kvm_vcpu * vcpu,int size,unsigned short port)9107 static int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size,
9108 			    unsigned short port)
9109 {
9110 	unsigned long val = kvm_rax_read(vcpu);
9111 	int ret = emulator_pio_out(vcpu, size, port, &val, 1);
9112 
9113 	if (ret)
9114 		return ret;
9115 
9116 	/*
9117 	 * Workaround userspace that relies on old KVM behavior of %rip being
9118 	 * incremented prior to exiting to userspace to handle "OUT 0x7e".
9119 	 */
9120 	if (port == 0x7e &&
9121 	    kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_OUT_7E_INC_RIP)) {
9122 		vcpu->arch.complete_userspace_io =
9123 			complete_fast_pio_out_port_0x7e;
9124 		kvm_skip_emulated_instruction(vcpu);
9125 	} else {
9126 		vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9127 		vcpu->arch.complete_userspace_io = complete_fast_pio_out;
9128 	}
9129 	return 0;
9130 }
9131 
complete_fast_pio_in(struct kvm_vcpu * vcpu)9132 static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
9133 {
9134 	unsigned long val;
9135 
9136 	/* We should only ever be called with arch.pio.count equal to 1 */
9137 	BUG_ON(vcpu->arch.pio.count != 1);
9138 
9139 	if (unlikely(!kvm_is_linear_rip(vcpu, vcpu->arch.pio.linear_rip))) {
9140 		vcpu->arch.pio.count = 0;
9141 		return 1;
9142 	}
9143 
9144 	/* For size less than 4 we merge, else we zero extend */
9145 	val = (vcpu->arch.pio.size < 4) ? kvm_rax_read(vcpu) : 0;
9146 
9147 	complete_emulator_pio_in(vcpu, &val);
9148 	kvm_rax_write(vcpu, val);
9149 
9150 	return kvm_skip_emulated_instruction(vcpu);
9151 }
9152 
kvm_fast_pio_in(struct kvm_vcpu * vcpu,int size,unsigned short port)9153 static int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size,
9154 			   unsigned short port)
9155 {
9156 	unsigned long val;
9157 	int ret;
9158 
9159 	/* For size less than 4 we merge, else we zero extend */
9160 	val = (size < 4) ? kvm_rax_read(vcpu) : 0;
9161 
9162 	ret = emulator_pio_in(vcpu, size, port, &val, 1);
9163 	if (ret) {
9164 		kvm_rax_write(vcpu, val);
9165 		return ret;
9166 	}
9167 
9168 	vcpu->arch.pio.linear_rip = kvm_get_linear_rip(vcpu);
9169 	vcpu->arch.complete_userspace_io = complete_fast_pio_in;
9170 
9171 	return 0;
9172 }
9173 
kvm_fast_pio(struct kvm_vcpu * vcpu,int size,unsigned short port,int in)9174 int kvm_fast_pio(struct kvm_vcpu *vcpu, int size, unsigned short port, int in)
9175 {
9176 	int ret;
9177 
9178 	if (in)
9179 		ret = kvm_fast_pio_in(vcpu, size, port);
9180 	else
9181 		ret = kvm_fast_pio_out(vcpu, size, port);
9182 	return ret && kvm_skip_emulated_instruction(vcpu);
9183 }
9184 EXPORT_SYMBOL_GPL(kvm_fast_pio);
9185 
kvmclock_cpu_down_prep(unsigned int cpu)9186 static int kvmclock_cpu_down_prep(unsigned int cpu)
9187 {
9188 	__this_cpu_write(cpu_tsc_khz, 0);
9189 	return 0;
9190 }
9191 
tsc_khz_changed(void * data)9192 static void tsc_khz_changed(void *data)
9193 {
9194 	struct cpufreq_freqs *freq = data;
9195 	unsigned long khz;
9196 
9197 	WARN_ON_ONCE(boot_cpu_has(X86_FEATURE_CONSTANT_TSC));
9198 
9199 	if (data)
9200 		khz = freq->new;
9201 	else
9202 		khz = cpufreq_quick_get(raw_smp_processor_id());
9203 	if (!khz)
9204 		khz = tsc_khz;
9205 	__this_cpu_write(cpu_tsc_khz, khz);
9206 }
9207 
9208 #ifdef CONFIG_X86_64
kvm_hyperv_tsc_notifier(void)9209 static void kvm_hyperv_tsc_notifier(void)
9210 {
9211 	struct kvm *kvm;
9212 	int cpu;
9213 
9214 	mutex_lock(&kvm_lock);
9215 	list_for_each_entry(kvm, &vm_list, vm_list)
9216 		kvm_make_mclock_inprogress_request(kvm);
9217 
9218 	/* no guest entries from this point */
9219 	hyperv_stop_tsc_emulation();
9220 
9221 	/* TSC frequency always matches when on Hyper-V */
9222 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9223 		for_each_present_cpu(cpu)
9224 			per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
9225 	}
9226 	kvm_caps.max_guest_tsc_khz = tsc_khz;
9227 
9228 	list_for_each_entry(kvm, &vm_list, vm_list) {
9229 		__kvm_start_pvclock_update(kvm);
9230 		pvclock_update_vm_gtod_copy(kvm);
9231 		kvm_end_pvclock_update(kvm);
9232 	}
9233 
9234 	mutex_unlock(&kvm_lock);
9235 }
9236 #endif
9237 
__kvmclock_cpufreq_notifier(struct cpufreq_freqs * freq,int cpu)9238 static void __kvmclock_cpufreq_notifier(struct cpufreq_freqs *freq, int cpu)
9239 {
9240 	struct kvm *kvm;
9241 	struct kvm_vcpu *vcpu;
9242 	int send_ipi = 0;
9243 	unsigned long i;
9244 
9245 	/*
9246 	 * We allow guests to temporarily run on slowing clocks,
9247 	 * provided we notify them after, or to run on accelerating
9248 	 * clocks, provided we notify them before.  Thus time never
9249 	 * goes backwards.
9250 	 *
9251 	 * However, we have a problem.  We can't atomically update
9252 	 * the frequency of a given CPU from this function; it is
9253 	 * merely a notifier, which can be called from any CPU.
9254 	 * Changing the TSC frequency at arbitrary points in time
9255 	 * requires a recomputation of local variables related to
9256 	 * the TSC for each VCPU.  We must flag these local variables
9257 	 * to be updated and be sure the update takes place with the
9258 	 * new frequency before any guests proceed.
9259 	 *
9260 	 * Unfortunately, the combination of hotplug CPU and frequency
9261 	 * change creates an intractable locking scenario; the order
9262 	 * of when these callouts happen is undefined with respect to
9263 	 * CPU hotplug, and they can race with each other.  As such,
9264 	 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
9265 	 * undefined; you can actually have a CPU frequency change take
9266 	 * place in between the computation of X and the setting of the
9267 	 * variable.  To protect against this problem, all updates of
9268 	 * the per_cpu tsc_khz variable are done in an interrupt
9269 	 * protected IPI, and all callers wishing to update the value
9270 	 * must wait for a synchronous IPI to complete (which is trivial
9271 	 * if the caller is on the CPU already).  This establishes the
9272 	 * necessary total order on variable updates.
9273 	 *
9274 	 * Note that because a guest time update may take place
9275 	 * anytime after the setting of the VCPU's request bit, the
9276 	 * correct TSC value must be set before the request.  However,
9277 	 * to ensure the update actually makes it to any guest which
9278 	 * starts running in hardware virtualization between the set
9279 	 * and the acquisition of the spinlock, we must also ping the
9280 	 * CPU after setting the request bit.
9281 	 *
9282 	 */
9283 
9284 	smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9285 
9286 	mutex_lock(&kvm_lock);
9287 	list_for_each_entry(kvm, &vm_list, vm_list) {
9288 		kvm_for_each_vcpu(i, vcpu, kvm) {
9289 			if (vcpu->cpu != cpu)
9290 				continue;
9291 			kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
9292 			if (vcpu->cpu != raw_smp_processor_id())
9293 				send_ipi = 1;
9294 		}
9295 	}
9296 	mutex_unlock(&kvm_lock);
9297 
9298 	if (freq->old < freq->new && send_ipi) {
9299 		/*
9300 		 * We upscale the frequency.  Must make the guest
9301 		 * doesn't see old kvmclock values while running with
9302 		 * the new frequency, otherwise we risk the guest sees
9303 		 * time go backwards.
9304 		 *
9305 		 * In case we update the frequency for another cpu
9306 		 * (which might be in guest context) send an interrupt
9307 		 * to kick the cpu out of guest context.  Next time
9308 		 * guest context is entered kvmclock will be updated,
9309 		 * so the guest will not see stale values.
9310 		 */
9311 		smp_call_function_single(cpu, tsc_khz_changed, freq, 1);
9312 	}
9313 }
9314 
kvmclock_cpufreq_notifier(struct notifier_block * nb,unsigned long val,void * data)9315 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
9316 				     void *data)
9317 {
9318 	struct cpufreq_freqs *freq = data;
9319 	int cpu;
9320 
9321 	if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
9322 		return 0;
9323 	if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
9324 		return 0;
9325 
9326 	for_each_cpu(cpu, freq->policy->cpus)
9327 		__kvmclock_cpufreq_notifier(freq, cpu);
9328 
9329 	return 0;
9330 }
9331 
9332 static struct notifier_block kvmclock_cpufreq_notifier_block = {
9333 	.notifier_call  = kvmclock_cpufreq_notifier
9334 };
9335 
kvmclock_cpu_online(unsigned int cpu)9336 static int kvmclock_cpu_online(unsigned int cpu)
9337 {
9338 	tsc_khz_changed(NULL);
9339 	return 0;
9340 }
9341 
kvm_timer_init(void)9342 static void kvm_timer_init(void)
9343 {
9344 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9345 		max_tsc_khz = tsc_khz;
9346 
9347 		if (IS_ENABLED(CONFIG_CPU_FREQ)) {
9348 			struct cpufreq_policy *policy;
9349 			int cpu;
9350 
9351 			cpu = get_cpu();
9352 			policy = cpufreq_cpu_get(cpu);
9353 			if (policy) {
9354 				if (policy->cpuinfo.max_freq)
9355 					max_tsc_khz = policy->cpuinfo.max_freq;
9356 				cpufreq_cpu_put(policy);
9357 			}
9358 			put_cpu();
9359 		}
9360 		cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
9361 					  CPUFREQ_TRANSITION_NOTIFIER);
9362 
9363 		cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
9364 				  kvmclock_cpu_online, kvmclock_cpu_down_prep);
9365 	}
9366 }
9367 
9368 #ifdef CONFIG_X86_64
pvclock_gtod_update_fn(struct work_struct * work)9369 static void pvclock_gtod_update_fn(struct work_struct *work)
9370 {
9371 	struct kvm *kvm;
9372 	struct kvm_vcpu *vcpu;
9373 	unsigned long i;
9374 
9375 	mutex_lock(&kvm_lock);
9376 	list_for_each_entry(kvm, &vm_list, vm_list)
9377 		kvm_for_each_vcpu(i, vcpu, kvm)
9378 			kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
9379 	atomic_set(&kvm_guest_has_master_clock, 0);
9380 	mutex_unlock(&kvm_lock);
9381 }
9382 
9383 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
9384 
9385 /*
9386  * Indirection to move queue_work() out of the tk_core.seq write held
9387  * region to prevent possible deadlocks against time accessors which
9388  * are invoked with work related locks held.
9389  */
pvclock_irq_work_fn(struct irq_work * w)9390 static void pvclock_irq_work_fn(struct irq_work *w)
9391 {
9392 	queue_work(system_long_wq, &pvclock_gtod_work);
9393 }
9394 
9395 static DEFINE_IRQ_WORK(pvclock_irq_work, pvclock_irq_work_fn);
9396 
9397 /*
9398  * Notification about pvclock gtod data update.
9399  */
pvclock_gtod_notify(struct notifier_block * nb,unsigned long unused,void * priv)9400 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
9401 			       void *priv)
9402 {
9403 	struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
9404 	struct timekeeper *tk = priv;
9405 
9406 	update_pvclock_gtod(tk);
9407 
9408 	/*
9409 	 * Disable master clock if host does not trust, or does not use,
9410 	 * TSC based clocksource. Delegate queue_work() to irq_work as
9411 	 * this is invoked with tk_core.seq write held.
9412 	 */
9413 	if (!gtod_is_based_on_tsc(gtod->clock.vclock_mode) &&
9414 	    atomic_read(&kvm_guest_has_master_clock) != 0)
9415 		irq_work_queue(&pvclock_irq_work);
9416 	return 0;
9417 }
9418 
9419 static struct notifier_block pvclock_gtod_notifier = {
9420 	.notifier_call = pvclock_gtod_notify,
9421 };
9422 #endif
9423 
kvm_ops_update(struct kvm_x86_init_ops * ops)9424 static inline void kvm_ops_update(struct kvm_x86_init_ops *ops)
9425 {
9426 	memcpy(&kvm_x86_ops, ops->runtime_ops, sizeof(kvm_x86_ops));
9427 
9428 #define __KVM_X86_OP(func) \
9429 	static_call_update(kvm_x86_##func, kvm_x86_ops.func);
9430 #define KVM_X86_OP(func) \
9431 	WARN_ON(!kvm_x86_ops.func); __KVM_X86_OP(func)
9432 #define KVM_X86_OP_OPTIONAL __KVM_X86_OP
9433 #define KVM_X86_OP_OPTIONAL_RET0(func) \
9434 	static_call_update(kvm_x86_##func, (void *)kvm_x86_ops.func ? : \
9435 					   (void *)__static_call_return0);
9436 #include <asm/kvm-x86-ops.h>
9437 #undef __KVM_X86_OP
9438 
9439 	kvm_pmu_ops_update(ops->pmu_ops);
9440 }
9441 
kvm_x86_check_processor_compatibility(void)9442 static int kvm_x86_check_processor_compatibility(void)
9443 {
9444 	int cpu = smp_processor_id();
9445 	struct cpuinfo_x86 *c = &cpu_data(cpu);
9446 
9447 	/*
9448 	 * Compatibility checks are done when loading KVM and when enabling
9449 	 * hardware, e.g. during CPU hotplug, to ensure all online CPUs are
9450 	 * compatible, i.e. KVM should never perform a compatibility check on
9451 	 * an offline CPU.
9452 	 */
9453 	WARN_ON(!cpu_online(cpu));
9454 
9455 	if (__cr4_reserved_bits(cpu_has, c) !=
9456 	    __cr4_reserved_bits(cpu_has, &boot_cpu_data))
9457 		return -EIO;
9458 
9459 	return static_call(kvm_x86_check_processor_compatibility)();
9460 }
9461 
kvm_x86_check_cpu_compat(void * ret)9462 static void kvm_x86_check_cpu_compat(void *ret)
9463 {
9464 	*(int *)ret = kvm_x86_check_processor_compatibility();
9465 }
9466 
__kvm_x86_vendor_init(struct kvm_x86_init_ops * ops)9467 static int __kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9468 {
9469 	u64 host_pat;
9470 	int r, cpu;
9471 
9472 	if (kvm_x86_ops.hardware_enable) {
9473 		pr_err("already loaded vendor module '%s'\n", kvm_x86_ops.name);
9474 		return -EEXIST;
9475 	}
9476 
9477 	/*
9478 	 * KVM explicitly assumes that the guest has an FPU and
9479 	 * FXSAVE/FXRSTOR. For example, the KVM_GET_FPU explicitly casts the
9480 	 * vCPU's FPU state as a fxregs_state struct.
9481 	 */
9482 	if (!boot_cpu_has(X86_FEATURE_FPU) || !boot_cpu_has(X86_FEATURE_FXSR)) {
9483 		pr_err("inadequate fpu\n");
9484 		return -EOPNOTSUPP;
9485 	}
9486 
9487 	if (IS_ENABLED(CONFIG_PREEMPT_RT) && !boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9488 		pr_err("RT requires X86_FEATURE_CONSTANT_TSC\n");
9489 		return -EOPNOTSUPP;
9490 	}
9491 
9492 	/*
9493 	 * KVM assumes that PAT entry '0' encodes WB memtype and simply zeroes
9494 	 * the PAT bits in SPTEs.  Bail if PAT[0] is programmed to something
9495 	 * other than WB.  Note, EPT doesn't utilize the PAT, but don't bother
9496 	 * with an exception.  PAT[0] is set to WB on RESET and also by the
9497 	 * kernel, i.e. failure indicates a kernel bug or broken firmware.
9498 	 */
9499 	if (rdmsrl_safe(MSR_IA32_CR_PAT, &host_pat) ||
9500 	    (host_pat & GENMASK(2, 0)) != 6) {
9501 		pr_err("host PAT[0] is not WB\n");
9502 		return -EIO;
9503 	}
9504 
9505 	x86_emulator_cache = kvm_alloc_emulator_cache();
9506 	if (!x86_emulator_cache) {
9507 		pr_err("failed to allocate cache for x86 emulator\n");
9508 		return -ENOMEM;
9509 	}
9510 
9511 	user_return_msrs = alloc_percpu(struct kvm_user_return_msrs);
9512 	if (!user_return_msrs) {
9513 		pr_err("failed to allocate percpu kvm_user_return_msrs\n");
9514 		r = -ENOMEM;
9515 		goto out_free_x86_emulator_cache;
9516 	}
9517 	kvm_nr_uret_msrs = 0;
9518 
9519 	r = kvm_mmu_vendor_module_init();
9520 	if (r)
9521 		goto out_free_percpu;
9522 
9523 	if (boot_cpu_has(X86_FEATURE_XSAVE)) {
9524 		host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
9525 		kvm_caps.supported_xcr0 = host_xcr0 & KVM_SUPPORTED_XCR0;
9526 	}
9527 
9528 	rdmsrl_safe(MSR_EFER, &host_efer);
9529 
9530 	if (boot_cpu_has(X86_FEATURE_XSAVES))
9531 		rdmsrl(MSR_IA32_XSS, host_xss);
9532 
9533 	kvm_init_pmu_capability(ops->pmu_ops);
9534 
9535 	if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
9536 		rdmsrl(MSR_IA32_ARCH_CAPABILITIES, host_arch_capabilities);
9537 
9538 	r = ops->hardware_setup();
9539 	if (r != 0)
9540 		goto out_mmu_exit;
9541 
9542 	kvm_ops_update(ops);
9543 
9544 	for_each_online_cpu(cpu) {
9545 		smp_call_function_single(cpu, kvm_x86_check_cpu_compat, &r, 1);
9546 		if (r < 0)
9547 			goto out_unwind_ops;
9548 	}
9549 
9550 	/*
9551 	 * Point of no return!  DO NOT add error paths below this point unless
9552 	 * absolutely necessary, as most operations from this point forward
9553 	 * require unwinding.
9554 	 */
9555 	kvm_timer_init();
9556 
9557 	if (pi_inject_timer == -1)
9558 		pi_inject_timer = housekeeping_enabled(HK_TYPE_TIMER);
9559 #ifdef CONFIG_X86_64
9560 	pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
9561 
9562 	if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9563 		set_hv_tscchange_cb(kvm_hyperv_tsc_notifier);
9564 #endif
9565 
9566 	kvm_register_perf_callbacks(ops->handle_intel_pt_intr);
9567 
9568 	if (!kvm_cpu_cap_has(X86_FEATURE_XSAVES))
9569 		kvm_caps.supported_xss = 0;
9570 
9571 #define __kvm_cpu_cap_has(UNUSED_, f) kvm_cpu_cap_has(f)
9572 	cr4_reserved_bits = __cr4_reserved_bits(__kvm_cpu_cap_has, UNUSED_);
9573 #undef __kvm_cpu_cap_has
9574 
9575 	if (kvm_caps.has_tsc_control) {
9576 		/*
9577 		 * Make sure the user can only configure tsc_khz values that
9578 		 * fit into a signed integer.
9579 		 * A min value is not calculated because it will always
9580 		 * be 1 on all machines.
9581 		 */
9582 		u64 max = min(0x7fffffffULL,
9583 			      __scale_tsc(kvm_caps.max_tsc_scaling_ratio, tsc_khz));
9584 		kvm_caps.max_guest_tsc_khz = max;
9585 	}
9586 	kvm_caps.default_tsc_scaling_ratio = 1ULL << kvm_caps.tsc_scaling_ratio_frac_bits;
9587 	kvm_init_msr_lists();
9588 	return 0;
9589 
9590 out_unwind_ops:
9591 	kvm_x86_ops.hardware_enable = NULL;
9592 	static_call(kvm_x86_hardware_unsetup)();
9593 out_mmu_exit:
9594 	kvm_mmu_vendor_module_exit();
9595 out_free_percpu:
9596 	free_percpu(user_return_msrs);
9597 out_free_x86_emulator_cache:
9598 	kmem_cache_destroy(x86_emulator_cache);
9599 	return r;
9600 }
9601 
kvm_x86_vendor_init(struct kvm_x86_init_ops * ops)9602 int kvm_x86_vendor_init(struct kvm_x86_init_ops *ops)
9603 {
9604 	int r;
9605 
9606 	mutex_lock(&vendor_module_lock);
9607 	r = __kvm_x86_vendor_init(ops);
9608 	mutex_unlock(&vendor_module_lock);
9609 
9610 	return r;
9611 }
9612 EXPORT_SYMBOL_GPL(kvm_x86_vendor_init);
9613 
kvm_x86_vendor_exit(void)9614 void kvm_x86_vendor_exit(void)
9615 {
9616 	kvm_unregister_perf_callbacks();
9617 
9618 #ifdef CONFIG_X86_64
9619 	if (hypervisor_is_type(X86_HYPER_MS_HYPERV))
9620 		clear_hv_tscchange_cb();
9621 #endif
9622 	kvm_lapic_exit();
9623 
9624 	if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
9625 		cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
9626 					    CPUFREQ_TRANSITION_NOTIFIER);
9627 		cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
9628 	}
9629 #ifdef CONFIG_X86_64
9630 	pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
9631 	irq_work_sync(&pvclock_irq_work);
9632 	cancel_work_sync(&pvclock_gtod_work);
9633 #endif
9634 	static_call(kvm_x86_hardware_unsetup)();
9635 	kvm_mmu_vendor_module_exit();
9636 	free_percpu(user_return_msrs);
9637 	kmem_cache_destroy(x86_emulator_cache);
9638 #ifdef CONFIG_KVM_XEN
9639 	static_key_deferred_flush(&kvm_xen_enabled);
9640 	WARN_ON(static_branch_unlikely(&kvm_xen_enabled.key));
9641 #endif
9642 	mutex_lock(&vendor_module_lock);
9643 	kvm_x86_ops.hardware_enable = NULL;
9644 	mutex_unlock(&vendor_module_lock);
9645 }
9646 EXPORT_SYMBOL_GPL(kvm_x86_vendor_exit);
9647 
__kvm_emulate_halt(struct kvm_vcpu * vcpu,int state,int reason)9648 static int __kvm_emulate_halt(struct kvm_vcpu *vcpu, int state, int reason)
9649 {
9650 	/*
9651 	 * The vCPU has halted, e.g. executed HLT.  Update the run state if the
9652 	 * local APIC is in-kernel, the run loop will detect the non-runnable
9653 	 * state and halt the vCPU.  Exit to userspace if the local APIC is
9654 	 * managed by userspace, in which case userspace is responsible for
9655 	 * handling wake events.
9656 	 */
9657 	++vcpu->stat.halt_exits;
9658 	if (lapic_in_kernel(vcpu)) {
9659 		vcpu->arch.mp_state = state;
9660 		return 1;
9661 	} else {
9662 		vcpu->run->exit_reason = reason;
9663 		return 0;
9664 	}
9665 }
9666 
kvm_emulate_halt_noskip(struct kvm_vcpu * vcpu)9667 int kvm_emulate_halt_noskip(struct kvm_vcpu *vcpu)
9668 {
9669 	return __kvm_emulate_halt(vcpu, KVM_MP_STATE_HALTED, KVM_EXIT_HLT);
9670 }
9671 EXPORT_SYMBOL_GPL(kvm_emulate_halt_noskip);
9672 
kvm_emulate_halt(struct kvm_vcpu * vcpu)9673 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
9674 {
9675 	int ret = kvm_skip_emulated_instruction(vcpu);
9676 	/*
9677 	 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
9678 	 * KVM_EXIT_DEBUG here.
9679 	 */
9680 	return kvm_emulate_halt_noskip(vcpu) && ret;
9681 }
9682 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
9683 
kvm_emulate_ap_reset_hold(struct kvm_vcpu * vcpu)9684 int kvm_emulate_ap_reset_hold(struct kvm_vcpu *vcpu)
9685 {
9686 	int ret = kvm_skip_emulated_instruction(vcpu);
9687 
9688 	return __kvm_emulate_halt(vcpu, KVM_MP_STATE_AP_RESET_HOLD,
9689 					KVM_EXIT_AP_RESET_HOLD) && ret;
9690 }
9691 EXPORT_SYMBOL_GPL(kvm_emulate_ap_reset_hold);
9692 
9693 #ifdef CONFIG_X86_64
kvm_pv_clock_pairing(struct kvm_vcpu * vcpu,gpa_t paddr,unsigned long clock_type)9694 static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
9695 			        unsigned long clock_type)
9696 {
9697 	struct kvm_clock_pairing clock_pairing;
9698 	struct timespec64 ts;
9699 	u64 cycle;
9700 	int ret;
9701 
9702 	if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
9703 		return -KVM_EOPNOTSUPP;
9704 
9705 	/*
9706 	 * When tsc is in permanent catchup mode guests won't be able to use
9707 	 * pvclock_read_retry loop to get consistent view of pvclock
9708 	 */
9709 	if (vcpu->arch.tsc_always_catchup)
9710 		return -KVM_EOPNOTSUPP;
9711 
9712 	if (!kvm_get_walltime_and_clockread(&ts, &cycle))
9713 		return -KVM_EOPNOTSUPP;
9714 
9715 	clock_pairing.sec = ts.tv_sec;
9716 	clock_pairing.nsec = ts.tv_nsec;
9717 	clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
9718 	clock_pairing.flags = 0;
9719 	memset(&clock_pairing.pad, 0, sizeof(clock_pairing.pad));
9720 
9721 	ret = 0;
9722 	if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
9723 			    sizeof(struct kvm_clock_pairing)))
9724 		ret = -KVM_EFAULT;
9725 
9726 	return ret;
9727 }
9728 #endif
9729 
9730 /*
9731  * kvm_pv_kick_cpu_op:  Kick a vcpu.
9732  *
9733  * @apicid - apicid of vcpu to be kicked.
9734  */
kvm_pv_kick_cpu_op(struct kvm * kvm,int apicid)9735 static void kvm_pv_kick_cpu_op(struct kvm *kvm, int apicid)
9736 {
9737 	/*
9738 	 * All other fields are unused for APIC_DM_REMRD, but may be consumed by
9739 	 * common code, e.g. for tracing. Defer initialization to the compiler.
9740 	 */
9741 	struct kvm_lapic_irq lapic_irq = {
9742 		.delivery_mode = APIC_DM_REMRD,
9743 		.dest_mode = APIC_DEST_PHYSICAL,
9744 		.shorthand = APIC_DEST_NOSHORT,
9745 		.dest_id = apicid,
9746 	};
9747 
9748 	kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
9749 }
9750 
kvm_apicv_activated(struct kvm * kvm)9751 bool kvm_apicv_activated(struct kvm *kvm)
9752 {
9753 	return (READ_ONCE(kvm->arch.apicv_inhibit_reasons) == 0);
9754 }
9755 EXPORT_SYMBOL_GPL(kvm_apicv_activated);
9756 
kvm_vcpu_apicv_activated(struct kvm_vcpu * vcpu)9757 bool kvm_vcpu_apicv_activated(struct kvm_vcpu *vcpu)
9758 {
9759 	ulong vm_reasons = READ_ONCE(vcpu->kvm->arch.apicv_inhibit_reasons);
9760 	ulong vcpu_reasons = static_call(kvm_x86_vcpu_get_apicv_inhibit_reasons)(vcpu);
9761 
9762 	return (vm_reasons | vcpu_reasons) == 0;
9763 }
9764 EXPORT_SYMBOL_GPL(kvm_vcpu_apicv_activated);
9765 
set_or_clear_apicv_inhibit(unsigned long * inhibits,enum kvm_apicv_inhibit reason,bool set)9766 static void set_or_clear_apicv_inhibit(unsigned long *inhibits,
9767 				       enum kvm_apicv_inhibit reason, bool set)
9768 {
9769 	if (set)
9770 		__set_bit(reason, inhibits);
9771 	else
9772 		__clear_bit(reason, inhibits);
9773 
9774 	trace_kvm_apicv_inhibit_changed(reason, set, *inhibits);
9775 }
9776 
kvm_apicv_init(struct kvm * kvm)9777 static void kvm_apicv_init(struct kvm *kvm)
9778 {
9779 	unsigned long *inhibits = &kvm->arch.apicv_inhibit_reasons;
9780 
9781 	init_rwsem(&kvm->arch.apicv_update_lock);
9782 
9783 	set_or_clear_apicv_inhibit(inhibits, APICV_INHIBIT_REASON_ABSENT, true);
9784 
9785 	if (!enable_apicv)
9786 		set_or_clear_apicv_inhibit(inhibits,
9787 					   APICV_INHIBIT_REASON_DISABLE, true);
9788 }
9789 
kvm_sched_yield(struct kvm_vcpu * vcpu,unsigned long dest_id)9790 static void kvm_sched_yield(struct kvm_vcpu *vcpu, unsigned long dest_id)
9791 {
9792 	struct kvm_vcpu *target = NULL;
9793 	struct kvm_apic_map *map;
9794 
9795 	vcpu->stat.directed_yield_attempted++;
9796 
9797 	if (single_task_running())
9798 		goto no_yield;
9799 
9800 	rcu_read_lock();
9801 	map = rcu_dereference(vcpu->kvm->arch.apic_map);
9802 
9803 	if (likely(map) && dest_id <= map->max_apic_id && map->phys_map[dest_id])
9804 		target = map->phys_map[dest_id]->vcpu;
9805 
9806 	rcu_read_unlock();
9807 
9808 	if (!target || !READ_ONCE(target->ready))
9809 		goto no_yield;
9810 
9811 	/* Ignore requests to yield to self */
9812 	if (vcpu == target)
9813 		goto no_yield;
9814 
9815 	if (kvm_vcpu_yield_to(target) <= 0)
9816 		goto no_yield;
9817 
9818 	vcpu->stat.directed_yield_successful++;
9819 
9820 no_yield:
9821 	return;
9822 }
9823 
complete_hypercall_exit(struct kvm_vcpu * vcpu)9824 static int complete_hypercall_exit(struct kvm_vcpu *vcpu)
9825 {
9826 	u64 ret = vcpu->run->hypercall.ret;
9827 
9828 	if (!is_64_bit_mode(vcpu))
9829 		ret = (u32)ret;
9830 	kvm_rax_write(vcpu, ret);
9831 	++vcpu->stat.hypercalls;
9832 	return kvm_skip_emulated_instruction(vcpu);
9833 }
9834 
kvm_emulate_hypercall(struct kvm_vcpu * vcpu)9835 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
9836 {
9837 	unsigned long nr, a0, a1, a2, a3, ret;
9838 	int op_64_bit;
9839 
9840 	if (kvm_xen_hypercall_enabled(vcpu->kvm))
9841 		return kvm_xen_hypercall(vcpu);
9842 
9843 	if (kvm_hv_hypercall_enabled(vcpu))
9844 		return kvm_hv_hypercall(vcpu);
9845 
9846 	nr = kvm_rax_read(vcpu);
9847 	a0 = kvm_rbx_read(vcpu);
9848 	a1 = kvm_rcx_read(vcpu);
9849 	a2 = kvm_rdx_read(vcpu);
9850 	a3 = kvm_rsi_read(vcpu);
9851 
9852 	trace_kvm_hypercall(nr, a0, a1, a2, a3);
9853 
9854 	op_64_bit = is_64_bit_hypercall(vcpu);
9855 	if (!op_64_bit) {
9856 		nr &= 0xFFFFFFFF;
9857 		a0 &= 0xFFFFFFFF;
9858 		a1 &= 0xFFFFFFFF;
9859 		a2 &= 0xFFFFFFFF;
9860 		a3 &= 0xFFFFFFFF;
9861 	}
9862 
9863 	if (static_call(kvm_x86_get_cpl)(vcpu) != 0) {
9864 		ret = -KVM_EPERM;
9865 		goto out;
9866 	}
9867 
9868 	ret = -KVM_ENOSYS;
9869 
9870 	switch (nr) {
9871 	case KVM_HC_VAPIC_POLL_IRQ:
9872 		ret = 0;
9873 		break;
9874 	case KVM_HC_KICK_CPU:
9875 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_UNHALT))
9876 			break;
9877 
9878 		kvm_pv_kick_cpu_op(vcpu->kvm, a1);
9879 		kvm_sched_yield(vcpu, a1);
9880 		ret = 0;
9881 		break;
9882 #ifdef CONFIG_X86_64
9883 	case KVM_HC_CLOCK_PAIRING:
9884 		ret = kvm_pv_clock_pairing(vcpu, a0, a1);
9885 		break;
9886 #endif
9887 	case KVM_HC_SEND_IPI:
9888 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SEND_IPI))
9889 			break;
9890 
9891 		ret = kvm_pv_send_ipi(vcpu->kvm, a0, a1, a2, a3, op_64_bit);
9892 		break;
9893 	case KVM_HC_SCHED_YIELD:
9894 		if (!guest_pv_has(vcpu, KVM_FEATURE_PV_SCHED_YIELD))
9895 			break;
9896 
9897 		kvm_sched_yield(vcpu, a0);
9898 		ret = 0;
9899 		break;
9900 	case KVM_HC_MAP_GPA_RANGE: {
9901 		u64 gpa = a0, npages = a1, attrs = a2;
9902 
9903 		ret = -KVM_ENOSYS;
9904 		if (!(vcpu->kvm->arch.hypercall_exit_enabled & (1 << KVM_HC_MAP_GPA_RANGE)))
9905 			break;
9906 
9907 		if (!PAGE_ALIGNED(gpa) || !npages ||
9908 		    gpa_to_gfn(gpa) + npages <= gpa_to_gfn(gpa)) {
9909 			ret = -KVM_EINVAL;
9910 			break;
9911 		}
9912 
9913 		vcpu->run->exit_reason        = KVM_EXIT_HYPERCALL;
9914 		vcpu->run->hypercall.nr       = KVM_HC_MAP_GPA_RANGE;
9915 		vcpu->run->hypercall.args[0]  = gpa;
9916 		vcpu->run->hypercall.args[1]  = npages;
9917 		vcpu->run->hypercall.args[2]  = attrs;
9918 		vcpu->run->hypercall.flags    = 0;
9919 		if (op_64_bit)
9920 			vcpu->run->hypercall.flags |= KVM_EXIT_HYPERCALL_LONG_MODE;
9921 
9922 		WARN_ON_ONCE(vcpu->run->hypercall.flags & KVM_EXIT_HYPERCALL_MBZ);
9923 		vcpu->arch.complete_userspace_io = complete_hypercall_exit;
9924 		return 0;
9925 	}
9926 	default:
9927 		ret = -KVM_ENOSYS;
9928 		break;
9929 	}
9930 out:
9931 	if (!op_64_bit)
9932 		ret = (u32)ret;
9933 	kvm_rax_write(vcpu, ret);
9934 
9935 	++vcpu->stat.hypercalls;
9936 	return kvm_skip_emulated_instruction(vcpu);
9937 }
9938 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
9939 
emulator_fix_hypercall(struct x86_emulate_ctxt * ctxt)9940 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
9941 {
9942 	struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
9943 	char instruction[3];
9944 	unsigned long rip = kvm_rip_read(vcpu);
9945 
9946 	/*
9947 	 * If the quirk is disabled, synthesize a #UD and let the guest pick up
9948 	 * the pieces.
9949 	 */
9950 	if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_FIX_HYPERCALL_INSN)) {
9951 		ctxt->exception.error_code_valid = false;
9952 		ctxt->exception.vector = UD_VECTOR;
9953 		ctxt->have_exception = true;
9954 		return X86EMUL_PROPAGATE_FAULT;
9955 	}
9956 
9957 	static_call(kvm_x86_patch_hypercall)(vcpu, instruction);
9958 
9959 	return emulator_write_emulated(ctxt, rip, instruction, 3,
9960 		&ctxt->exception);
9961 }
9962 
dm_request_for_irq_injection(struct kvm_vcpu * vcpu)9963 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
9964 {
9965 	return vcpu->run->request_interrupt_window &&
9966 		likely(!pic_in_kernel(vcpu->kvm));
9967 }
9968 
9969 /* Called within kvm->srcu read side.  */
post_kvm_run_save(struct kvm_vcpu * vcpu)9970 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
9971 {
9972 	struct kvm_run *kvm_run = vcpu->run;
9973 
9974 	kvm_run->if_flag = static_call(kvm_x86_get_if_flag)(vcpu);
9975 	kvm_run->cr8 = kvm_get_cr8(vcpu);
9976 	kvm_run->apic_base = kvm_get_apic_base(vcpu);
9977 
9978 	kvm_run->ready_for_interrupt_injection =
9979 		pic_in_kernel(vcpu->kvm) ||
9980 		kvm_vcpu_ready_for_interrupt_injection(vcpu);
9981 
9982 	if (is_smm(vcpu))
9983 		kvm_run->flags |= KVM_RUN_X86_SMM;
9984 }
9985 
update_cr8_intercept(struct kvm_vcpu * vcpu)9986 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
9987 {
9988 	int max_irr, tpr;
9989 
9990 	if (!kvm_x86_ops.update_cr8_intercept)
9991 		return;
9992 
9993 	if (!lapic_in_kernel(vcpu))
9994 		return;
9995 
9996 	if (vcpu->arch.apic->apicv_active)
9997 		return;
9998 
9999 	if (!vcpu->arch.apic->vapic_addr)
10000 		max_irr = kvm_lapic_find_highest_irr(vcpu);
10001 	else
10002 		max_irr = -1;
10003 
10004 	if (max_irr != -1)
10005 		max_irr >>= 4;
10006 
10007 	tpr = kvm_lapic_get_cr8(vcpu);
10008 
10009 	static_call(kvm_x86_update_cr8_intercept)(vcpu, tpr, max_irr);
10010 }
10011 
10012 
kvm_check_nested_events(struct kvm_vcpu * vcpu)10013 int kvm_check_nested_events(struct kvm_vcpu *vcpu)
10014 {
10015 	if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10016 		kvm_x86_ops.nested_ops->triple_fault(vcpu);
10017 		return 1;
10018 	}
10019 
10020 	return kvm_x86_ops.nested_ops->check_events(vcpu);
10021 }
10022 
kvm_inject_exception(struct kvm_vcpu * vcpu)10023 static void kvm_inject_exception(struct kvm_vcpu *vcpu)
10024 {
10025 	/*
10026 	 * Suppress the error code if the vCPU is in Real Mode, as Real Mode
10027 	 * exceptions don't report error codes.  The presence of an error code
10028 	 * is carried with the exception and only stripped when the exception
10029 	 * is injected as intercepted #PF VM-Exits for AMD's Paged Real Mode do
10030 	 * report an error code despite the CPU being in Real Mode.
10031 	 */
10032 	vcpu->arch.exception.has_error_code &= is_protmode(vcpu);
10033 
10034 	trace_kvm_inj_exception(vcpu->arch.exception.vector,
10035 				vcpu->arch.exception.has_error_code,
10036 				vcpu->arch.exception.error_code,
10037 				vcpu->arch.exception.injected);
10038 
10039 	static_call(kvm_x86_inject_exception)(vcpu);
10040 }
10041 
10042 /*
10043  * Check for any event (interrupt or exception) that is ready to be injected,
10044  * and if there is at least one event, inject the event with the highest
10045  * priority.  This handles both "pending" events, i.e. events that have never
10046  * been injected into the guest, and "injected" events, i.e. events that were
10047  * injected as part of a previous VM-Enter, but weren't successfully delivered
10048  * and need to be re-injected.
10049  *
10050  * Note, this is not guaranteed to be invoked on a guest instruction boundary,
10051  * i.e. doesn't guarantee that there's an event window in the guest.  KVM must
10052  * be able to inject exceptions in the "middle" of an instruction, and so must
10053  * also be able to re-inject NMIs and IRQs in the middle of an instruction.
10054  * I.e. for exceptions and re-injected events, NOT invoking this on instruction
10055  * boundaries is necessary and correct.
10056  *
10057  * For simplicity, KVM uses a single path to inject all events (except events
10058  * that are injected directly from L1 to L2) and doesn't explicitly track
10059  * instruction boundaries for asynchronous events.  However, because VM-Exits
10060  * that can occur during instruction execution typically result in KVM skipping
10061  * the instruction or injecting an exception, e.g. instruction and exception
10062  * intercepts, and because pending exceptions have higher priority than pending
10063  * interrupts, KVM still honors instruction boundaries in most scenarios.
10064  *
10065  * But, if a VM-Exit occurs during instruction execution, and KVM does NOT skip
10066  * the instruction or inject an exception, then KVM can incorrecty inject a new
10067  * asynchrounous event if the event became pending after the CPU fetched the
10068  * instruction (in the guest).  E.g. if a page fault (#PF, #NPF, EPT violation)
10069  * occurs and is resolved by KVM, a coincident NMI, SMI, IRQ, etc... can be
10070  * injected on the restarted instruction instead of being deferred until the
10071  * instruction completes.
10072  *
10073  * In practice, this virtualization hole is unlikely to be observed by the
10074  * guest, and even less likely to cause functional problems.  To detect the
10075  * hole, the guest would have to trigger an event on a side effect of an early
10076  * phase of instruction execution, e.g. on the instruction fetch from memory.
10077  * And for it to be a functional problem, the guest would need to depend on the
10078  * ordering between that side effect, the instruction completing, _and_ the
10079  * delivery of the asynchronous event.
10080  */
kvm_check_and_inject_events(struct kvm_vcpu * vcpu,bool * req_immediate_exit)10081 static int kvm_check_and_inject_events(struct kvm_vcpu *vcpu,
10082 				       bool *req_immediate_exit)
10083 {
10084 	bool can_inject;
10085 	int r;
10086 
10087 	/*
10088 	 * Process nested events first, as nested VM-Exit supercedes event
10089 	 * re-injection.  If there's an event queued for re-injection, it will
10090 	 * be saved into the appropriate vmc{b,s}12 fields on nested VM-Exit.
10091 	 */
10092 	if (is_guest_mode(vcpu))
10093 		r = kvm_check_nested_events(vcpu);
10094 	else
10095 		r = 0;
10096 
10097 	/*
10098 	 * Re-inject exceptions and events *especially* if immediate entry+exit
10099 	 * to/from L2 is needed, as any event that has already been injected
10100 	 * into L2 needs to complete its lifecycle before injecting a new event.
10101 	 *
10102 	 * Don't re-inject an NMI or interrupt if there is a pending exception.
10103 	 * This collision arises if an exception occurred while vectoring the
10104 	 * injected event, KVM intercepted said exception, and KVM ultimately
10105 	 * determined the fault belongs to the guest and queues the exception
10106 	 * for injection back into the guest.
10107 	 *
10108 	 * "Injected" interrupts can also collide with pending exceptions if
10109 	 * userspace ignores the "ready for injection" flag and blindly queues
10110 	 * an interrupt.  In that case, prioritizing the exception is correct,
10111 	 * as the exception "occurred" before the exit to userspace.  Trap-like
10112 	 * exceptions, e.g. most #DBs, have higher priority than interrupts.
10113 	 * And while fault-like exceptions, e.g. #GP and #PF, are the lowest
10114 	 * priority, they're only generated (pended) during instruction
10115 	 * execution, and interrupts are recognized at instruction boundaries.
10116 	 * Thus a pending fault-like exception means the fault occurred on the
10117 	 * *previous* instruction and must be serviced prior to recognizing any
10118 	 * new events in order to fully complete the previous instruction.
10119 	 */
10120 	if (vcpu->arch.exception.injected)
10121 		kvm_inject_exception(vcpu);
10122 	else if (kvm_is_exception_pending(vcpu))
10123 		; /* see above */
10124 	else if (vcpu->arch.nmi_injected)
10125 		static_call(kvm_x86_inject_nmi)(vcpu);
10126 	else if (vcpu->arch.interrupt.injected)
10127 		static_call(kvm_x86_inject_irq)(vcpu, true);
10128 
10129 	/*
10130 	 * Exceptions that morph to VM-Exits are handled above, and pending
10131 	 * exceptions on top of injected exceptions that do not VM-Exit should
10132 	 * either morph to #DF or, sadly, override the injected exception.
10133 	 */
10134 	WARN_ON_ONCE(vcpu->arch.exception.injected &&
10135 		     vcpu->arch.exception.pending);
10136 
10137 	/*
10138 	 * Bail if immediate entry+exit to/from the guest is needed to complete
10139 	 * nested VM-Enter or event re-injection so that a different pending
10140 	 * event can be serviced (or if KVM needs to exit to userspace).
10141 	 *
10142 	 * Otherwise, continue processing events even if VM-Exit occurred.  The
10143 	 * VM-Exit will have cleared exceptions that were meant for L2, but
10144 	 * there may now be events that can be injected into L1.
10145 	 */
10146 	if (r < 0)
10147 		goto out;
10148 
10149 	/*
10150 	 * A pending exception VM-Exit should either result in nested VM-Exit
10151 	 * or force an immediate re-entry and exit to/from L2, and exception
10152 	 * VM-Exits cannot be injected (flag should _never_ be set).
10153 	 */
10154 	WARN_ON_ONCE(vcpu->arch.exception_vmexit.injected ||
10155 		     vcpu->arch.exception_vmexit.pending);
10156 
10157 	/*
10158 	 * New events, other than exceptions, cannot be injected if KVM needs
10159 	 * to re-inject a previous event.  See above comments on re-injecting
10160 	 * for why pending exceptions get priority.
10161 	 */
10162 	can_inject = !kvm_event_needs_reinjection(vcpu);
10163 
10164 	if (vcpu->arch.exception.pending) {
10165 		/*
10166 		 * Fault-class exceptions, except #DBs, set RF=1 in the RFLAGS
10167 		 * value pushed on the stack.  Trap-like exception and all #DBs
10168 		 * leave RF as-is (KVM follows Intel's behavior in this regard;
10169 		 * AMD states that code breakpoint #DBs excplitly clear RF=0).
10170 		 *
10171 		 * Note, most versions of Intel's SDM and AMD's APM incorrectly
10172 		 * describe the behavior of General Detect #DBs, which are
10173 		 * fault-like.  They do _not_ set RF, a la code breakpoints.
10174 		 */
10175 		if (exception_type(vcpu->arch.exception.vector) == EXCPT_FAULT)
10176 			__kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
10177 					     X86_EFLAGS_RF);
10178 
10179 		if (vcpu->arch.exception.vector == DB_VECTOR) {
10180 			kvm_deliver_exception_payload(vcpu, &vcpu->arch.exception);
10181 			if (vcpu->arch.dr7 & DR7_GD) {
10182 				vcpu->arch.dr7 &= ~DR7_GD;
10183 				kvm_update_dr7(vcpu);
10184 			}
10185 		}
10186 
10187 		kvm_inject_exception(vcpu);
10188 
10189 		vcpu->arch.exception.pending = false;
10190 		vcpu->arch.exception.injected = true;
10191 
10192 		can_inject = false;
10193 	}
10194 
10195 	/* Don't inject interrupts if the user asked to avoid doing so */
10196 	if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ)
10197 		return 0;
10198 
10199 	/*
10200 	 * Finally, inject interrupt events.  If an event cannot be injected
10201 	 * due to architectural conditions (e.g. IF=0) a window-open exit
10202 	 * will re-request KVM_REQ_EVENT.  Sometimes however an event is pending
10203 	 * and can architecturally be injected, but we cannot do it right now:
10204 	 * an interrupt could have arrived just now and we have to inject it
10205 	 * as a vmexit, or there could already an event in the queue, which is
10206 	 * indicated by can_inject.  In that case we request an immediate exit
10207 	 * in order to make progress and get back here for another iteration.
10208 	 * The kvm_x86_ops hooks communicate this by returning -EBUSY.
10209 	 */
10210 #ifdef CONFIG_KVM_SMM
10211 	if (vcpu->arch.smi_pending) {
10212 		r = can_inject ? static_call(kvm_x86_smi_allowed)(vcpu, true) : -EBUSY;
10213 		if (r < 0)
10214 			goto out;
10215 		if (r) {
10216 			vcpu->arch.smi_pending = false;
10217 			++vcpu->arch.smi_count;
10218 			enter_smm(vcpu);
10219 			can_inject = false;
10220 		} else
10221 			static_call(kvm_x86_enable_smi_window)(vcpu);
10222 	}
10223 #endif
10224 
10225 	if (vcpu->arch.nmi_pending) {
10226 		r = can_inject ? static_call(kvm_x86_nmi_allowed)(vcpu, true) : -EBUSY;
10227 		if (r < 0)
10228 			goto out;
10229 		if (r) {
10230 			--vcpu->arch.nmi_pending;
10231 			vcpu->arch.nmi_injected = true;
10232 			static_call(kvm_x86_inject_nmi)(vcpu);
10233 			can_inject = false;
10234 			WARN_ON(static_call(kvm_x86_nmi_allowed)(vcpu, true) < 0);
10235 		}
10236 		if (vcpu->arch.nmi_pending)
10237 			static_call(kvm_x86_enable_nmi_window)(vcpu);
10238 	}
10239 
10240 	if (kvm_cpu_has_injectable_intr(vcpu)) {
10241 		r = can_inject ? static_call(kvm_x86_interrupt_allowed)(vcpu, true) : -EBUSY;
10242 		if (r < 0)
10243 			goto out;
10244 		if (r) {
10245 			int irq = kvm_cpu_get_interrupt(vcpu);
10246 
10247 			if (!WARN_ON_ONCE(irq == -1)) {
10248 				kvm_queue_interrupt(vcpu, irq, false);
10249 				static_call(kvm_x86_inject_irq)(vcpu, false);
10250 				WARN_ON(static_call(kvm_x86_interrupt_allowed)(vcpu, true) < 0);
10251 			}
10252 		}
10253 		if (kvm_cpu_has_injectable_intr(vcpu))
10254 			static_call(kvm_x86_enable_irq_window)(vcpu);
10255 	}
10256 
10257 	if (is_guest_mode(vcpu) &&
10258 	    kvm_x86_ops.nested_ops->has_events &&
10259 	    kvm_x86_ops.nested_ops->has_events(vcpu, true))
10260 		*req_immediate_exit = true;
10261 
10262 	/*
10263 	 * KVM must never queue a new exception while injecting an event; KVM
10264 	 * is done emulating and should only propagate the to-be-injected event
10265 	 * to the VMCS/VMCB.  Queueing a new exception can put the vCPU into an
10266 	 * infinite loop as KVM will bail from VM-Enter to inject the pending
10267 	 * exception and start the cycle all over.
10268 	 *
10269 	 * Exempt triple faults as they have special handling and won't put the
10270 	 * vCPU into an infinite loop.  Triple fault can be queued when running
10271 	 * VMX without unrestricted guest, as that requires KVM to emulate Real
10272 	 * Mode events (see kvm_inject_realmode_interrupt()).
10273 	 */
10274 	WARN_ON_ONCE(vcpu->arch.exception.pending ||
10275 		     vcpu->arch.exception_vmexit.pending);
10276 	return 0;
10277 
10278 out:
10279 	if (r == -EBUSY) {
10280 		*req_immediate_exit = true;
10281 		r = 0;
10282 	}
10283 	return r;
10284 }
10285 
process_nmi(struct kvm_vcpu * vcpu)10286 static void process_nmi(struct kvm_vcpu *vcpu)
10287 {
10288 	unsigned int limit;
10289 
10290 	/*
10291 	 * x86 is limited to one NMI pending, but because KVM can't react to
10292 	 * incoming NMIs as quickly as bare metal, e.g. if the vCPU is
10293 	 * scheduled out, KVM needs to play nice with two queued NMIs showing
10294 	 * up at the same time.  To handle this scenario, allow two NMIs to be
10295 	 * (temporarily) pending so long as NMIs are not blocked and KVM is not
10296 	 * waiting for a previous NMI injection to complete (which effectively
10297 	 * blocks NMIs).  KVM will immediately inject one of the two NMIs, and
10298 	 * will request an NMI window to handle the second NMI.
10299 	 */
10300 	if (static_call(kvm_x86_get_nmi_mask)(vcpu) || vcpu->arch.nmi_injected)
10301 		limit = 1;
10302 	else
10303 		limit = 2;
10304 
10305 	/*
10306 	 * Adjust the limit to account for pending virtual NMIs, which aren't
10307 	 * tracked in vcpu->arch.nmi_pending.
10308 	 */
10309 	if (static_call(kvm_x86_is_vnmi_pending)(vcpu))
10310 		limit--;
10311 
10312 	vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
10313 	vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
10314 
10315 	if (vcpu->arch.nmi_pending &&
10316 	    (static_call(kvm_x86_set_vnmi_pending)(vcpu)))
10317 		vcpu->arch.nmi_pending--;
10318 
10319 	if (vcpu->arch.nmi_pending)
10320 		kvm_make_request(KVM_REQ_EVENT, vcpu);
10321 }
10322 
10323 /* Return total number of NMIs pending injection to the VM */
kvm_get_nr_pending_nmis(struct kvm_vcpu * vcpu)10324 int kvm_get_nr_pending_nmis(struct kvm_vcpu *vcpu)
10325 {
10326 	return vcpu->arch.nmi_pending +
10327 	       static_call(kvm_x86_is_vnmi_pending)(vcpu);
10328 }
10329 
kvm_make_scan_ioapic_request_mask(struct kvm * kvm,unsigned long * vcpu_bitmap)10330 void kvm_make_scan_ioapic_request_mask(struct kvm *kvm,
10331 				       unsigned long *vcpu_bitmap)
10332 {
10333 	kvm_make_vcpus_request_mask(kvm, KVM_REQ_SCAN_IOAPIC, vcpu_bitmap);
10334 }
10335 
kvm_make_scan_ioapic_request(struct kvm * kvm)10336 void kvm_make_scan_ioapic_request(struct kvm *kvm)
10337 {
10338 	kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
10339 }
10340 
__kvm_vcpu_update_apicv(struct kvm_vcpu * vcpu)10341 void __kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10342 {
10343 	struct kvm_lapic *apic = vcpu->arch.apic;
10344 	bool activate;
10345 
10346 	if (!lapic_in_kernel(vcpu))
10347 		return;
10348 
10349 	down_read(&vcpu->kvm->arch.apicv_update_lock);
10350 	preempt_disable();
10351 
10352 	/* Do not activate APICV when APIC is disabled */
10353 	activate = kvm_vcpu_apicv_activated(vcpu) &&
10354 		   (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED);
10355 
10356 	if (apic->apicv_active == activate)
10357 		goto out;
10358 
10359 	apic->apicv_active = activate;
10360 	kvm_apic_update_apicv(vcpu);
10361 	static_call(kvm_x86_refresh_apicv_exec_ctrl)(vcpu);
10362 
10363 	/*
10364 	 * When APICv gets disabled, we may still have injected interrupts
10365 	 * pending. At the same time, KVM_REQ_EVENT may not be set as APICv was
10366 	 * still active when the interrupt got accepted. Make sure
10367 	 * kvm_check_and_inject_events() is called to check for that.
10368 	 */
10369 	if (!apic->apicv_active)
10370 		kvm_make_request(KVM_REQ_EVENT, vcpu);
10371 
10372 out:
10373 	preempt_enable();
10374 	up_read(&vcpu->kvm->arch.apicv_update_lock);
10375 }
10376 EXPORT_SYMBOL_GPL(__kvm_vcpu_update_apicv);
10377 
kvm_vcpu_update_apicv(struct kvm_vcpu * vcpu)10378 static void kvm_vcpu_update_apicv(struct kvm_vcpu *vcpu)
10379 {
10380 	if (!lapic_in_kernel(vcpu))
10381 		return;
10382 
10383 	/*
10384 	 * Due to sharing page tables across vCPUs, the xAPIC memslot must be
10385 	 * deleted if any vCPU has xAPIC virtualization and x2APIC enabled, but
10386 	 * and hardware doesn't support x2APIC virtualization.  E.g. some AMD
10387 	 * CPUs support AVIC but not x2APIC.  KVM still allows enabling AVIC in
10388 	 * this case so that KVM can the AVIC doorbell to inject interrupts to
10389 	 * running vCPUs, but KVM must not create SPTEs for the APIC base as
10390 	 * the vCPU would incorrectly be able to access the vAPIC page via MMIO
10391 	 * despite being in x2APIC mode.  For simplicity, inhibiting the APIC
10392 	 * access page is sticky.
10393 	 */
10394 	if (apic_x2apic_mode(vcpu->arch.apic) &&
10395 	    kvm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization)
10396 		kvm_inhibit_apic_access_page(vcpu);
10397 
10398 	__kvm_vcpu_update_apicv(vcpu);
10399 }
10400 
__kvm_set_or_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason,bool set)10401 void __kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10402 				      enum kvm_apicv_inhibit reason, bool set)
10403 {
10404 	unsigned long old, new;
10405 
10406 	lockdep_assert_held_write(&kvm->arch.apicv_update_lock);
10407 
10408 	if (!(kvm_x86_ops.required_apicv_inhibits & BIT(reason)))
10409 		return;
10410 
10411 	old = new = kvm->arch.apicv_inhibit_reasons;
10412 
10413 	set_or_clear_apicv_inhibit(&new, reason, set);
10414 
10415 	if (!!old != !!new) {
10416 		/*
10417 		 * Kick all vCPUs before setting apicv_inhibit_reasons to avoid
10418 		 * false positives in the sanity check WARN in svm_vcpu_run().
10419 		 * This task will wait for all vCPUs to ack the kick IRQ before
10420 		 * updating apicv_inhibit_reasons, and all other vCPUs will
10421 		 * block on acquiring apicv_update_lock so that vCPUs can't
10422 		 * redo svm_vcpu_run() without seeing the new inhibit state.
10423 		 *
10424 		 * Note, holding apicv_update_lock and taking it in the read
10425 		 * side (handling the request) also prevents other vCPUs from
10426 		 * servicing the request with a stale apicv_inhibit_reasons.
10427 		 */
10428 		kvm_make_all_cpus_request(kvm, KVM_REQ_APICV_UPDATE);
10429 		kvm->arch.apicv_inhibit_reasons = new;
10430 		if (new) {
10431 			unsigned long gfn = gpa_to_gfn(APIC_DEFAULT_PHYS_BASE);
10432 			int idx = srcu_read_lock(&kvm->srcu);
10433 
10434 			kvm_zap_gfn_range(kvm, gfn, gfn+1);
10435 			srcu_read_unlock(&kvm->srcu, idx);
10436 		}
10437 	} else {
10438 		kvm->arch.apicv_inhibit_reasons = new;
10439 	}
10440 }
10441 
kvm_set_or_clear_apicv_inhibit(struct kvm * kvm,enum kvm_apicv_inhibit reason,bool set)10442 void kvm_set_or_clear_apicv_inhibit(struct kvm *kvm,
10443 				    enum kvm_apicv_inhibit reason, bool set)
10444 {
10445 	if (!enable_apicv)
10446 		return;
10447 
10448 	down_write(&kvm->arch.apicv_update_lock);
10449 	__kvm_set_or_clear_apicv_inhibit(kvm, reason, set);
10450 	up_write(&kvm->arch.apicv_update_lock);
10451 }
10452 EXPORT_SYMBOL_GPL(kvm_set_or_clear_apicv_inhibit);
10453 
vcpu_scan_ioapic(struct kvm_vcpu * vcpu)10454 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
10455 {
10456 	if (!kvm_apic_present(vcpu))
10457 		return;
10458 
10459 	bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
10460 
10461 	static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10462 
10463 	if (irqchip_split(vcpu->kvm))
10464 		kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
10465 	else if (ioapic_in_kernel(vcpu->kvm))
10466 		kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
10467 
10468 	if (is_guest_mode(vcpu))
10469 		vcpu->arch.load_eoi_exitmap_pending = true;
10470 	else
10471 		kvm_make_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu);
10472 }
10473 
vcpu_load_eoi_exitmap(struct kvm_vcpu * vcpu)10474 static void vcpu_load_eoi_exitmap(struct kvm_vcpu *vcpu)
10475 {
10476 	u64 eoi_exit_bitmap[4];
10477 
10478 	if (!kvm_apic_hw_enabled(vcpu->arch.apic))
10479 		return;
10480 
10481 	if (to_hv_vcpu(vcpu)) {
10482 		bitmap_or((ulong *)eoi_exit_bitmap,
10483 			  vcpu->arch.ioapic_handled_vectors,
10484 			  to_hv_synic(vcpu)->vec_bitmap, 256);
10485 		static_call_cond(kvm_x86_load_eoi_exitmap)(vcpu, eoi_exit_bitmap);
10486 		return;
10487 	}
10488 
10489 	static_call_cond(kvm_x86_load_eoi_exitmap)(
10490 		vcpu, (u64 *)vcpu->arch.ioapic_handled_vectors);
10491 }
10492 
kvm_arch_guest_memory_reclaimed(struct kvm * kvm)10493 void kvm_arch_guest_memory_reclaimed(struct kvm *kvm)
10494 {
10495 	static_call_cond(kvm_x86_guest_memory_reclaimed)(kvm);
10496 }
10497 
kvm_vcpu_reload_apic_access_page(struct kvm_vcpu * vcpu)10498 static void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
10499 {
10500 	if (!lapic_in_kernel(vcpu))
10501 		return;
10502 
10503 	static_call_cond(kvm_x86_set_apic_access_page_addr)(vcpu);
10504 }
10505 
__kvm_request_immediate_exit(struct kvm_vcpu * vcpu)10506 void __kvm_request_immediate_exit(struct kvm_vcpu *vcpu)
10507 {
10508 	smp_send_reschedule(vcpu->cpu);
10509 }
10510 EXPORT_SYMBOL_GPL(__kvm_request_immediate_exit);
10511 
10512 /*
10513  * Called within kvm->srcu read side.
10514  * Returns 1 to let vcpu_run() continue the guest execution loop without
10515  * exiting to the userspace.  Otherwise, the value will be returned to the
10516  * userspace.
10517  */
vcpu_enter_guest(struct kvm_vcpu * vcpu)10518 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
10519 {
10520 	int r;
10521 	bool req_int_win =
10522 		dm_request_for_irq_injection(vcpu) &&
10523 		kvm_cpu_accept_dm_intr(vcpu);
10524 	fastpath_t exit_fastpath;
10525 
10526 	bool req_immediate_exit = false;
10527 
10528 	if (kvm_request_pending(vcpu)) {
10529 		if (kvm_check_request(KVM_REQ_VM_DEAD, vcpu)) {
10530 			r = -EIO;
10531 			goto out;
10532 		}
10533 
10534 		if (kvm_dirty_ring_check_request(vcpu)) {
10535 			r = 0;
10536 			goto out;
10537 		}
10538 
10539 		if (kvm_check_request(KVM_REQ_GET_NESTED_STATE_PAGES, vcpu)) {
10540 			if (unlikely(!kvm_x86_ops.nested_ops->get_nested_state_pages(vcpu))) {
10541 				r = 0;
10542 				goto out;
10543 			}
10544 		}
10545 		if (kvm_check_request(KVM_REQ_MMU_FREE_OBSOLETE_ROOTS, vcpu))
10546 			kvm_mmu_free_obsolete_roots(vcpu);
10547 		if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
10548 			__kvm_migrate_timers(vcpu);
10549 		if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
10550 			kvm_update_masterclock(vcpu->kvm);
10551 		if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
10552 			kvm_gen_kvmclock_update(vcpu);
10553 		if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
10554 			r = kvm_guest_time_update(vcpu);
10555 			if (unlikely(r))
10556 				goto out;
10557 		}
10558 		if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
10559 			kvm_mmu_sync_roots(vcpu);
10560 		if (kvm_check_request(KVM_REQ_LOAD_MMU_PGD, vcpu))
10561 			kvm_mmu_load_pgd(vcpu);
10562 
10563 		/*
10564 		 * Note, the order matters here, as flushing "all" TLB entries
10565 		 * also flushes the "current" TLB entries, i.e. servicing the
10566 		 * flush "all" will clear any request to flush "current".
10567 		 */
10568 		if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
10569 			kvm_vcpu_flush_tlb_all(vcpu);
10570 
10571 		kvm_service_local_tlb_flush_requests(vcpu);
10572 
10573 		/*
10574 		 * Fall back to a "full" guest flush if Hyper-V's precise
10575 		 * flushing fails.  Note, Hyper-V's flushing is per-vCPU, but
10576 		 * the flushes are considered "remote" and not "local" because
10577 		 * the requests can be initiated from other vCPUs.
10578 		 */
10579 		if (kvm_check_request(KVM_REQ_HV_TLB_FLUSH, vcpu) &&
10580 		    kvm_hv_vcpu_flush_tlb(vcpu))
10581 			kvm_vcpu_flush_tlb_guest(vcpu);
10582 
10583 		if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
10584 			vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
10585 			r = 0;
10586 			goto out;
10587 		}
10588 		if (kvm_test_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10589 			if (is_guest_mode(vcpu))
10590 				kvm_x86_ops.nested_ops->triple_fault(vcpu);
10591 
10592 			if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
10593 				vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
10594 				vcpu->mmio_needed = 0;
10595 				r = 0;
10596 				goto out;
10597 			}
10598 		}
10599 		if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
10600 			/* Page is swapped out. Do synthetic halt */
10601 			vcpu->arch.apf.halted = true;
10602 			r = 1;
10603 			goto out;
10604 		}
10605 		if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
10606 			record_steal_time(vcpu);
10607 #ifdef CONFIG_KVM_SMM
10608 		if (kvm_check_request(KVM_REQ_SMI, vcpu))
10609 			process_smi(vcpu);
10610 #endif
10611 		if (kvm_check_request(KVM_REQ_NMI, vcpu))
10612 			process_nmi(vcpu);
10613 		if (kvm_check_request(KVM_REQ_PMU, vcpu))
10614 			kvm_pmu_handle_event(vcpu);
10615 		if (kvm_check_request(KVM_REQ_PMI, vcpu))
10616 			kvm_pmu_deliver_pmi(vcpu);
10617 		if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
10618 			BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
10619 			if (test_bit(vcpu->arch.pending_ioapic_eoi,
10620 				     vcpu->arch.ioapic_handled_vectors)) {
10621 				vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
10622 				vcpu->run->eoi.vector =
10623 						vcpu->arch.pending_ioapic_eoi;
10624 				r = 0;
10625 				goto out;
10626 			}
10627 		}
10628 		if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
10629 			vcpu_scan_ioapic(vcpu);
10630 		if (kvm_check_request(KVM_REQ_LOAD_EOI_EXITMAP, vcpu))
10631 			vcpu_load_eoi_exitmap(vcpu);
10632 		if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
10633 			kvm_vcpu_reload_apic_access_page(vcpu);
10634 		if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
10635 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10636 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
10637 			vcpu->run->system_event.ndata = 0;
10638 			r = 0;
10639 			goto out;
10640 		}
10641 		if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
10642 			vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
10643 			vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
10644 			vcpu->run->system_event.ndata = 0;
10645 			r = 0;
10646 			goto out;
10647 		}
10648 		if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
10649 			struct kvm_vcpu_hv *hv_vcpu = to_hv_vcpu(vcpu);
10650 
10651 			vcpu->run->exit_reason = KVM_EXIT_HYPERV;
10652 			vcpu->run->hyperv = hv_vcpu->exit;
10653 			r = 0;
10654 			goto out;
10655 		}
10656 
10657 		/*
10658 		 * KVM_REQ_HV_STIMER has to be processed after
10659 		 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
10660 		 * depend on the guest clock being up-to-date
10661 		 */
10662 		if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
10663 			kvm_hv_process_stimers(vcpu);
10664 		if (kvm_check_request(KVM_REQ_APICV_UPDATE, vcpu))
10665 			kvm_vcpu_update_apicv(vcpu);
10666 		if (kvm_check_request(KVM_REQ_APF_READY, vcpu))
10667 			kvm_check_async_pf_completion(vcpu);
10668 		if (kvm_check_request(KVM_REQ_MSR_FILTER_CHANGED, vcpu))
10669 			static_call(kvm_x86_msr_filter_changed)(vcpu);
10670 
10671 		if (kvm_check_request(KVM_REQ_UPDATE_CPU_DIRTY_LOGGING, vcpu))
10672 			static_call(kvm_x86_update_cpu_dirty_logging)(vcpu);
10673 	}
10674 
10675 	if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win ||
10676 	    kvm_xen_has_interrupt(vcpu)) {
10677 		++vcpu->stat.req_event;
10678 		r = kvm_apic_accept_events(vcpu);
10679 		if (r < 0) {
10680 			r = 0;
10681 			goto out;
10682 		}
10683 		if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
10684 			r = 1;
10685 			goto out;
10686 		}
10687 
10688 		r = kvm_check_and_inject_events(vcpu, &req_immediate_exit);
10689 		if (r < 0) {
10690 			r = 0;
10691 			goto out;
10692 		}
10693 		if (req_int_win)
10694 			static_call(kvm_x86_enable_irq_window)(vcpu);
10695 
10696 		if (kvm_lapic_enabled(vcpu)) {
10697 			update_cr8_intercept(vcpu);
10698 			kvm_lapic_sync_to_vapic(vcpu);
10699 		}
10700 	}
10701 
10702 	r = kvm_mmu_reload(vcpu);
10703 	if (unlikely(r)) {
10704 		goto cancel_injection;
10705 	}
10706 
10707 	preempt_disable();
10708 
10709 	static_call(kvm_x86_prepare_switch_to_guest)(vcpu);
10710 
10711 	/*
10712 	 * Disable IRQs before setting IN_GUEST_MODE.  Posted interrupt
10713 	 * IPI are then delayed after guest entry, which ensures that they
10714 	 * result in virtual interrupt delivery.
10715 	 */
10716 	local_irq_disable();
10717 
10718 	/* Store vcpu->apicv_active before vcpu->mode.  */
10719 	smp_store_release(&vcpu->mode, IN_GUEST_MODE);
10720 
10721 	kvm_vcpu_srcu_read_unlock(vcpu);
10722 
10723 	/*
10724 	 * 1) We should set ->mode before checking ->requests.  Please see
10725 	 * the comment in kvm_vcpu_exiting_guest_mode().
10726 	 *
10727 	 * 2) For APICv, we should set ->mode before checking PID.ON. This
10728 	 * pairs with the memory barrier implicit in pi_test_and_set_on
10729 	 * (see vmx_deliver_posted_interrupt).
10730 	 *
10731 	 * 3) This also orders the write to mode from any reads to the page
10732 	 * tables done while the VCPU is running.  Please see the comment
10733 	 * in kvm_flush_remote_tlbs.
10734 	 */
10735 	smp_mb__after_srcu_read_unlock();
10736 
10737 	/*
10738 	 * Process pending posted interrupts to handle the case where the
10739 	 * notification IRQ arrived in the host, or was never sent (because the
10740 	 * target vCPU wasn't running).  Do this regardless of the vCPU's APICv
10741 	 * status, KVM doesn't update assigned devices when APICv is inhibited,
10742 	 * i.e. they can post interrupts even if APICv is temporarily disabled.
10743 	 */
10744 	if (kvm_lapic_enabled(vcpu))
10745 		static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10746 
10747 	if (kvm_vcpu_exit_request(vcpu)) {
10748 		vcpu->mode = OUTSIDE_GUEST_MODE;
10749 		smp_wmb();
10750 		local_irq_enable();
10751 		preempt_enable();
10752 		kvm_vcpu_srcu_read_lock(vcpu);
10753 		r = 1;
10754 		goto cancel_injection;
10755 	}
10756 
10757 	if (req_immediate_exit) {
10758 		kvm_make_request(KVM_REQ_EVENT, vcpu);
10759 		static_call(kvm_x86_request_immediate_exit)(vcpu);
10760 	}
10761 
10762 	fpregs_assert_state_consistent();
10763 	if (test_thread_flag(TIF_NEED_FPU_LOAD))
10764 		switch_fpu_return();
10765 
10766 	if (vcpu->arch.guest_fpu.xfd_err)
10767 		wrmsrl(MSR_IA32_XFD_ERR, vcpu->arch.guest_fpu.xfd_err);
10768 
10769 	if (unlikely(vcpu->arch.switch_db_regs)) {
10770 		set_debugreg(0, 7);
10771 		set_debugreg(vcpu->arch.eff_db[0], 0);
10772 		set_debugreg(vcpu->arch.eff_db[1], 1);
10773 		set_debugreg(vcpu->arch.eff_db[2], 2);
10774 		set_debugreg(vcpu->arch.eff_db[3], 3);
10775 	} else if (unlikely(hw_breakpoint_active())) {
10776 		set_debugreg(0, 7);
10777 	}
10778 
10779 	guest_timing_enter_irqoff();
10780 
10781 	for (;;) {
10782 		/*
10783 		 * Assert that vCPU vs. VM APICv state is consistent.  An APICv
10784 		 * update must kick and wait for all vCPUs before toggling the
10785 		 * per-VM state, and responsing vCPUs must wait for the update
10786 		 * to complete before servicing KVM_REQ_APICV_UPDATE.
10787 		 */
10788 		WARN_ON_ONCE((kvm_vcpu_apicv_activated(vcpu) != kvm_vcpu_apicv_active(vcpu)) &&
10789 			     (kvm_get_apic_mode(vcpu) != LAPIC_MODE_DISABLED));
10790 
10791 		exit_fastpath = static_call(kvm_x86_vcpu_run)(vcpu);
10792 		if (likely(exit_fastpath != EXIT_FASTPATH_REENTER_GUEST))
10793 			break;
10794 
10795 		if (kvm_lapic_enabled(vcpu))
10796 			static_call_cond(kvm_x86_sync_pir_to_irr)(vcpu);
10797 
10798 		if (unlikely(kvm_vcpu_exit_request(vcpu))) {
10799 			exit_fastpath = EXIT_FASTPATH_EXIT_HANDLED;
10800 			break;
10801 		}
10802 
10803 		/* Note, VM-Exits that go down the "slow" path are accounted below. */
10804 		++vcpu->stat.exits;
10805 	}
10806 
10807 	/*
10808 	 * Do this here before restoring debug registers on the host.  And
10809 	 * since we do this before handling the vmexit, a DR access vmexit
10810 	 * can (a) read the correct value of the debug registers, (b) set
10811 	 * KVM_DEBUGREG_WONT_EXIT again.
10812 	 */
10813 	if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
10814 		WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
10815 		static_call(kvm_x86_sync_dirty_debug_regs)(vcpu);
10816 		kvm_update_dr0123(vcpu);
10817 		kvm_update_dr7(vcpu);
10818 	}
10819 
10820 	/*
10821 	 * If the guest has used debug registers, at least dr7
10822 	 * will be disabled while returning to the host.
10823 	 * If we don't have active breakpoints in the host, we don't
10824 	 * care about the messed up debug address registers. But if
10825 	 * we have some of them active, restore the old state.
10826 	 */
10827 	if (hw_breakpoint_active())
10828 		hw_breakpoint_restore();
10829 
10830 	vcpu->arch.last_vmentry_cpu = vcpu->cpu;
10831 	vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
10832 
10833 	vcpu->mode = OUTSIDE_GUEST_MODE;
10834 	smp_wmb();
10835 
10836 	/*
10837 	 * Sync xfd before calling handle_exit_irqoff() which may
10838 	 * rely on the fact that guest_fpu::xfd is up-to-date (e.g.
10839 	 * in #NM irqoff handler).
10840 	 */
10841 	if (vcpu->arch.xfd_no_write_intercept)
10842 		fpu_sync_guest_vmexit_xfd_state();
10843 
10844 	static_call(kvm_x86_handle_exit_irqoff)(vcpu);
10845 
10846 	if (vcpu->arch.guest_fpu.xfd_err)
10847 		wrmsrl(MSR_IA32_XFD_ERR, 0);
10848 
10849 	/*
10850 	 * Consume any pending interrupts, including the possible source of
10851 	 * VM-Exit on SVM and any ticks that occur between VM-Exit and now.
10852 	 * An instruction is required after local_irq_enable() to fully unblock
10853 	 * interrupts on processors that implement an interrupt shadow, the
10854 	 * stat.exits increment will do nicely.
10855 	 */
10856 	kvm_before_interrupt(vcpu, KVM_HANDLING_IRQ);
10857 	local_irq_enable();
10858 	++vcpu->stat.exits;
10859 	local_irq_disable();
10860 	kvm_after_interrupt(vcpu);
10861 
10862 	/*
10863 	 * Wait until after servicing IRQs to account guest time so that any
10864 	 * ticks that occurred while running the guest are properly accounted
10865 	 * to the guest.  Waiting until IRQs are enabled degrades the accuracy
10866 	 * of accounting via context tracking, but the loss of accuracy is
10867 	 * acceptable for all known use cases.
10868 	 */
10869 	guest_timing_exit_irqoff();
10870 
10871 	local_irq_enable();
10872 	preempt_enable();
10873 
10874 	kvm_vcpu_srcu_read_lock(vcpu);
10875 
10876 	/*
10877 	 * Profile KVM exit RIPs:
10878 	 */
10879 	if (unlikely(prof_on == KVM_PROFILING)) {
10880 		unsigned long rip = kvm_rip_read(vcpu);
10881 		profile_hit(KVM_PROFILING, (void *)rip);
10882 	}
10883 
10884 	if (unlikely(vcpu->arch.tsc_always_catchup))
10885 		kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
10886 
10887 	if (vcpu->arch.apic_attention)
10888 		kvm_lapic_sync_from_vapic(vcpu);
10889 
10890 	r = static_call(kvm_x86_handle_exit)(vcpu, exit_fastpath);
10891 	return r;
10892 
10893 cancel_injection:
10894 	if (req_immediate_exit)
10895 		kvm_make_request(KVM_REQ_EVENT, vcpu);
10896 	static_call(kvm_x86_cancel_injection)(vcpu);
10897 	if (unlikely(vcpu->arch.apic_attention))
10898 		kvm_lapic_sync_from_vapic(vcpu);
10899 out:
10900 	return r;
10901 }
10902 
10903 /* Called within kvm->srcu read side.  */
vcpu_block(struct kvm_vcpu * vcpu)10904 static inline int vcpu_block(struct kvm_vcpu *vcpu)
10905 {
10906 	bool hv_timer;
10907 
10908 	if (!kvm_arch_vcpu_runnable(vcpu)) {
10909 		/*
10910 		 * Switch to the software timer before halt-polling/blocking as
10911 		 * the guest's timer may be a break event for the vCPU, and the
10912 		 * hypervisor timer runs only when the CPU is in guest mode.
10913 		 * Switch before halt-polling so that KVM recognizes an expired
10914 		 * timer before blocking.
10915 		 */
10916 		hv_timer = kvm_lapic_hv_timer_in_use(vcpu);
10917 		if (hv_timer)
10918 			kvm_lapic_switch_to_sw_timer(vcpu);
10919 
10920 		kvm_vcpu_srcu_read_unlock(vcpu);
10921 		if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10922 			kvm_vcpu_halt(vcpu);
10923 		else
10924 			kvm_vcpu_block(vcpu);
10925 		kvm_vcpu_srcu_read_lock(vcpu);
10926 
10927 		if (hv_timer)
10928 			kvm_lapic_switch_to_hv_timer(vcpu);
10929 
10930 		/*
10931 		 * If the vCPU is not runnable, a signal or another host event
10932 		 * of some kind is pending; service it without changing the
10933 		 * vCPU's activity state.
10934 		 */
10935 		if (!kvm_arch_vcpu_runnable(vcpu))
10936 			return 1;
10937 	}
10938 
10939 	/*
10940 	 * Evaluate nested events before exiting the halted state.  This allows
10941 	 * the halt state to be recorded properly in the VMCS12's activity
10942 	 * state field (AMD does not have a similar field and a VM-Exit always
10943 	 * causes a spurious wakeup from HLT).
10944 	 */
10945 	if (is_guest_mode(vcpu)) {
10946 		if (kvm_check_nested_events(vcpu) < 0)
10947 			return 0;
10948 	}
10949 
10950 	if (kvm_apic_accept_events(vcpu) < 0)
10951 		return 0;
10952 	switch(vcpu->arch.mp_state) {
10953 	case KVM_MP_STATE_HALTED:
10954 	case KVM_MP_STATE_AP_RESET_HOLD:
10955 		vcpu->arch.pv.pv_unhalted = false;
10956 		vcpu->arch.mp_state =
10957 			KVM_MP_STATE_RUNNABLE;
10958 		fallthrough;
10959 	case KVM_MP_STATE_RUNNABLE:
10960 		vcpu->arch.apf.halted = false;
10961 		break;
10962 	case KVM_MP_STATE_INIT_RECEIVED:
10963 		break;
10964 	default:
10965 		WARN_ON_ONCE(1);
10966 		break;
10967 	}
10968 	return 1;
10969 }
10970 
kvm_vcpu_running(struct kvm_vcpu * vcpu)10971 static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
10972 {
10973 	return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
10974 		!vcpu->arch.apf.halted);
10975 }
10976 
10977 /* Called within kvm->srcu read side.  */
vcpu_run(struct kvm_vcpu * vcpu)10978 static int vcpu_run(struct kvm_vcpu *vcpu)
10979 {
10980 	int r;
10981 
10982 	vcpu->arch.l1tf_flush_l1d = true;
10983 
10984 	for (;;) {
10985 		/*
10986 		 * If another guest vCPU requests a PV TLB flush in the middle
10987 		 * of instruction emulation, the rest of the emulation could
10988 		 * use a stale page translation. Assume that any code after
10989 		 * this point can start executing an instruction.
10990 		 */
10991 		vcpu->arch.at_instruction_boundary = false;
10992 		if (kvm_vcpu_running(vcpu)) {
10993 			r = vcpu_enter_guest(vcpu);
10994 		} else {
10995 			r = vcpu_block(vcpu);
10996 		}
10997 
10998 		if (r <= 0)
10999 			break;
11000 
11001 		kvm_clear_request(KVM_REQ_UNBLOCK, vcpu);
11002 		if (kvm_xen_has_pending_events(vcpu))
11003 			kvm_xen_inject_pending_events(vcpu);
11004 
11005 		if (kvm_cpu_has_pending_timer(vcpu))
11006 			kvm_inject_pending_timer_irqs(vcpu);
11007 
11008 		if (dm_request_for_irq_injection(vcpu) &&
11009 			kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
11010 			r = 0;
11011 			vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
11012 			++vcpu->stat.request_irq_exits;
11013 			break;
11014 		}
11015 
11016 		if (__xfer_to_guest_mode_work_pending()) {
11017 			kvm_vcpu_srcu_read_unlock(vcpu);
11018 			r = xfer_to_guest_mode_handle_work(vcpu);
11019 			kvm_vcpu_srcu_read_lock(vcpu);
11020 			if (r)
11021 				return r;
11022 		}
11023 	}
11024 
11025 	return r;
11026 }
11027 
complete_emulated_io(struct kvm_vcpu * vcpu)11028 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
11029 {
11030 	return kvm_emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
11031 }
11032 
complete_emulated_pio(struct kvm_vcpu * vcpu)11033 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
11034 {
11035 	BUG_ON(!vcpu->arch.pio.count);
11036 
11037 	return complete_emulated_io(vcpu);
11038 }
11039 
11040 /*
11041  * Implements the following, as a state machine:
11042  *
11043  * read:
11044  *   for each fragment
11045  *     for each mmio piece in the fragment
11046  *       write gpa, len
11047  *       exit
11048  *       copy data
11049  *   execute insn
11050  *
11051  * write:
11052  *   for each fragment
11053  *     for each mmio piece in the fragment
11054  *       write gpa, len
11055  *       copy data
11056  *       exit
11057  */
complete_emulated_mmio(struct kvm_vcpu * vcpu)11058 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
11059 {
11060 	struct kvm_run *run = vcpu->run;
11061 	struct kvm_mmio_fragment *frag;
11062 	unsigned len;
11063 
11064 	BUG_ON(!vcpu->mmio_needed);
11065 
11066 	/* Complete previous fragment */
11067 	frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
11068 	len = min(8u, frag->len);
11069 	if (!vcpu->mmio_is_write)
11070 		memcpy(frag->data, run->mmio.data, len);
11071 
11072 	if (frag->len <= 8) {
11073 		/* Switch to the next fragment. */
11074 		frag++;
11075 		vcpu->mmio_cur_fragment++;
11076 	} else {
11077 		/* Go forward to the next mmio piece. */
11078 		frag->data += len;
11079 		frag->gpa += len;
11080 		frag->len -= len;
11081 	}
11082 
11083 	if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
11084 		vcpu->mmio_needed = 0;
11085 
11086 		/* FIXME: return into emulator if single-stepping.  */
11087 		if (vcpu->mmio_is_write)
11088 			return 1;
11089 		vcpu->mmio_read_completed = 1;
11090 		return complete_emulated_io(vcpu);
11091 	}
11092 
11093 	run->exit_reason = KVM_EXIT_MMIO;
11094 	run->mmio.phys_addr = frag->gpa;
11095 	if (vcpu->mmio_is_write)
11096 		memcpy(run->mmio.data, frag->data, min(8u, frag->len));
11097 	run->mmio.len = min(8u, frag->len);
11098 	run->mmio.is_write = vcpu->mmio_is_write;
11099 	vcpu->arch.complete_userspace_io = complete_emulated_mmio;
11100 	return 0;
11101 }
11102 
11103 /* Swap (qemu) user FPU context for the guest FPU context. */
kvm_load_guest_fpu(struct kvm_vcpu * vcpu)11104 static void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
11105 {
11106 	/* Exclude PKRU, it's restored separately immediately after VM-Exit. */
11107 	fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, true);
11108 	trace_kvm_fpu(1);
11109 }
11110 
11111 /* When vcpu_run ends, restore user space FPU context. */
kvm_put_guest_fpu(struct kvm_vcpu * vcpu)11112 static void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
11113 {
11114 	fpu_swap_kvm_fpstate(&vcpu->arch.guest_fpu, false);
11115 	++vcpu->stat.fpu_reload;
11116 	trace_kvm_fpu(0);
11117 }
11118 
kvm_arch_vcpu_ioctl_run(struct kvm_vcpu * vcpu)11119 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
11120 {
11121 	struct kvm_queued_exception *ex = &vcpu->arch.exception;
11122 	struct kvm_run *kvm_run = vcpu->run;
11123 	int r;
11124 
11125 	vcpu_load(vcpu);
11126 	kvm_sigset_activate(vcpu);
11127 	kvm_run->flags = 0;
11128 	kvm_load_guest_fpu(vcpu);
11129 
11130 	kvm_vcpu_srcu_read_lock(vcpu);
11131 	if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
11132 		if (kvm_run->immediate_exit) {
11133 			r = -EINTR;
11134 			goto out;
11135 		}
11136 
11137 		/*
11138 		 * Don't bother switching APIC timer emulation from the
11139 		 * hypervisor timer to the software timer, the only way for the
11140 		 * APIC timer to be active is if userspace stuffed vCPU state,
11141 		 * i.e. put the vCPU into a nonsensical state.  Only an INIT
11142 		 * will transition the vCPU out of UNINITIALIZED (without more
11143 		 * state stuffing from userspace), which will reset the local
11144 		 * APIC and thus cancel the timer or drop the IRQ (if the timer
11145 		 * already expired).
11146 		 */
11147 		kvm_vcpu_srcu_read_unlock(vcpu);
11148 		kvm_vcpu_block(vcpu);
11149 		kvm_vcpu_srcu_read_lock(vcpu);
11150 
11151 		if (kvm_apic_accept_events(vcpu) < 0) {
11152 			r = 0;
11153 			goto out;
11154 		}
11155 		r = -EAGAIN;
11156 		if (signal_pending(current)) {
11157 			r = -EINTR;
11158 			kvm_run->exit_reason = KVM_EXIT_INTR;
11159 			++vcpu->stat.signal_exits;
11160 		}
11161 		goto out;
11162 	}
11163 
11164 	if ((kvm_run->kvm_valid_regs & ~KVM_SYNC_X86_VALID_FIELDS) ||
11165 	    (kvm_run->kvm_dirty_regs & ~KVM_SYNC_X86_VALID_FIELDS)) {
11166 		r = -EINVAL;
11167 		goto out;
11168 	}
11169 
11170 	if (kvm_run->kvm_dirty_regs) {
11171 		r = sync_regs(vcpu);
11172 		if (r != 0)
11173 			goto out;
11174 	}
11175 
11176 	/* re-sync apic's tpr */
11177 	if (!lapic_in_kernel(vcpu)) {
11178 		if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
11179 			r = -EINVAL;
11180 			goto out;
11181 		}
11182 	}
11183 
11184 	/*
11185 	 * If userspace set a pending exception and L2 is active, convert it to
11186 	 * a pending VM-Exit if L1 wants to intercept the exception.
11187 	 */
11188 	if (vcpu->arch.exception_from_userspace && is_guest_mode(vcpu) &&
11189 	    kvm_x86_ops.nested_ops->is_exception_vmexit(vcpu, ex->vector,
11190 							ex->error_code)) {
11191 		kvm_queue_exception_vmexit(vcpu, ex->vector,
11192 					   ex->has_error_code, ex->error_code,
11193 					   ex->has_payload, ex->payload);
11194 		ex->injected = false;
11195 		ex->pending = false;
11196 	}
11197 	vcpu->arch.exception_from_userspace = false;
11198 
11199 	if (unlikely(vcpu->arch.complete_userspace_io)) {
11200 		int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
11201 		vcpu->arch.complete_userspace_io = NULL;
11202 		r = cui(vcpu);
11203 		if (r <= 0)
11204 			goto out;
11205 	} else {
11206 		WARN_ON_ONCE(vcpu->arch.pio.count);
11207 		WARN_ON_ONCE(vcpu->mmio_needed);
11208 	}
11209 
11210 	if (kvm_run->immediate_exit) {
11211 		r = -EINTR;
11212 		goto out;
11213 	}
11214 
11215 	r = static_call(kvm_x86_vcpu_pre_run)(vcpu);
11216 	if (r <= 0)
11217 		goto out;
11218 
11219 	r = vcpu_run(vcpu);
11220 
11221 out:
11222 	kvm_put_guest_fpu(vcpu);
11223 	if (kvm_run->kvm_valid_regs)
11224 		store_regs(vcpu);
11225 	post_kvm_run_save(vcpu);
11226 	kvm_vcpu_srcu_read_unlock(vcpu);
11227 
11228 	kvm_sigset_deactivate(vcpu);
11229 	vcpu_put(vcpu);
11230 	return r;
11231 }
11232 
__get_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11233 static void __get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11234 {
11235 	if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
11236 		/*
11237 		 * We are here if userspace calls get_regs() in the middle of
11238 		 * instruction emulation. Registers state needs to be copied
11239 		 * back from emulation context to vcpu. Userspace shouldn't do
11240 		 * that usually, but some bad designed PV devices (vmware
11241 		 * backdoor interface) need this to work
11242 		 */
11243 		emulator_writeback_register_cache(vcpu->arch.emulate_ctxt);
11244 		vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11245 	}
11246 	regs->rax = kvm_rax_read(vcpu);
11247 	regs->rbx = kvm_rbx_read(vcpu);
11248 	regs->rcx = kvm_rcx_read(vcpu);
11249 	regs->rdx = kvm_rdx_read(vcpu);
11250 	regs->rsi = kvm_rsi_read(vcpu);
11251 	regs->rdi = kvm_rdi_read(vcpu);
11252 	regs->rsp = kvm_rsp_read(vcpu);
11253 	regs->rbp = kvm_rbp_read(vcpu);
11254 #ifdef CONFIG_X86_64
11255 	regs->r8 = kvm_r8_read(vcpu);
11256 	regs->r9 = kvm_r9_read(vcpu);
11257 	regs->r10 = kvm_r10_read(vcpu);
11258 	regs->r11 = kvm_r11_read(vcpu);
11259 	regs->r12 = kvm_r12_read(vcpu);
11260 	regs->r13 = kvm_r13_read(vcpu);
11261 	regs->r14 = kvm_r14_read(vcpu);
11262 	regs->r15 = kvm_r15_read(vcpu);
11263 #endif
11264 
11265 	regs->rip = kvm_rip_read(vcpu);
11266 	regs->rflags = kvm_get_rflags(vcpu);
11267 }
11268 
kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11269 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11270 {
11271 	vcpu_load(vcpu);
11272 	__get_regs(vcpu, regs);
11273 	vcpu_put(vcpu);
11274 	return 0;
11275 }
11276 
__set_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11277 static void __set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11278 {
11279 	vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
11280 	vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
11281 
11282 	kvm_rax_write(vcpu, regs->rax);
11283 	kvm_rbx_write(vcpu, regs->rbx);
11284 	kvm_rcx_write(vcpu, regs->rcx);
11285 	kvm_rdx_write(vcpu, regs->rdx);
11286 	kvm_rsi_write(vcpu, regs->rsi);
11287 	kvm_rdi_write(vcpu, regs->rdi);
11288 	kvm_rsp_write(vcpu, regs->rsp);
11289 	kvm_rbp_write(vcpu, regs->rbp);
11290 #ifdef CONFIG_X86_64
11291 	kvm_r8_write(vcpu, regs->r8);
11292 	kvm_r9_write(vcpu, regs->r9);
11293 	kvm_r10_write(vcpu, regs->r10);
11294 	kvm_r11_write(vcpu, regs->r11);
11295 	kvm_r12_write(vcpu, regs->r12);
11296 	kvm_r13_write(vcpu, regs->r13);
11297 	kvm_r14_write(vcpu, regs->r14);
11298 	kvm_r15_write(vcpu, regs->r15);
11299 #endif
11300 
11301 	kvm_rip_write(vcpu, regs->rip);
11302 	kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
11303 
11304 	vcpu->arch.exception.pending = false;
11305 	vcpu->arch.exception_vmexit.pending = false;
11306 
11307 	kvm_make_request(KVM_REQ_EVENT, vcpu);
11308 }
11309 
kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu * vcpu,struct kvm_regs * regs)11310 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
11311 {
11312 	vcpu_load(vcpu);
11313 	__set_regs(vcpu, regs);
11314 	vcpu_put(vcpu);
11315 	return 0;
11316 }
11317 
__get_sregs_common(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11318 static void __get_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11319 {
11320 	struct desc_ptr dt;
11321 
11322 	if (vcpu->arch.guest_state_protected)
11323 		goto skip_protected_regs;
11324 
11325 	kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11326 	kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11327 	kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11328 	kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11329 	kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11330 	kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11331 
11332 	kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11333 	kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11334 
11335 	static_call(kvm_x86_get_idt)(vcpu, &dt);
11336 	sregs->idt.limit = dt.size;
11337 	sregs->idt.base = dt.address;
11338 	static_call(kvm_x86_get_gdt)(vcpu, &dt);
11339 	sregs->gdt.limit = dt.size;
11340 	sregs->gdt.base = dt.address;
11341 
11342 	sregs->cr2 = vcpu->arch.cr2;
11343 	sregs->cr3 = kvm_read_cr3(vcpu);
11344 
11345 skip_protected_regs:
11346 	sregs->cr0 = kvm_read_cr0(vcpu);
11347 	sregs->cr4 = kvm_read_cr4(vcpu);
11348 	sregs->cr8 = kvm_get_cr8(vcpu);
11349 	sregs->efer = vcpu->arch.efer;
11350 	sregs->apic_base = kvm_get_apic_base(vcpu);
11351 }
11352 
__get_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11353 static void __get_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11354 {
11355 	__get_sregs_common(vcpu, sregs);
11356 
11357 	if (vcpu->arch.guest_state_protected)
11358 		return;
11359 
11360 	if (vcpu->arch.interrupt.injected && !vcpu->arch.interrupt.soft)
11361 		set_bit(vcpu->arch.interrupt.nr,
11362 			(unsigned long *)sregs->interrupt_bitmap);
11363 }
11364 
__get_sregs2(struct kvm_vcpu * vcpu,struct kvm_sregs2 * sregs2)11365 static void __get_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11366 {
11367 	int i;
11368 
11369 	__get_sregs_common(vcpu, (struct kvm_sregs *)sregs2);
11370 
11371 	if (vcpu->arch.guest_state_protected)
11372 		return;
11373 
11374 	if (is_pae_paging(vcpu)) {
11375 		for (i = 0 ; i < 4 ; i++)
11376 			sregs2->pdptrs[i] = kvm_pdptr_read(vcpu, i);
11377 		sregs2->flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
11378 	}
11379 }
11380 
kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11381 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
11382 				  struct kvm_sregs *sregs)
11383 {
11384 	vcpu_load(vcpu);
11385 	__get_sregs(vcpu, sregs);
11386 	vcpu_put(vcpu);
11387 	return 0;
11388 }
11389 
kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)11390 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
11391 				    struct kvm_mp_state *mp_state)
11392 {
11393 	int r;
11394 
11395 	vcpu_load(vcpu);
11396 	if (kvm_mpx_supported())
11397 		kvm_load_guest_fpu(vcpu);
11398 
11399 	r = kvm_apic_accept_events(vcpu);
11400 	if (r < 0)
11401 		goto out;
11402 	r = 0;
11403 
11404 	if ((vcpu->arch.mp_state == KVM_MP_STATE_HALTED ||
11405 	     vcpu->arch.mp_state == KVM_MP_STATE_AP_RESET_HOLD) &&
11406 	    vcpu->arch.pv.pv_unhalted)
11407 		mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
11408 	else
11409 		mp_state->mp_state = vcpu->arch.mp_state;
11410 
11411 out:
11412 	if (kvm_mpx_supported())
11413 		kvm_put_guest_fpu(vcpu);
11414 	vcpu_put(vcpu);
11415 	return r;
11416 }
11417 
kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu * vcpu,struct kvm_mp_state * mp_state)11418 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
11419 				    struct kvm_mp_state *mp_state)
11420 {
11421 	int ret = -EINVAL;
11422 
11423 	vcpu_load(vcpu);
11424 
11425 	switch (mp_state->mp_state) {
11426 	case KVM_MP_STATE_UNINITIALIZED:
11427 	case KVM_MP_STATE_HALTED:
11428 	case KVM_MP_STATE_AP_RESET_HOLD:
11429 	case KVM_MP_STATE_INIT_RECEIVED:
11430 	case KVM_MP_STATE_SIPI_RECEIVED:
11431 		if (!lapic_in_kernel(vcpu))
11432 			goto out;
11433 		break;
11434 
11435 	case KVM_MP_STATE_RUNNABLE:
11436 		break;
11437 
11438 	default:
11439 		goto out;
11440 	}
11441 
11442 	/*
11443 	 * Pending INITs are reported using KVM_SET_VCPU_EVENTS, disallow
11444 	 * forcing the guest into INIT/SIPI if those events are supposed to be
11445 	 * blocked.  KVM prioritizes SMI over INIT, so reject INIT/SIPI state
11446 	 * if an SMI is pending as well.
11447 	 */
11448 	if ((!kvm_apic_init_sipi_allowed(vcpu) || vcpu->arch.smi_pending) &&
11449 	    (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
11450 	     mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
11451 		goto out;
11452 
11453 	if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
11454 		vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
11455 		set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
11456 	} else
11457 		vcpu->arch.mp_state = mp_state->mp_state;
11458 	kvm_make_request(KVM_REQ_EVENT, vcpu);
11459 
11460 	ret = 0;
11461 out:
11462 	vcpu_put(vcpu);
11463 	return ret;
11464 }
11465 
kvm_task_switch(struct kvm_vcpu * vcpu,u16 tss_selector,int idt_index,int reason,bool has_error_code,u32 error_code)11466 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
11467 		    int reason, bool has_error_code, u32 error_code)
11468 {
11469 	struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
11470 	int ret;
11471 
11472 	init_emulate_ctxt(vcpu);
11473 
11474 	ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
11475 				   has_error_code, error_code);
11476 	if (ret) {
11477 		vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
11478 		vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
11479 		vcpu->run->internal.ndata = 0;
11480 		return 0;
11481 	}
11482 
11483 	kvm_rip_write(vcpu, ctxt->eip);
11484 	kvm_set_rflags(vcpu, ctxt->eflags);
11485 	return 1;
11486 }
11487 EXPORT_SYMBOL_GPL(kvm_task_switch);
11488 
kvm_is_valid_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11489 static bool kvm_is_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11490 {
11491 	if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
11492 		/*
11493 		 * When EFER.LME and CR0.PG are set, the processor is in
11494 		 * 64-bit mode (though maybe in a 32-bit code segment).
11495 		 * CR4.PAE and EFER.LMA must be set.
11496 		 */
11497 		if (!(sregs->cr4 & X86_CR4_PAE) || !(sregs->efer & EFER_LMA))
11498 			return false;
11499 		if (kvm_vcpu_is_illegal_gpa(vcpu, sregs->cr3))
11500 			return false;
11501 	} else {
11502 		/*
11503 		 * Not in 64-bit mode: EFER.LMA is clear and the code
11504 		 * segment cannot be 64-bit.
11505 		 */
11506 		if (sregs->efer & EFER_LMA || sregs->cs.l)
11507 			return false;
11508 	}
11509 
11510 	return kvm_is_valid_cr4(vcpu, sregs->cr4) &&
11511 	       kvm_is_valid_cr0(vcpu, sregs->cr0);
11512 }
11513 
__set_sregs_common(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs,int * mmu_reset_needed,bool update_pdptrs)11514 static int __set_sregs_common(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs,
11515 		int *mmu_reset_needed, bool update_pdptrs)
11516 {
11517 	struct msr_data apic_base_msr;
11518 	int idx;
11519 	struct desc_ptr dt;
11520 
11521 	if (!kvm_is_valid_sregs(vcpu, sregs))
11522 		return -EINVAL;
11523 
11524 	apic_base_msr.data = sregs->apic_base;
11525 	apic_base_msr.host_initiated = true;
11526 	if (kvm_set_apic_base(vcpu, &apic_base_msr))
11527 		return -EINVAL;
11528 
11529 	if (vcpu->arch.guest_state_protected)
11530 		return 0;
11531 
11532 	dt.size = sregs->idt.limit;
11533 	dt.address = sregs->idt.base;
11534 	static_call(kvm_x86_set_idt)(vcpu, &dt);
11535 	dt.size = sregs->gdt.limit;
11536 	dt.address = sregs->gdt.base;
11537 	static_call(kvm_x86_set_gdt)(vcpu, &dt);
11538 
11539 	vcpu->arch.cr2 = sregs->cr2;
11540 	*mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
11541 	vcpu->arch.cr3 = sregs->cr3;
11542 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
11543 	static_call_cond(kvm_x86_post_set_cr3)(vcpu, sregs->cr3);
11544 
11545 	kvm_set_cr8(vcpu, sregs->cr8);
11546 
11547 	*mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
11548 	static_call(kvm_x86_set_efer)(vcpu, sregs->efer);
11549 
11550 	*mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
11551 	static_call(kvm_x86_set_cr0)(vcpu, sregs->cr0);
11552 	vcpu->arch.cr0 = sregs->cr0;
11553 
11554 	*mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
11555 	static_call(kvm_x86_set_cr4)(vcpu, sregs->cr4);
11556 
11557 	if (update_pdptrs) {
11558 		idx = srcu_read_lock(&vcpu->kvm->srcu);
11559 		if (is_pae_paging(vcpu)) {
11560 			load_pdptrs(vcpu, kvm_read_cr3(vcpu));
11561 			*mmu_reset_needed = 1;
11562 		}
11563 		srcu_read_unlock(&vcpu->kvm->srcu, idx);
11564 	}
11565 
11566 	kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
11567 	kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
11568 	kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
11569 	kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
11570 	kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
11571 	kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
11572 
11573 	kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
11574 	kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
11575 
11576 	update_cr8_intercept(vcpu);
11577 
11578 	/* Older userspace won't unhalt the vcpu on reset. */
11579 	if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
11580 	    sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
11581 	    !is_protmode(vcpu))
11582 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11583 
11584 	return 0;
11585 }
11586 
__set_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11587 static int __set_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
11588 {
11589 	int pending_vec, max_bits;
11590 	int mmu_reset_needed = 0;
11591 	int ret = __set_sregs_common(vcpu, sregs, &mmu_reset_needed, true);
11592 
11593 	if (ret)
11594 		return ret;
11595 
11596 	if (mmu_reset_needed)
11597 		kvm_mmu_reset_context(vcpu);
11598 
11599 	max_bits = KVM_NR_INTERRUPTS;
11600 	pending_vec = find_first_bit(
11601 		(const unsigned long *)sregs->interrupt_bitmap, max_bits);
11602 
11603 	if (pending_vec < max_bits) {
11604 		kvm_queue_interrupt(vcpu, pending_vec, false);
11605 		pr_debug("Set back pending irq %d\n", pending_vec);
11606 		kvm_make_request(KVM_REQ_EVENT, vcpu);
11607 	}
11608 	return 0;
11609 }
11610 
__set_sregs2(struct kvm_vcpu * vcpu,struct kvm_sregs2 * sregs2)11611 static int __set_sregs2(struct kvm_vcpu *vcpu, struct kvm_sregs2 *sregs2)
11612 {
11613 	int mmu_reset_needed = 0;
11614 	bool valid_pdptrs = sregs2->flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
11615 	bool pae = (sregs2->cr0 & X86_CR0_PG) && (sregs2->cr4 & X86_CR4_PAE) &&
11616 		!(sregs2->efer & EFER_LMA);
11617 	int i, ret;
11618 
11619 	if (sregs2->flags & ~KVM_SREGS2_FLAGS_PDPTRS_VALID)
11620 		return -EINVAL;
11621 
11622 	if (valid_pdptrs && (!pae || vcpu->arch.guest_state_protected))
11623 		return -EINVAL;
11624 
11625 	ret = __set_sregs_common(vcpu, (struct kvm_sregs *)sregs2,
11626 				 &mmu_reset_needed, !valid_pdptrs);
11627 	if (ret)
11628 		return ret;
11629 
11630 	if (valid_pdptrs) {
11631 		for (i = 0; i < 4 ; i++)
11632 			kvm_pdptr_write(vcpu, i, sregs2->pdptrs[i]);
11633 
11634 		kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR);
11635 		mmu_reset_needed = 1;
11636 		vcpu->arch.pdptrs_from_userspace = true;
11637 	}
11638 	if (mmu_reset_needed)
11639 		kvm_mmu_reset_context(vcpu);
11640 	return 0;
11641 }
11642 
kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu * vcpu,struct kvm_sregs * sregs)11643 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
11644 				  struct kvm_sregs *sregs)
11645 {
11646 	int ret;
11647 
11648 	vcpu_load(vcpu);
11649 	ret = __set_sregs(vcpu, sregs);
11650 	vcpu_put(vcpu);
11651 	return ret;
11652 }
11653 
kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm * kvm)11654 static void kvm_arch_vcpu_guestdbg_update_apicv_inhibit(struct kvm *kvm)
11655 {
11656 	bool set = false;
11657 	struct kvm_vcpu *vcpu;
11658 	unsigned long i;
11659 
11660 	if (!enable_apicv)
11661 		return;
11662 
11663 	down_write(&kvm->arch.apicv_update_lock);
11664 
11665 	kvm_for_each_vcpu(i, vcpu, kvm) {
11666 		if (vcpu->guest_debug & KVM_GUESTDBG_BLOCKIRQ) {
11667 			set = true;
11668 			break;
11669 		}
11670 	}
11671 	__kvm_set_or_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_BLOCKIRQ, set);
11672 	up_write(&kvm->arch.apicv_update_lock);
11673 }
11674 
kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu * vcpu,struct kvm_guest_debug * dbg)11675 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
11676 					struct kvm_guest_debug *dbg)
11677 {
11678 	unsigned long rflags;
11679 	int i, r;
11680 
11681 	if (vcpu->arch.guest_state_protected)
11682 		return -EINVAL;
11683 
11684 	vcpu_load(vcpu);
11685 
11686 	if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
11687 		r = -EBUSY;
11688 		if (kvm_is_exception_pending(vcpu))
11689 			goto out;
11690 		if (dbg->control & KVM_GUESTDBG_INJECT_DB)
11691 			kvm_queue_exception(vcpu, DB_VECTOR);
11692 		else
11693 			kvm_queue_exception(vcpu, BP_VECTOR);
11694 	}
11695 
11696 	/*
11697 	 * Read rflags as long as potentially injected trace flags are still
11698 	 * filtered out.
11699 	 */
11700 	rflags = kvm_get_rflags(vcpu);
11701 
11702 	vcpu->guest_debug = dbg->control;
11703 	if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
11704 		vcpu->guest_debug = 0;
11705 
11706 	if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
11707 		for (i = 0; i < KVM_NR_DB_REGS; ++i)
11708 			vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
11709 		vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
11710 	} else {
11711 		for (i = 0; i < KVM_NR_DB_REGS; i++)
11712 			vcpu->arch.eff_db[i] = vcpu->arch.db[i];
11713 	}
11714 	kvm_update_dr7(vcpu);
11715 
11716 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
11717 		vcpu->arch.singlestep_rip = kvm_get_linear_rip(vcpu);
11718 
11719 	/*
11720 	 * Trigger an rflags update that will inject or remove the trace
11721 	 * flags.
11722 	 */
11723 	kvm_set_rflags(vcpu, rflags);
11724 
11725 	static_call(kvm_x86_update_exception_bitmap)(vcpu);
11726 
11727 	kvm_arch_vcpu_guestdbg_update_apicv_inhibit(vcpu->kvm);
11728 
11729 	r = 0;
11730 
11731 out:
11732 	vcpu_put(vcpu);
11733 	return r;
11734 }
11735 
11736 /*
11737  * Translate a guest virtual address to a guest physical address.
11738  */
kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu * vcpu,struct kvm_translation * tr)11739 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
11740 				    struct kvm_translation *tr)
11741 {
11742 	unsigned long vaddr = tr->linear_address;
11743 	gpa_t gpa;
11744 	int idx;
11745 
11746 	vcpu_load(vcpu);
11747 
11748 	idx = srcu_read_lock(&vcpu->kvm->srcu);
11749 	gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
11750 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
11751 	tr->physical_address = gpa;
11752 	tr->valid = gpa != INVALID_GPA;
11753 	tr->writeable = 1;
11754 	tr->usermode = 0;
11755 
11756 	vcpu_put(vcpu);
11757 	return 0;
11758 }
11759 
kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)11760 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11761 {
11762 	struct fxregs_state *fxsave;
11763 
11764 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11765 		return 0;
11766 
11767 	vcpu_load(vcpu);
11768 
11769 	fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11770 	memcpy(fpu->fpr, fxsave->st_space, 128);
11771 	fpu->fcw = fxsave->cwd;
11772 	fpu->fsw = fxsave->swd;
11773 	fpu->ftwx = fxsave->twd;
11774 	fpu->last_opcode = fxsave->fop;
11775 	fpu->last_ip = fxsave->rip;
11776 	fpu->last_dp = fxsave->rdp;
11777 	memcpy(fpu->xmm, fxsave->xmm_space, sizeof(fxsave->xmm_space));
11778 
11779 	vcpu_put(vcpu);
11780 	return 0;
11781 }
11782 
kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu * vcpu,struct kvm_fpu * fpu)11783 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
11784 {
11785 	struct fxregs_state *fxsave;
11786 
11787 	if (fpstate_is_confidential(&vcpu->arch.guest_fpu))
11788 		return 0;
11789 
11790 	vcpu_load(vcpu);
11791 
11792 	fxsave = &vcpu->arch.guest_fpu.fpstate->regs.fxsave;
11793 
11794 	memcpy(fxsave->st_space, fpu->fpr, 128);
11795 	fxsave->cwd = fpu->fcw;
11796 	fxsave->swd = fpu->fsw;
11797 	fxsave->twd = fpu->ftwx;
11798 	fxsave->fop = fpu->last_opcode;
11799 	fxsave->rip = fpu->last_ip;
11800 	fxsave->rdp = fpu->last_dp;
11801 	memcpy(fxsave->xmm_space, fpu->xmm, sizeof(fxsave->xmm_space));
11802 
11803 	vcpu_put(vcpu);
11804 	return 0;
11805 }
11806 
store_regs(struct kvm_vcpu * vcpu)11807 static void store_regs(struct kvm_vcpu *vcpu)
11808 {
11809 	BUILD_BUG_ON(sizeof(struct kvm_sync_regs) > SYNC_REGS_SIZE_BYTES);
11810 
11811 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_REGS)
11812 		__get_regs(vcpu, &vcpu->run->s.regs.regs);
11813 
11814 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_SREGS)
11815 		__get_sregs(vcpu, &vcpu->run->s.regs.sregs);
11816 
11817 	if (vcpu->run->kvm_valid_regs & KVM_SYNC_X86_EVENTS)
11818 		kvm_vcpu_ioctl_x86_get_vcpu_events(
11819 				vcpu, &vcpu->run->s.regs.events);
11820 }
11821 
sync_regs(struct kvm_vcpu * vcpu)11822 static int sync_regs(struct kvm_vcpu *vcpu)
11823 {
11824 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_REGS) {
11825 		__set_regs(vcpu, &vcpu->run->s.regs.regs);
11826 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_REGS;
11827 	}
11828 
11829 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_SREGS) {
11830 		struct kvm_sregs sregs = vcpu->run->s.regs.sregs;
11831 
11832 		if (__set_sregs(vcpu, &sregs))
11833 			return -EINVAL;
11834 
11835 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_SREGS;
11836 	}
11837 
11838 	if (vcpu->run->kvm_dirty_regs & KVM_SYNC_X86_EVENTS) {
11839 		struct kvm_vcpu_events events = vcpu->run->s.regs.events;
11840 
11841 		if (kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events))
11842 			return -EINVAL;
11843 
11844 		vcpu->run->kvm_dirty_regs &= ~KVM_SYNC_X86_EVENTS;
11845 	}
11846 
11847 	return 0;
11848 }
11849 
kvm_arch_vcpu_precreate(struct kvm * kvm,unsigned int id)11850 int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
11851 {
11852 	if (kvm_check_tsc_unstable() && kvm->created_vcpus)
11853 		pr_warn_once("SMP vm created on host with unstable TSC; "
11854 			     "guest TSC will not be reliable\n");
11855 
11856 	if (!kvm->arch.max_vcpu_ids)
11857 		kvm->arch.max_vcpu_ids = KVM_MAX_VCPU_IDS;
11858 
11859 	if (id >= kvm->arch.max_vcpu_ids)
11860 		return -EINVAL;
11861 
11862 	return static_call(kvm_x86_vcpu_precreate)(kvm);
11863 }
11864 
kvm_arch_vcpu_create(struct kvm_vcpu * vcpu)11865 int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
11866 {
11867 	struct page *page;
11868 	int r;
11869 
11870 	vcpu->arch.last_vmentry_cpu = -1;
11871 	vcpu->arch.regs_avail = ~0;
11872 	vcpu->arch.regs_dirty = ~0;
11873 
11874 	kvm_gpc_init(&vcpu->arch.pv_time, vcpu->kvm, vcpu, KVM_HOST_USES_PFN);
11875 
11876 	if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
11877 		vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
11878 	else
11879 		vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
11880 
11881 	r = kvm_mmu_create(vcpu);
11882 	if (r < 0)
11883 		return r;
11884 
11885 	if (irqchip_in_kernel(vcpu->kvm)) {
11886 		r = kvm_create_lapic(vcpu, lapic_timer_advance_ns);
11887 		if (r < 0)
11888 			goto fail_mmu_destroy;
11889 
11890 		/*
11891 		 * Defer evaluating inhibits until the vCPU is first run, as
11892 		 * this vCPU will not get notified of any changes until this
11893 		 * vCPU is visible to other vCPUs (marked online and added to
11894 		 * the set of vCPUs).  Opportunistically mark APICv active as
11895 		 * VMX in particularly is highly unlikely to have inhibits.
11896 		 * Ignore the current per-VM APICv state so that vCPU creation
11897 		 * is guaranteed to run with a deterministic value, the request
11898 		 * will ensure the vCPU gets the correct state before VM-Entry.
11899 		 */
11900 		if (enable_apicv) {
11901 			vcpu->arch.apic->apicv_active = true;
11902 			kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
11903 		}
11904 	} else
11905 		static_branch_inc(&kvm_has_noapic_vcpu);
11906 
11907 	r = -ENOMEM;
11908 
11909 	page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
11910 	if (!page)
11911 		goto fail_free_lapic;
11912 	vcpu->arch.pio_data = page_address(page);
11913 
11914 	vcpu->arch.mce_banks = kcalloc(KVM_MAX_MCE_BANKS * 4, sizeof(u64),
11915 				       GFP_KERNEL_ACCOUNT);
11916 	vcpu->arch.mci_ctl2_banks = kcalloc(KVM_MAX_MCE_BANKS, sizeof(u64),
11917 					    GFP_KERNEL_ACCOUNT);
11918 	if (!vcpu->arch.mce_banks || !vcpu->arch.mci_ctl2_banks)
11919 		goto fail_free_mce_banks;
11920 	vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
11921 
11922 	if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask,
11923 				GFP_KERNEL_ACCOUNT))
11924 		goto fail_free_mce_banks;
11925 
11926 	if (!alloc_emulate_ctxt(vcpu))
11927 		goto free_wbinvd_dirty_mask;
11928 
11929 	if (!fpu_alloc_guest_fpstate(&vcpu->arch.guest_fpu)) {
11930 		pr_err("failed to allocate vcpu's fpu\n");
11931 		goto free_emulate_ctxt;
11932 	}
11933 
11934 	vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
11935 	vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
11936 
11937 	vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
11938 
11939 	kvm_async_pf_hash_reset(vcpu);
11940 
11941 	vcpu->arch.perf_capabilities = kvm_caps.supported_perf_cap;
11942 	kvm_pmu_init(vcpu);
11943 
11944 	vcpu->arch.pending_external_vector = -1;
11945 	vcpu->arch.preempted_in_kernel = false;
11946 
11947 #if IS_ENABLED(CONFIG_HYPERV)
11948 	vcpu->arch.hv_root_tdp = INVALID_PAGE;
11949 #endif
11950 
11951 	r = static_call(kvm_x86_vcpu_create)(vcpu);
11952 	if (r)
11953 		goto free_guest_fpu;
11954 
11955 	vcpu->arch.arch_capabilities = kvm_get_arch_capabilities();
11956 	vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
11957 	kvm_xen_init_vcpu(vcpu);
11958 	kvm_vcpu_mtrr_init(vcpu);
11959 	vcpu_load(vcpu);
11960 	kvm_set_tsc_khz(vcpu, vcpu->kvm->arch.default_tsc_khz);
11961 	kvm_vcpu_reset(vcpu, false);
11962 	kvm_init_mmu(vcpu);
11963 	vcpu_put(vcpu);
11964 	return 0;
11965 
11966 free_guest_fpu:
11967 	fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
11968 free_emulate_ctxt:
11969 	kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
11970 free_wbinvd_dirty_mask:
11971 	free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
11972 fail_free_mce_banks:
11973 	kfree(vcpu->arch.mce_banks);
11974 	kfree(vcpu->arch.mci_ctl2_banks);
11975 	free_page((unsigned long)vcpu->arch.pio_data);
11976 fail_free_lapic:
11977 	kvm_free_lapic(vcpu);
11978 fail_mmu_destroy:
11979 	kvm_mmu_destroy(vcpu);
11980 	return r;
11981 }
11982 
kvm_arch_vcpu_postcreate(struct kvm_vcpu * vcpu)11983 void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
11984 {
11985 	struct kvm *kvm = vcpu->kvm;
11986 
11987 	if (mutex_lock_killable(&vcpu->mutex))
11988 		return;
11989 	vcpu_load(vcpu);
11990 	kvm_synchronize_tsc(vcpu, 0);
11991 	vcpu_put(vcpu);
11992 
11993 	/* poll control enabled by default */
11994 	vcpu->arch.msr_kvm_poll_control = 1;
11995 
11996 	mutex_unlock(&vcpu->mutex);
11997 
11998 	if (kvmclock_periodic_sync && vcpu->vcpu_idx == 0)
11999 		schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
12000 						KVMCLOCK_SYNC_PERIOD);
12001 }
12002 
kvm_arch_vcpu_destroy(struct kvm_vcpu * vcpu)12003 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
12004 {
12005 	int idx;
12006 
12007 	kvmclock_reset(vcpu);
12008 
12009 	static_call(kvm_x86_vcpu_free)(vcpu);
12010 
12011 	kmem_cache_free(x86_emulator_cache, vcpu->arch.emulate_ctxt);
12012 	free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
12013 	fpu_free_guest_fpstate(&vcpu->arch.guest_fpu);
12014 
12015 	kvm_xen_destroy_vcpu(vcpu);
12016 	kvm_hv_vcpu_uninit(vcpu);
12017 	kvm_pmu_destroy(vcpu);
12018 	kfree(vcpu->arch.mce_banks);
12019 	kfree(vcpu->arch.mci_ctl2_banks);
12020 	kvm_free_lapic(vcpu);
12021 	idx = srcu_read_lock(&vcpu->kvm->srcu);
12022 	kvm_mmu_destroy(vcpu);
12023 	srcu_read_unlock(&vcpu->kvm->srcu, idx);
12024 	free_page((unsigned long)vcpu->arch.pio_data);
12025 	kvfree(vcpu->arch.cpuid_entries);
12026 	if (!lapic_in_kernel(vcpu))
12027 		static_branch_dec(&kvm_has_noapic_vcpu);
12028 }
12029 
kvm_vcpu_reset(struct kvm_vcpu * vcpu,bool init_event)12030 void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
12031 {
12032 	struct kvm_cpuid_entry2 *cpuid_0x1;
12033 	unsigned long old_cr0 = kvm_read_cr0(vcpu);
12034 	unsigned long new_cr0;
12035 
12036 	/*
12037 	 * Several of the "set" flows, e.g. ->set_cr0(), read other registers
12038 	 * to handle side effects.  RESET emulation hits those flows and relies
12039 	 * on emulated/virtualized registers, including those that are loaded
12040 	 * into hardware, to be zeroed at vCPU creation.  Use CRs as a sentinel
12041 	 * to detect improper or missing initialization.
12042 	 */
12043 	WARN_ON_ONCE(!init_event &&
12044 		     (old_cr0 || kvm_read_cr3(vcpu) || kvm_read_cr4(vcpu)));
12045 
12046 	/*
12047 	 * SVM doesn't unconditionally VM-Exit on INIT and SHUTDOWN, thus it's
12048 	 * possible to INIT the vCPU while L2 is active.  Force the vCPU back
12049 	 * into L1 as EFER.SVME is cleared on INIT (along with all other EFER
12050 	 * bits), i.e. virtualization is disabled.
12051 	 */
12052 	if (is_guest_mode(vcpu))
12053 		kvm_leave_nested(vcpu);
12054 
12055 	kvm_lapic_reset(vcpu, init_event);
12056 
12057 	WARN_ON_ONCE(is_guest_mode(vcpu) || is_smm(vcpu));
12058 	vcpu->arch.hflags = 0;
12059 
12060 	vcpu->arch.smi_pending = 0;
12061 	vcpu->arch.smi_count = 0;
12062 	atomic_set(&vcpu->arch.nmi_queued, 0);
12063 	vcpu->arch.nmi_pending = 0;
12064 	vcpu->arch.nmi_injected = false;
12065 	kvm_clear_interrupt_queue(vcpu);
12066 	kvm_clear_exception_queue(vcpu);
12067 
12068 	memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
12069 	kvm_update_dr0123(vcpu);
12070 	vcpu->arch.dr6 = DR6_ACTIVE_LOW;
12071 	vcpu->arch.dr7 = DR7_FIXED_1;
12072 	kvm_update_dr7(vcpu);
12073 
12074 	vcpu->arch.cr2 = 0;
12075 
12076 	kvm_make_request(KVM_REQ_EVENT, vcpu);
12077 	vcpu->arch.apf.msr_en_val = 0;
12078 	vcpu->arch.apf.msr_int_val = 0;
12079 	vcpu->arch.st.msr_val = 0;
12080 
12081 	kvmclock_reset(vcpu);
12082 
12083 	kvm_clear_async_pf_completion_queue(vcpu);
12084 	kvm_async_pf_hash_reset(vcpu);
12085 	vcpu->arch.apf.halted = false;
12086 
12087 	if (vcpu->arch.guest_fpu.fpstate && kvm_mpx_supported()) {
12088 		struct fpstate *fpstate = vcpu->arch.guest_fpu.fpstate;
12089 
12090 		/*
12091 		 * All paths that lead to INIT are required to load the guest's
12092 		 * FPU state (because most paths are buried in KVM_RUN).
12093 		 */
12094 		if (init_event)
12095 			kvm_put_guest_fpu(vcpu);
12096 
12097 		fpstate_clear_xstate_component(fpstate, XFEATURE_BNDREGS);
12098 		fpstate_clear_xstate_component(fpstate, XFEATURE_BNDCSR);
12099 
12100 		if (init_event)
12101 			kvm_load_guest_fpu(vcpu);
12102 	}
12103 
12104 	if (!init_event) {
12105 		kvm_pmu_reset(vcpu);
12106 		vcpu->arch.smbase = 0x30000;
12107 
12108 		vcpu->arch.msr_misc_features_enables = 0;
12109 		vcpu->arch.ia32_misc_enable_msr = MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
12110 						  MSR_IA32_MISC_ENABLE_BTS_UNAVAIL;
12111 
12112 		__kvm_set_xcr(vcpu, 0, XFEATURE_MASK_FP);
12113 		__kvm_set_msr(vcpu, MSR_IA32_XSS, 0, true);
12114 	}
12115 
12116 	/* All GPRs except RDX (handled below) are zeroed on RESET/INIT. */
12117 	memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
12118 	kvm_register_mark_dirty(vcpu, VCPU_REGS_RSP);
12119 
12120 	/*
12121 	 * Fall back to KVM's default Family/Model/Stepping of 0x600 (P6/Athlon)
12122 	 * if no CPUID match is found.  Note, it's impossible to get a match at
12123 	 * RESET since KVM emulates RESET before exposing the vCPU to userspace,
12124 	 * i.e. it's impossible for kvm_find_cpuid_entry() to find a valid entry
12125 	 * on RESET.  But, go through the motions in case that's ever remedied.
12126 	 */
12127 	cpuid_0x1 = kvm_find_cpuid_entry(vcpu, 1);
12128 	kvm_rdx_write(vcpu, cpuid_0x1 ? cpuid_0x1->eax : 0x600);
12129 
12130 	static_call(kvm_x86_vcpu_reset)(vcpu, init_event);
12131 
12132 	kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
12133 	kvm_rip_write(vcpu, 0xfff0);
12134 
12135 	vcpu->arch.cr3 = 0;
12136 	kvm_register_mark_dirty(vcpu, VCPU_EXREG_CR3);
12137 
12138 	/*
12139 	 * CR0.CD/NW are set on RESET, preserved on INIT.  Note, some versions
12140 	 * of Intel's SDM list CD/NW as being set on INIT, but they contradict
12141 	 * (or qualify) that with a footnote stating that CD/NW are preserved.
12142 	 */
12143 	new_cr0 = X86_CR0_ET;
12144 	if (init_event)
12145 		new_cr0 |= (old_cr0 & (X86_CR0_NW | X86_CR0_CD));
12146 	else
12147 		new_cr0 |= X86_CR0_NW | X86_CR0_CD;
12148 
12149 	static_call(kvm_x86_set_cr0)(vcpu, new_cr0);
12150 	static_call(kvm_x86_set_cr4)(vcpu, 0);
12151 	static_call(kvm_x86_set_efer)(vcpu, 0);
12152 	static_call(kvm_x86_update_exception_bitmap)(vcpu);
12153 
12154 	/*
12155 	 * On the standard CR0/CR4/EFER modification paths, there are several
12156 	 * complex conditions determining whether the MMU has to be reset and/or
12157 	 * which PCIDs have to be flushed.  However, CR0.WP and the paging-related
12158 	 * bits in CR4 and EFER are irrelevant if CR0.PG was '0'; and a reset+flush
12159 	 * is needed anyway if CR0.PG was '1' (which can only happen for INIT, as
12160 	 * CR0 will be '0' prior to RESET).  So we only need to check CR0.PG here.
12161 	 */
12162 	if (old_cr0 & X86_CR0_PG) {
12163 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12164 		kvm_mmu_reset_context(vcpu);
12165 	}
12166 
12167 	/*
12168 	 * Intel's SDM states that all TLB entries are flushed on INIT.  AMD's
12169 	 * APM states the TLBs are untouched by INIT, but it also states that
12170 	 * the TLBs are flushed on "External initialization of the processor."
12171 	 * Flush the guest TLB regardless of vendor, there is no meaningful
12172 	 * benefit in relying on the guest to flush the TLB immediately after
12173 	 * INIT.  A spurious TLB flush is benign and likely negligible from a
12174 	 * performance perspective.
12175 	 */
12176 	if (init_event)
12177 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
12178 }
12179 EXPORT_SYMBOL_GPL(kvm_vcpu_reset);
12180 
kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu * vcpu,u8 vector)12181 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
12182 {
12183 	struct kvm_segment cs;
12184 
12185 	kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
12186 	cs.selector = vector << 8;
12187 	cs.base = vector << 12;
12188 	kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
12189 	kvm_rip_write(vcpu, 0);
12190 }
12191 EXPORT_SYMBOL_GPL(kvm_vcpu_deliver_sipi_vector);
12192 
kvm_arch_hardware_enable(void)12193 int kvm_arch_hardware_enable(void)
12194 {
12195 	struct kvm *kvm;
12196 	struct kvm_vcpu *vcpu;
12197 	unsigned long i;
12198 	int ret;
12199 	u64 local_tsc;
12200 	u64 max_tsc = 0;
12201 	bool stable, backwards_tsc = false;
12202 
12203 	kvm_user_return_msr_cpu_online();
12204 
12205 	ret = kvm_x86_check_processor_compatibility();
12206 	if (ret)
12207 		return ret;
12208 
12209 	ret = static_call(kvm_x86_hardware_enable)();
12210 	if (ret != 0)
12211 		return ret;
12212 
12213 	local_tsc = rdtsc();
12214 	stable = !kvm_check_tsc_unstable();
12215 	list_for_each_entry(kvm, &vm_list, vm_list) {
12216 		kvm_for_each_vcpu(i, vcpu, kvm) {
12217 			if (!stable && vcpu->cpu == smp_processor_id())
12218 				kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
12219 			if (stable && vcpu->arch.last_host_tsc > local_tsc) {
12220 				backwards_tsc = true;
12221 				if (vcpu->arch.last_host_tsc > max_tsc)
12222 					max_tsc = vcpu->arch.last_host_tsc;
12223 			}
12224 		}
12225 	}
12226 
12227 	/*
12228 	 * Sometimes, even reliable TSCs go backwards.  This happens on
12229 	 * platforms that reset TSC during suspend or hibernate actions, but
12230 	 * maintain synchronization.  We must compensate.  Fortunately, we can
12231 	 * detect that condition here, which happens early in CPU bringup,
12232 	 * before any KVM threads can be running.  Unfortunately, we can't
12233 	 * bring the TSCs fully up to date with real time, as we aren't yet far
12234 	 * enough into CPU bringup that we know how much real time has actually
12235 	 * elapsed; our helper function, ktime_get_boottime_ns() will be using boot
12236 	 * variables that haven't been updated yet.
12237 	 *
12238 	 * So we simply find the maximum observed TSC above, then record the
12239 	 * adjustment to TSC in each VCPU.  When the VCPU later gets loaded,
12240 	 * the adjustment will be applied.  Note that we accumulate
12241 	 * adjustments, in case multiple suspend cycles happen before some VCPU
12242 	 * gets a chance to run again.  In the event that no KVM threads get a
12243 	 * chance to run, we will miss the entire elapsed period, as we'll have
12244 	 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
12245 	 * loose cycle time.  This isn't too big a deal, since the loss will be
12246 	 * uniform across all VCPUs (not to mention the scenario is extremely
12247 	 * unlikely). It is possible that a second hibernate recovery happens
12248 	 * much faster than a first, causing the observed TSC here to be
12249 	 * smaller; this would require additional padding adjustment, which is
12250 	 * why we set last_host_tsc to the local tsc observed here.
12251 	 *
12252 	 * N.B. - this code below runs only on platforms with reliable TSC,
12253 	 * as that is the only way backwards_tsc is set above.  Also note
12254 	 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
12255 	 * have the same delta_cyc adjustment applied if backwards_tsc
12256 	 * is detected.  Note further, this adjustment is only done once,
12257 	 * as we reset last_host_tsc on all VCPUs to stop this from being
12258 	 * called multiple times (one for each physical CPU bringup).
12259 	 *
12260 	 * Platforms with unreliable TSCs don't have to deal with this, they
12261 	 * will be compensated by the logic in vcpu_load, which sets the TSC to
12262 	 * catchup mode.  This will catchup all VCPUs to real time, but cannot
12263 	 * guarantee that they stay in perfect synchronization.
12264 	 */
12265 	if (backwards_tsc) {
12266 		u64 delta_cyc = max_tsc - local_tsc;
12267 		list_for_each_entry(kvm, &vm_list, vm_list) {
12268 			kvm->arch.backwards_tsc_observed = true;
12269 			kvm_for_each_vcpu(i, vcpu, kvm) {
12270 				vcpu->arch.tsc_offset_adjustment += delta_cyc;
12271 				vcpu->arch.last_host_tsc = local_tsc;
12272 				kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
12273 			}
12274 
12275 			/*
12276 			 * We have to disable TSC offset matching.. if you were
12277 			 * booting a VM while issuing an S4 host suspend....
12278 			 * you may have some problem.  Solving this issue is
12279 			 * left as an exercise to the reader.
12280 			 */
12281 			kvm->arch.last_tsc_nsec = 0;
12282 			kvm->arch.last_tsc_write = 0;
12283 		}
12284 
12285 	}
12286 	return 0;
12287 }
12288 
kvm_arch_hardware_disable(void)12289 void kvm_arch_hardware_disable(void)
12290 {
12291 	static_call(kvm_x86_hardware_disable)();
12292 	drop_user_return_notifiers();
12293 }
12294 
kvm_vcpu_is_reset_bsp(struct kvm_vcpu * vcpu)12295 bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
12296 {
12297 	return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
12298 }
12299 
kvm_vcpu_is_bsp(struct kvm_vcpu * vcpu)12300 bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
12301 {
12302 	return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
12303 }
12304 
12305 __read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
12306 EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
12307 
kvm_arch_sched_in(struct kvm_vcpu * vcpu,int cpu)12308 void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
12309 {
12310 	struct kvm_pmu *pmu = vcpu_to_pmu(vcpu);
12311 
12312 	vcpu->arch.l1tf_flush_l1d = true;
12313 	if (pmu->version && unlikely(pmu->event_count)) {
12314 		pmu->need_cleanup = true;
12315 		kvm_make_request(KVM_REQ_PMU, vcpu);
12316 	}
12317 	static_call(kvm_x86_sched_in)(vcpu, cpu);
12318 }
12319 
kvm_arch_free_vm(struct kvm * kvm)12320 void kvm_arch_free_vm(struct kvm *kvm)
12321 {
12322 	kfree(to_kvm_hv(kvm)->hv_pa_pg);
12323 	__kvm_arch_free_vm(kvm);
12324 }
12325 
12326 
kvm_arch_init_vm(struct kvm * kvm,unsigned long type)12327 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
12328 {
12329 	int ret;
12330 	unsigned long flags;
12331 
12332 	if (type)
12333 		return -EINVAL;
12334 
12335 	ret = kvm_page_track_init(kvm);
12336 	if (ret)
12337 		goto out;
12338 
12339 	kvm_mmu_init_vm(kvm);
12340 
12341 	ret = static_call(kvm_x86_vm_init)(kvm);
12342 	if (ret)
12343 		goto out_uninit_mmu;
12344 
12345 	INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
12346 	INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
12347 	atomic_set(&kvm->arch.noncoherent_dma_count, 0);
12348 
12349 	/* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
12350 	set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
12351 	/* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
12352 	set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
12353 		&kvm->arch.irq_sources_bitmap);
12354 
12355 	raw_spin_lock_init(&kvm->arch.tsc_write_lock);
12356 	mutex_init(&kvm->arch.apic_map_lock);
12357 	seqcount_raw_spinlock_init(&kvm->arch.pvclock_sc, &kvm->arch.tsc_write_lock);
12358 	kvm->arch.kvmclock_offset = -get_kvmclock_base_ns();
12359 
12360 	raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
12361 	pvclock_update_vm_gtod_copy(kvm);
12362 	raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
12363 
12364 	kvm->arch.default_tsc_khz = max_tsc_khz ? : tsc_khz;
12365 	kvm->arch.guest_can_read_msr_platform_info = true;
12366 	kvm->arch.enable_pmu = enable_pmu;
12367 
12368 #if IS_ENABLED(CONFIG_HYPERV)
12369 	spin_lock_init(&kvm->arch.hv_root_tdp_lock);
12370 	kvm->arch.hv_root_tdp = INVALID_PAGE;
12371 #endif
12372 
12373 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
12374 	INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
12375 
12376 	kvm_apicv_init(kvm);
12377 	kvm_hv_init_vm(kvm);
12378 	kvm_xen_init_vm(kvm);
12379 
12380 	return 0;
12381 
12382 out_uninit_mmu:
12383 	kvm_mmu_uninit_vm(kvm);
12384 	kvm_page_track_cleanup(kvm);
12385 out:
12386 	return ret;
12387 }
12388 
kvm_arch_post_init_vm(struct kvm * kvm)12389 int kvm_arch_post_init_vm(struct kvm *kvm)
12390 {
12391 	return kvm_mmu_post_init_vm(kvm);
12392 }
12393 
kvm_unload_vcpu_mmu(struct kvm_vcpu * vcpu)12394 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
12395 {
12396 	vcpu_load(vcpu);
12397 	kvm_mmu_unload(vcpu);
12398 	vcpu_put(vcpu);
12399 }
12400 
kvm_unload_vcpu_mmus(struct kvm * kvm)12401 static void kvm_unload_vcpu_mmus(struct kvm *kvm)
12402 {
12403 	unsigned long i;
12404 	struct kvm_vcpu *vcpu;
12405 
12406 	kvm_for_each_vcpu(i, vcpu, kvm) {
12407 		kvm_clear_async_pf_completion_queue(vcpu);
12408 		kvm_unload_vcpu_mmu(vcpu);
12409 	}
12410 }
12411 
kvm_arch_sync_events(struct kvm * kvm)12412 void kvm_arch_sync_events(struct kvm *kvm)
12413 {
12414 	cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
12415 	cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
12416 	kvm_free_pit(kvm);
12417 }
12418 
12419 /**
12420  * __x86_set_memory_region: Setup KVM internal memory slot
12421  *
12422  * @kvm: the kvm pointer to the VM.
12423  * @id: the slot ID to setup.
12424  * @gpa: the GPA to install the slot (unused when @size == 0).
12425  * @size: the size of the slot. Set to zero to uninstall a slot.
12426  *
12427  * This function helps to setup a KVM internal memory slot.  Specify
12428  * @size > 0 to install a new slot, while @size == 0 to uninstall a
12429  * slot.  The return code can be one of the following:
12430  *
12431  *   HVA:           on success (uninstall will return a bogus HVA)
12432  *   -errno:        on error
12433  *
12434  * The caller should always use IS_ERR() to check the return value
12435  * before use.  Note, the KVM internal memory slots are guaranteed to
12436  * remain valid and unchanged until the VM is destroyed, i.e., the
12437  * GPA->HVA translation will not change.  However, the HVA is a user
12438  * address, i.e. its accessibility is not guaranteed, and must be
12439  * accessed via __copy_{to,from}_user().
12440  */
__x86_set_memory_region(struct kvm * kvm,int id,gpa_t gpa,u32 size)12441 void __user * __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa,
12442 				      u32 size)
12443 {
12444 	int i, r;
12445 	unsigned long hva, old_npages;
12446 	struct kvm_memslots *slots = kvm_memslots(kvm);
12447 	struct kvm_memory_slot *slot;
12448 
12449 	/* Called with kvm->slots_lock held.  */
12450 	if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
12451 		return ERR_PTR_USR(-EINVAL);
12452 
12453 	slot = id_to_memslot(slots, id);
12454 	if (size) {
12455 		if (slot && slot->npages)
12456 			return ERR_PTR_USR(-EEXIST);
12457 
12458 		/*
12459 		 * MAP_SHARED to prevent internal slot pages from being moved
12460 		 * by fork()/COW.
12461 		 */
12462 		hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
12463 			      MAP_SHARED | MAP_ANONYMOUS, 0);
12464 		if (IS_ERR_VALUE(hva))
12465 			return (void __user *)hva;
12466 	} else {
12467 		if (!slot || !slot->npages)
12468 			return NULL;
12469 
12470 		old_npages = slot->npages;
12471 		hva = slot->userspace_addr;
12472 	}
12473 
12474 	for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
12475 		struct kvm_userspace_memory_region m;
12476 
12477 		m.slot = id | (i << 16);
12478 		m.flags = 0;
12479 		m.guest_phys_addr = gpa;
12480 		m.userspace_addr = hva;
12481 		m.memory_size = size;
12482 		r = __kvm_set_memory_region(kvm, &m);
12483 		if (r < 0)
12484 			return ERR_PTR_USR(r);
12485 	}
12486 
12487 	if (!size)
12488 		vm_munmap(hva, old_npages * PAGE_SIZE);
12489 
12490 	return (void __user *)hva;
12491 }
12492 EXPORT_SYMBOL_GPL(__x86_set_memory_region);
12493 
kvm_arch_pre_destroy_vm(struct kvm * kvm)12494 void kvm_arch_pre_destroy_vm(struct kvm *kvm)
12495 {
12496 	kvm_mmu_pre_destroy_vm(kvm);
12497 }
12498 
kvm_arch_destroy_vm(struct kvm * kvm)12499 void kvm_arch_destroy_vm(struct kvm *kvm)
12500 {
12501 	if (current->mm == kvm->mm) {
12502 		/*
12503 		 * Free memory regions allocated on behalf of userspace,
12504 		 * unless the memory map has changed due to process exit
12505 		 * or fd copying.
12506 		 */
12507 		mutex_lock(&kvm->slots_lock);
12508 		__x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
12509 					0, 0);
12510 		__x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
12511 					0, 0);
12512 		__x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
12513 		mutex_unlock(&kvm->slots_lock);
12514 	}
12515 	kvm_unload_vcpu_mmus(kvm);
12516 	static_call_cond(kvm_x86_vm_destroy)(kvm);
12517 	kvm_free_msr_filter(srcu_dereference_check(kvm->arch.msr_filter, &kvm->srcu, 1));
12518 	kvm_pic_destroy(kvm);
12519 	kvm_ioapic_destroy(kvm);
12520 	kvm_destroy_vcpus(kvm);
12521 	kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
12522 	kfree(srcu_dereference_check(kvm->arch.pmu_event_filter, &kvm->srcu, 1));
12523 	kvm_mmu_uninit_vm(kvm);
12524 	kvm_page_track_cleanup(kvm);
12525 	kvm_xen_destroy_vm(kvm);
12526 	kvm_hv_destroy_vm(kvm);
12527 }
12528 
memslot_rmap_free(struct kvm_memory_slot * slot)12529 static void memslot_rmap_free(struct kvm_memory_slot *slot)
12530 {
12531 	int i;
12532 
12533 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12534 		kvfree(slot->arch.rmap[i]);
12535 		slot->arch.rmap[i] = NULL;
12536 	}
12537 }
12538 
kvm_arch_free_memslot(struct kvm * kvm,struct kvm_memory_slot * slot)12539 void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *slot)
12540 {
12541 	int i;
12542 
12543 	memslot_rmap_free(slot);
12544 
12545 	for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12546 		kvfree(slot->arch.lpage_info[i - 1]);
12547 		slot->arch.lpage_info[i - 1] = NULL;
12548 	}
12549 
12550 	kvm_page_track_free_memslot(slot);
12551 }
12552 
memslot_rmap_alloc(struct kvm_memory_slot * slot,unsigned long npages)12553 int memslot_rmap_alloc(struct kvm_memory_slot *slot, unsigned long npages)
12554 {
12555 	const int sz = sizeof(*slot->arch.rmap[0]);
12556 	int i;
12557 
12558 	for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
12559 		int level = i + 1;
12560 		int lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12561 
12562 		if (slot->arch.rmap[i])
12563 			continue;
12564 
12565 		slot->arch.rmap[i] = __vcalloc(lpages, sz, GFP_KERNEL_ACCOUNT);
12566 		if (!slot->arch.rmap[i]) {
12567 			memslot_rmap_free(slot);
12568 			return -ENOMEM;
12569 		}
12570 	}
12571 
12572 	return 0;
12573 }
12574 
kvm_alloc_memslot_metadata(struct kvm * kvm,struct kvm_memory_slot * slot)12575 static int kvm_alloc_memslot_metadata(struct kvm *kvm,
12576 				      struct kvm_memory_slot *slot)
12577 {
12578 	unsigned long npages = slot->npages;
12579 	int i, r;
12580 
12581 	/*
12582 	 * Clear out the previous array pointers for the KVM_MR_MOVE case.  The
12583 	 * old arrays will be freed by __kvm_set_memory_region() if installing
12584 	 * the new memslot is successful.
12585 	 */
12586 	memset(&slot->arch, 0, sizeof(slot->arch));
12587 
12588 	if (kvm_memslots_have_rmaps(kvm)) {
12589 		r = memslot_rmap_alloc(slot, npages);
12590 		if (r)
12591 			return r;
12592 	}
12593 
12594 	for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12595 		struct kvm_lpage_info *linfo;
12596 		unsigned long ugfn;
12597 		int lpages;
12598 		int level = i + 1;
12599 
12600 		lpages = __kvm_mmu_slot_lpages(slot, npages, level);
12601 
12602 		linfo = __vcalloc(lpages, sizeof(*linfo), GFP_KERNEL_ACCOUNT);
12603 		if (!linfo)
12604 			goto out_free;
12605 
12606 		slot->arch.lpage_info[i - 1] = linfo;
12607 
12608 		if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
12609 			linfo[0].disallow_lpage = 1;
12610 		if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
12611 			linfo[lpages - 1].disallow_lpage = 1;
12612 		ugfn = slot->userspace_addr >> PAGE_SHIFT;
12613 		/*
12614 		 * If the gfn and userspace address are not aligned wrt each
12615 		 * other, disable large page support for this slot.
12616 		 */
12617 		if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1)) {
12618 			unsigned long j;
12619 
12620 			for (j = 0; j < lpages; ++j)
12621 				linfo[j].disallow_lpage = 1;
12622 		}
12623 	}
12624 
12625 	if (kvm_page_track_create_memslot(kvm, slot, npages))
12626 		goto out_free;
12627 
12628 	return 0;
12629 
12630 out_free:
12631 	memslot_rmap_free(slot);
12632 
12633 	for (i = 1; i < KVM_NR_PAGE_SIZES; ++i) {
12634 		kvfree(slot->arch.lpage_info[i - 1]);
12635 		slot->arch.lpage_info[i - 1] = NULL;
12636 	}
12637 	return -ENOMEM;
12638 }
12639 
kvm_arch_memslots_updated(struct kvm * kvm,u64 gen)12640 void kvm_arch_memslots_updated(struct kvm *kvm, u64 gen)
12641 {
12642 	struct kvm_vcpu *vcpu;
12643 	unsigned long i;
12644 
12645 	/*
12646 	 * memslots->generation has been incremented.
12647 	 * mmio generation may have reached its maximum value.
12648 	 */
12649 	kvm_mmu_invalidate_mmio_sptes(kvm, gen);
12650 
12651 	/* Force re-initialization of steal_time cache */
12652 	kvm_for_each_vcpu(i, vcpu, kvm)
12653 		kvm_vcpu_kick(vcpu);
12654 }
12655 
kvm_arch_prepare_memory_region(struct kvm * kvm,const struct kvm_memory_slot * old,struct kvm_memory_slot * new,enum kvm_mr_change change)12656 int kvm_arch_prepare_memory_region(struct kvm *kvm,
12657 				   const struct kvm_memory_slot *old,
12658 				   struct kvm_memory_slot *new,
12659 				   enum kvm_mr_change change)
12660 {
12661 	/*
12662 	 * KVM doesn't support moving memslots when there are external page
12663 	 * trackers attached to the VM, i.e. if KVMGT is in use.
12664 	 */
12665 	if (change == KVM_MR_MOVE && kvm_page_track_has_external_user(kvm))
12666 		return -EINVAL;
12667 
12668 	if (change == KVM_MR_CREATE || change == KVM_MR_MOVE) {
12669 		if ((new->base_gfn + new->npages - 1) > kvm_mmu_max_gfn())
12670 			return -EINVAL;
12671 
12672 		return kvm_alloc_memslot_metadata(kvm, new);
12673 	}
12674 
12675 	if (change == KVM_MR_FLAGS_ONLY)
12676 		memcpy(&new->arch, &old->arch, sizeof(old->arch));
12677 	else if (WARN_ON_ONCE(change != KVM_MR_DELETE))
12678 		return -EIO;
12679 
12680 	return 0;
12681 }
12682 
12683 
kvm_mmu_update_cpu_dirty_logging(struct kvm * kvm,bool enable)12684 static void kvm_mmu_update_cpu_dirty_logging(struct kvm *kvm, bool enable)
12685 {
12686 	int nr_slots;
12687 
12688 	if (!kvm_x86_ops.cpu_dirty_log_size)
12689 		return;
12690 
12691 	nr_slots = atomic_read(&kvm->nr_memslots_dirty_logging);
12692 	if ((enable && nr_slots == 1) || !nr_slots)
12693 		kvm_make_all_cpus_request(kvm, KVM_REQ_UPDATE_CPU_DIRTY_LOGGING);
12694 }
12695 
kvm_mmu_slot_apply_flags(struct kvm * kvm,struct kvm_memory_slot * old,const struct kvm_memory_slot * new,enum kvm_mr_change change)12696 static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
12697 				     struct kvm_memory_slot *old,
12698 				     const struct kvm_memory_slot *new,
12699 				     enum kvm_mr_change change)
12700 {
12701 	u32 old_flags = old ? old->flags : 0;
12702 	u32 new_flags = new ? new->flags : 0;
12703 	bool log_dirty_pages = new_flags & KVM_MEM_LOG_DIRTY_PAGES;
12704 
12705 	/*
12706 	 * Update CPU dirty logging if dirty logging is being toggled.  This
12707 	 * applies to all operations.
12708 	 */
12709 	if ((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)
12710 		kvm_mmu_update_cpu_dirty_logging(kvm, log_dirty_pages);
12711 
12712 	/*
12713 	 * Nothing more to do for RO slots (which can't be dirtied and can't be
12714 	 * made writable) or CREATE/MOVE/DELETE of a slot.
12715 	 *
12716 	 * For a memslot with dirty logging disabled:
12717 	 * CREATE:      No dirty mappings will already exist.
12718 	 * MOVE/DELETE: The old mappings will already have been cleaned up by
12719 	 *		kvm_arch_flush_shadow_memslot()
12720 	 *
12721 	 * For a memslot with dirty logging enabled:
12722 	 * CREATE:      No shadow pages exist, thus nothing to write-protect
12723 	 *		and no dirty bits to clear.
12724 	 * MOVE/DELETE: The old mappings will already have been cleaned up by
12725 	 *		kvm_arch_flush_shadow_memslot().
12726 	 */
12727 	if ((change != KVM_MR_FLAGS_ONLY) || (new_flags & KVM_MEM_READONLY))
12728 		return;
12729 
12730 	/*
12731 	 * READONLY and non-flags changes were filtered out above, and the only
12732 	 * other flag is LOG_DIRTY_PAGES, i.e. something is wrong if dirty
12733 	 * logging isn't being toggled on or off.
12734 	 */
12735 	if (WARN_ON_ONCE(!((old_flags ^ new_flags) & KVM_MEM_LOG_DIRTY_PAGES)))
12736 		return;
12737 
12738 	if (!log_dirty_pages) {
12739 		/*
12740 		 * Dirty logging tracks sptes in 4k granularity, meaning that
12741 		 * large sptes have to be split.  If live migration succeeds,
12742 		 * the guest in the source machine will be destroyed and large
12743 		 * sptes will be created in the destination.  However, if the
12744 		 * guest continues to run in the source machine (for example if
12745 		 * live migration fails), small sptes will remain around and
12746 		 * cause bad performance.
12747 		 *
12748 		 * Scan sptes if dirty logging has been stopped, dropping those
12749 		 * which can be collapsed into a single large-page spte.  Later
12750 		 * page faults will create the large-page sptes.
12751 		 */
12752 		kvm_mmu_zap_collapsible_sptes(kvm, new);
12753 	} else {
12754 		/*
12755 		 * Initially-all-set does not require write protecting any page,
12756 		 * because they're all assumed to be dirty.
12757 		 */
12758 		if (kvm_dirty_log_manual_protect_and_init_set(kvm))
12759 			return;
12760 
12761 		if (READ_ONCE(eager_page_split))
12762 			kvm_mmu_slot_try_split_huge_pages(kvm, new, PG_LEVEL_4K);
12763 
12764 		if (kvm_x86_ops.cpu_dirty_log_size) {
12765 			kvm_mmu_slot_leaf_clear_dirty(kvm, new);
12766 			kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_2M);
12767 		} else {
12768 			kvm_mmu_slot_remove_write_access(kvm, new, PG_LEVEL_4K);
12769 		}
12770 
12771 		/*
12772 		 * Unconditionally flush the TLBs after enabling dirty logging.
12773 		 * A flush is almost always going to be necessary (see below),
12774 		 * and unconditionally flushing allows the helpers to omit
12775 		 * the subtly complex checks when removing write access.
12776 		 *
12777 		 * Do the flush outside of mmu_lock to reduce the amount of
12778 		 * time mmu_lock is held.  Flushing after dropping mmu_lock is
12779 		 * safe as KVM only needs to guarantee the slot is fully
12780 		 * write-protected before returning to userspace, i.e. before
12781 		 * userspace can consume the dirty status.
12782 		 *
12783 		 * Flushing outside of mmu_lock requires KVM to be careful when
12784 		 * making decisions based on writable status of an SPTE, e.g. a
12785 		 * !writable SPTE doesn't guarantee a CPU can't perform writes.
12786 		 *
12787 		 * Specifically, KVM also write-protects guest page tables to
12788 		 * monitor changes when using shadow paging, and must guarantee
12789 		 * no CPUs can write to those page before mmu_lock is dropped.
12790 		 * Because CPUs may have stale TLB entries at this point, a
12791 		 * !writable SPTE doesn't guarantee CPUs can't perform writes.
12792 		 *
12793 		 * KVM also allows making SPTES writable outside of mmu_lock,
12794 		 * e.g. to allow dirty logging without taking mmu_lock.
12795 		 *
12796 		 * To handle these scenarios, KVM uses a separate software-only
12797 		 * bit (MMU-writable) to track if a SPTE is !writable due to
12798 		 * a guest page table being write-protected (KVM clears the
12799 		 * MMU-writable flag when write-protecting for shadow paging).
12800 		 *
12801 		 * The use of MMU-writable is also the primary motivation for
12802 		 * the unconditional flush.  Because KVM must guarantee that a
12803 		 * CPU doesn't contain stale, writable TLB entries for a
12804 		 * !MMU-writable SPTE, KVM must flush if it encounters any
12805 		 * MMU-writable SPTE regardless of whether the actual hardware
12806 		 * writable bit was set.  I.e. KVM is almost guaranteed to need
12807 		 * to flush, while unconditionally flushing allows the "remove
12808 		 * write access" helpers to ignore MMU-writable entirely.
12809 		 *
12810 		 * See is_writable_pte() for more details (the case involving
12811 		 * access-tracked SPTEs is particularly relevant).
12812 		 */
12813 		kvm_flush_remote_tlbs_memslot(kvm, new);
12814 	}
12815 }
12816 
kvm_arch_commit_memory_region(struct kvm * kvm,struct kvm_memory_slot * old,const struct kvm_memory_slot * new,enum kvm_mr_change change)12817 void kvm_arch_commit_memory_region(struct kvm *kvm,
12818 				struct kvm_memory_slot *old,
12819 				const struct kvm_memory_slot *new,
12820 				enum kvm_mr_change change)
12821 {
12822 	if (change == KVM_MR_DELETE)
12823 		kvm_page_track_delete_slot(kvm, old);
12824 
12825 	if (!kvm->arch.n_requested_mmu_pages &&
12826 	    (change == KVM_MR_CREATE || change == KVM_MR_DELETE)) {
12827 		unsigned long nr_mmu_pages;
12828 
12829 		nr_mmu_pages = kvm->nr_memslot_pages / KVM_MEMSLOT_PAGES_TO_MMU_PAGES_RATIO;
12830 		nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
12831 		kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
12832 	}
12833 
12834 	kvm_mmu_slot_apply_flags(kvm, old, new, change);
12835 
12836 	/* Free the arrays associated with the old memslot. */
12837 	if (change == KVM_MR_MOVE)
12838 		kvm_arch_free_memslot(kvm, old);
12839 }
12840 
kvm_guest_apic_has_interrupt(struct kvm_vcpu * vcpu)12841 static inline bool kvm_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
12842 {
12843 	return (is_guest_mode(vcpu) &&
12844 		static_call(kvm_x86_guest_apic_has_interrupt)(vcpu));
12845 }
12846 
kvm_vcpu_has_events(struct kvm_vcpu * vcpu)12847 static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
12848 {
12849 	if (!list_empty_careful(&vcpu->async_pf.done))
12850 		return true;
12851 
12852 	if (kvm_apic_has_pending_init_or_sipi(vcpu) &&
12853 	    kvm_apic_init_sipi_allowed(vcpu))
12854 		return true;
12855 
12856 	if (vcpu->arch.pv.pv_unhalted)
12857 		return true;
12858 
12859 	if (kvm_is_exception_pending(vcpu))
12860 		return true;
12861 
12862 	if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12863 	    (vcpu->arch.nmi_pending &&
12864 	     static_call(kvm_x86_nmi_allowed)(vcpu, false)))
12865 		return true;
12866 
12867 #ifdef CONFIG_KVM_SMM
12868 	if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
12869 	    (vcpu->arch.smi_pending &&
12870 	     static_call(kvm_x86_smi_allowed)(vcpu, false)))
12871 		return true;
12872 #endif
12873 
12874 	if (kvm_test_request(KVM_REQ_PMI, vcpu))
12875 		return true;
12876 
12877 	if (kvm_arch_interrupt_allowed(vcpu) &&
12878 	    (kvm_cpu_has_interrupt(vcpu) ||
12879 	    kvm_guest_apic_has_interrupt(vcpu)))
12880 		return true;
12881 
12882 	if (kvm_hv_has_stimer_pending(vcpu))
12883 		return true;
12884 
12885 	if (is_guest_mode(vcpu) &&
12886 	    kvm_x86_ops.nested_ops->has_events &&
12887 	    kvm_x86_ops.nested_ops->has_events(vcpu, false))
12888 		return true;
12889 
12890 	if (kvm_xen_has_pending_events(vcpu))
12891 		return true;
12892 
12893 	return false;
12894 }
12895 
kvm_arch_vcpu_runnable(struct kvm_vcpu * vcpu)12896 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
12897 {
12898 	return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
12899 }
12900 
kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu * vcpu)12901 bool kvm_arch_dy_has_pending_interrupt(struct kvm_vcpu *vcpu)
12902 {
12903 	if (kvm_vcpu_apicv_active(vcpu) &&
12904 	    static_call(kvm_x86_dy_apicv_has_pending_interrupt)(vcpu))
12905 		return true;
12906 
12907 	return false;
12908 }
12909 
kvm_arch_dy_runnable(struct kvm_vcpu * vcpu)12910 bool kvm_arch_dy_runnable(struct kvm_vcpu *vcpu)
12911 {
12912 	if (READ_ONCE(vcpu->arch.pv.pv_unhalted))
12913 		return true;
12914 
12915 	if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
12916 #ifdef CONFIG_KVM_SMM
12917 		kvm_test_request(KVM_REQ_SMI, vcpu) ||
12918 #endif
12919 		 kvm_test_request(KVM_REQ_EVENT, vcpu))
12920 		return true;
12921 
12922 	return kvm_arch_dy_has_pending_interrupt(vcpu);
12923 }
12924 
kvm_arch_vcpu_in_kernel(struct kvm_vcpu * vcpu)12925 bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
12926 {
12927 	if (vcpu->arch.guest_state_protected)
12928 		return true;
12929 
12930 	return vcpu->arch.preempted_in_kernel;
12931 }
12932 
kvm_arch_vcpu_get_ip(struct kvm_vcpu * vcpu)12933 unsigned long kvm_arch_vcpu_get_ip(struct kvm_vcpu *vcpu)
12934 {
12935 	return kvm_rip_read(vcpu);
12936 }
12937 
kvm_arch_vcpu_should_kick(struct kvm_vcpu * vcpu)12938 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
12939 {
12940 	return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
12941 }
12942 
kvm_arch_interrupt_allowed(struct kvm_vcpu * vcpu)12943 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
12944 {
12945 	return static_call(kvm_x86_interrupt_allowed)(vcpu, false);
12946 }
12947 
kvm_get_linear_rip(struct kvm_vcpu * vcpu)12948 unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
12949 {
12950 	/* Can't read the RIP when guest state is protected, just return 0 */
12951 	if (vcpu->arch.guest_state_protected)
12952 		return 0;
12953 
12954 	if (is_64_bit_mode(vcpu))
12955 		return kvm_rip_read(vcpu);
12956 	return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
12957 		     kvm_rip_read(vcpu));
12958 }
12959 EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
12960 
kvm_is_linear_rip(struct kvm_vcpu * vcpu,unsigned long linear_rip)12961 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
12962 {
12963 	return kvm_get_linear_rip(vcpu) == linear_rip;
12964 }
12965 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
12966 
kvm_get_rflags(struct kvm_vcpu * vcpu)12967 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
12968 {
12969 	unsigned long rflags;
12970 
12971 	rflags = static_call(kvm_x86_get_rflags)(vcpu);
12972 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
12973 		rflags &= ~X86_EFLAGS_TF;
12974 	return rflags;
12975 }
12976 EXPORT_SYMBOL_GPL(kvm_get_rflags);
12977 
__kvm_set_rflags(struct kvm_vcpu * vcpu,unsigned long rflags)12978 static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12979 {
12980 	if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
12981 	    kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
12982 		rflags |= X86_EFLAGS_TF;
12983 	static_call(kvm_x86_set_rflags)(vcpu, rflags);
12984 }
12985 
kvm_set_rflags(struct kvm_vcpu * vcpu,unsigned long rflags)12986 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
12987 {
12988 	__kvm_set_rflags(vcpu, rflags);
12989 	kvm_make_request(KVM_REQ_EVENT, vcpu);
12990 }
12991 EXPORT_SYMBOL_GPL(kvm_set_rflags);
12992 
kvm_async_pf_hash_fn(gfn_t gfn)12993 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
12994 {
12995 	BUILD_BUG_ON(!is_power_of_2(ASYNC_PF_PER_VCPU));
12996 
12997 	return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
12998 }
12999 
kvm_async_pf_next_probe(u32 key)13000 static inline u32 kvm_async_pf_next_probe(u32 key)
13001 {
13002 	return (key + 1) & (ASYNC_PF_PER_VCPU - 1);
13003 }
13004 
kvm_add_async_pf_gfn(struct kvm_vcpu * vcpu,gfn_t gfn)13005 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13006 {
13007 	u32 key = kvm_async_pf_hash_fn(gfn);
13008 
13009 	while (vcpu->arch.apf.gfns[key] != ~0)
13010 		key = kvm_async_pf_next_probe(key);
13011 
13012 	vcpu->arch.apf.gfns[key] = gfn;
13013 }
13014 
kvm_async_pf_gfn_slot(struct kvm_vcpu * vcpu,gfn_t gfn)13015 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
13016 {
13017 	int i;
13018 	u32 key = kvm_async_pf_hash_fn(gfn);
13019 
13020 	for (i = 0; i < ASYNC_PF_PER_VCPU &&
13021 		     (vcpu->arch.apf.gfns[key] != gfn &&
13022 		      vcpu->arch.apf.gfns[key] != ~0); i++)
13023 		key = kvm_async_pf_next_probe(key);
13024 
13025 	return key;
13026 }
13027 
kvm_find_async_pf_gfn(struct kvm_vcpu * vcpu,gfn_t gfn)13028 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13029 {
13030 	return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
13031 }
13032 
kvm_del_async_pf_gfn(struct kvm_vcpu * vcpu,gfn_t gfn)13033 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
13034 {
13035 	u32 i, j, k;
13036 
13037 	i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
13038 
13039 	if (WARN_ON_ONCE(vcpu->arch.apf.gfns[i] != gfn))
13040 		return;
13041 
13042 	while (true) {
13043 		vcpu->arch.apf.gfns[i] = ~0;
13044 		do {
13045 			j = kvm_async_pf_next_probe(j);
13046 			if (vcpu->arch.apf.gfns[j] == ~0)
13047 				return;
13048 			k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
13049 			/*
13050 			 * k lies cyclically in ]i,j]
13051 			 * |    i.k.j |
13052 			 * |....j i.k.| or  |.k..j i...|
13053 			 */
13054 		} while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
13055 		vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
13056 		i = j;
13057 	}
13058 }
13059 
apf_put_user_notpresent(struct kvm_vcpu * vcpu)13060 static inline int apf_put_user_notpresent(struct kvm_vcpu *vcpu)
13061 {
13062 	u32 reason = KVM_PV_REASON_PAGE_NOT_PRESENT;
13063 
13064 	return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &reason,
13065 				      sizeof(reason));
13066 }
13067 
apf_put_user_ready(struct kvm_vcpu * vcpu,u32 token)13068 static inline int apf_put_user_ready(struct kvm_vcpu *vcpu, u32 token)
13069 {
13070 	unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13071 
13072 	return kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13073 					     &token, offset, sizeof(token));
13074 }
13075 
apf_pageready_slot_free(struct kvm_vcpu * vcpu)13076 static inline bool apf_pageready_slot_free(struct kvm_vcpu *vcpu)
13077 {
13078 	unsigned int offset = offsetof(struct kvm_vcpu_pv_apf_data, token);
13079 	u32 val;
13080 
13081 	if (kvm_read_guest_offset_cached(vcpu->kvm, &vcpu->arch.apf.data,
13082 					 &val, offset, sizeof(val)))
13083 		return false;
13084 
13085 	return !val;
13086 }
13087 
kvm_can_deliver_async_pf(struct kvm_vcpu * vcpu)13088 static bool kvm_can_deliver_async_pf(struct kvm_vcpu *vcpu)
13089 {
13090 
13091 	if (!kvm_pv_async_pf_enabled(vcpu))
13092 		return false;
13093 
13094 	if (vcpu->arch.apf.send_user_only &&
13095 	    static_call(kvm_x86_get_cpl)(vcpu) == 0)
13096 		return false;
13097 
13098 	if (is_guest_mode(vcpu)) {
13099 		/*
13100 		 * L1 needs to opt into the special #PF vmexits that are
13101 		 * used to deliver async page faults.
13102 		 */
13103 		return vcpu->arch.apf.delivery_as_pf_vmexit;
13104 	} else {
13105 		/*
13106 		 * Play it safe in case the guest temporarily disables paging.
13107 		 * The real mode IDT in particular is unlikely to have a #PF
13108 		 * exception setup.
13109 		 */
13110 		return is_paging(vcpu);
13111 	}
13112 }
13113 
kvm_can_do_async_pf(struct kvm_vcpu * vcpu)13114 bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu)
13115 {
13116 	if (unlikely(!lapic_in_kernel(vcpu) ||
13117 		     kvm_event_needs_reinjection(vcpu) ||
13118 		     kvm_is_exception_pending(vcpu)))
13119 		return false;
13120 
13121 	if (kvm_hlt_in_guest(vcpu->kvm) && !kvm_can_deliver_async_pf(vcpu))
13122 		return false;
13123 
13124 	/*
13125 	 * If interrupts are off we cannot even use an artificial
13126 	 * halt state.
13127 	 */
13128 	return kvm_arch_interrupt_allowed(vcpu);
13129 }
13130 
kvm_arch_async_page_not_present(struct kvm_vcpu * vcpu,struct kvm_async_pf * work)13131 bool kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
13132 				     struct kvm_async_pf *work)
13133 {
13134 	struct x86_exception fault;
13135 
13136 	trace_kvm_async_pf_not_present(work->arch.token, work->cr2_or_gpa);
13137 	kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
13138 
13139 	if (kvm_can_deliver_async_pf(vcpu) &&
13140 	    !apf_put_user_notpresent(vcpu)) {
13141 		fault.vector = PF_VECTOR;
13142 		fault.error_code_valid = true;
13143 		fault.error_code = 0;
13144 		fault.nested_page_fault = false;
13145 		fault.address = work->arch.token;
13146 		fault.async_page_fault = true;
13147 		kvm_inject_page_fault(vcpu, &fault);
13148 		return true;
13149 	} else {
13150 		/*
13151 		 * It is not possible to deliver a paravirtualized asynchronous
13152 		 * page fault, but putting the guest in an artificial halt state
13153 		 * can be beneficial nevertheless: if an interrupt arrives, we
13154 		 * can deliver it timely and perhaps the guest will schedule
13155 		 * another process.  When the instruction that triggered a page
13156 		 * fault is retried, hopefully the page will be ready in the host.
13157 		 */
13158 		kvm_make_request(KVM_REQ_APF_HALT, vcpu);
13159 		return false;
13160 	}
13161 }
13162 
kvm_arch_async_page_present(struct kvm_vcpu * vcpu,struct kvm_async_pf * work)13163 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
13164 				 struct kvm_async_pf *work)
13165 {
13166 	struct kvm_lapic_irq irq = {
13167 		.delivery_mode = APIC_DM_FIXED,
13168 		.vector = vcpu->arch.apf.vec
13169 	};
13170 
13171 	if (work->wakeup_all)
13172 		work->arch.token = ~0; /* broadcast wakeup */
13173 	else
13174 		kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
13175 	trace_kvm_async_pf_ready(work->arch.token, work->cr2_or_gpa);
13176 
13177 	if ((work->wakeup_all || work->notpresent_injected) &&
13178 	    kvm_pv_async_pf_enabled(vcpu) &&
13179 	    !apf_put_user_ready(vcpu, work->arch.token)) {
13180 		vcpu->arch.apf.pageready_pending = true;
13181 		kvm_apic_set_irq(vcpu, &irq, NULL);
13182 	}
13183 
13184 	vcpu->arch.apf.halted = false;
13185 	vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
13186 }
13187 
kvm_arch_async_page_present_queued(struct kvm_vcpu * vcpu)13188 void kvm_arch_async_page_present_queued(struct kvm_vcpu *vcpu)
13189 {
13190 	kvm_make_request(KVM_REQ_APF_READY, vcpu);
13191 	if (!vcpu->arch.apf.pageready_pending)
13192 		kvm_vcpu_kick(vcpu);
13193 }
13194 
kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu * vcpu)13195 bool kvm_arch_can_dequeue_async_page_present(struct kvm_vcpu *vcpu)
13196 {
13197 	if (!kvm_pv_async_pf_enabled(vcpu))
13198 		return true;
13199 	else
13200 		return kvm_lapic_enabled(vcpu) && apf_pageready_slot_free(vcpu);
13201 }
13202 
kvm_arch_start_assignment(struct kvm * kvm)13203 void kvm_arch_start_assignment(struct kvm *kvm)
13204 {
13205 	if (atomic_inc_return(&kvm->arch.assigned_device_count) == 1)
13206 		static_call_cond(kvm_x86_pi_start_assignment)(kvm);
13207 }
13208 EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
13209 
kvm_arch_end_assignment(struct kvm * kvm)13210 void kvm_arch_end_assignment(struct kvm *kvm)
13211 {
13212 	atomic_dec(&kvm->arch.assigned_device_count);
13213 }
13214 EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
13215 
kvm_arch_has_assigned_device(struct kvm * kvm)13216 bool noinstr kvm_arch_has_assigned_device(struct kvm *kvm)
13217 {
13218 	return raw_atomic_read(&kvm->arch.assigned_device_count);
13219 }
13220 EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
13221 
kvm_arch_register_noncoherent_dma(struct kvm * kvm)13222 void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
13223 {
13224 	atomic_inc(&kvm->arch.noncoherent_dma_count);
13225 }
13226 EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
13227 
kvm_arch_unregister_noncoherent_dma(struct kvm * kvm)13228 void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
13229 {
13230 	atomic_dec(&kvm->arch.noncoherent_dma_count);
13231 }
13232 EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
13233 
kvm_arch_has_noncoherent_dma(struct kvm * kvm)13234 bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
13235 {
13236 	return atomic_read(&kvm->arch.noncoherent_dma_count);
13237 }
13238 EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
13239 
kvm_arch_has_irq_bypass(void)13240 bool kvm_arch_has_irq_bypass(void)
13241 {
13242 	return enable_apicv && irq_remapping_cap(IRQ_POSTING_CAP);
13243 }
13244 
kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer * cons,struct irq_bypass_producer * prod)13245 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
13246 				      struct irq_bypass_producer *prod)
13247 {
13248 	struct kvm_kernel_irqfd *irqfd =
13249 		container_of(cons, struct kvm_kernel_irqfd, consumer);
13250 	int ret;
13251 
13252 	irqfd->producer = prod;
13253 	kvm_arch_start_assignment(irqfd->kvm);
13254 	ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm,
13255 					 prod->irq, irqfd->gsi, 1);
13256 
13257 	if (ret)
13258 		kvm_arch_end_assignment(irqfd->kvm);
13259 
13260 	return ret;
13261 }
13262 
kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer * cons,struct irq_bypass_producer * prod)13263 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
13264 				      struct irq_bypass_producer *prod)
13265 {
13266 	int ret;
13267 	struct kvm_kernel_irqfd *irqfd =
13268 		container_of(cons, struct kvm_kernel_irqfd, consumer);
13269 
13270 	WARN_ON(irqfd->producer != prod);
13271 	irqfd->producer = NULL;
13272 
13273 	/*
13274 	 * When producer of consumer is unregistered, we change back to
13275 	 * remapped mode, so we can re-use the current implementation
13276 	 * when the irq is masked/disabled or the consumer side (KVM
13277 	 * int this case doesn't want to receive the interrupts.
13278 	*/
13279 	ret = static_call(kvm_x86_pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0);
13280 	if (ret)
13281 		printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
13282 		       " fails: %d\n", irqfd->consumer.token, ret);
13283 
13284 	kvm_arch_end_assignment(irqfd->kvm);
13285 }
13286 
kvm_arch_update_irqfd_routing(struct kvm * kvm,unsigned int host_irq,uint32_t guest_irq,bool set)13287 int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
13288 				   uint32_t guest_irq, bool set)
13289 {
13290 	return static_call(kvm_x86_pi_update_irte)(kvm, host_irq, guest_irq, set);
13291 }
13292 
kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry * old,struct kvm_kernel_irq_routing_entry * new)13293 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old,
13294 				  struct kvm_kernel_irq_routing_entry *new)
13295 {
13296 	if (new->type != KVM_IRQ_ROUTING_MSI)
13297 		return true;
13298 
13299 	return !!memcmp(&old->msi, &new->msi, sizeof(new->msi));
13300 }
13301 
kvm_vector_hashing_enabled(void)13302 bool kvm_vector_hashing_enabled(void)
13303 {
13304 	return vector_hashing;
13305 }
13306 
kvm_arch_no_poll(struct kvm_vcpu * vcpu)13307 bool kvm_arch_no_poll(struct kvm_vcpu *vcpu)
13308 {
13309 	return (vcpu->arch.msr_kvm_poll_control & 1) == 0;
13310 }
13311 EXPORT_SYMBOL_GPL(kvm_arch_no_poll);
13312 
13313 
kvm_spec_ctrl_test_value(u64 value)13314 int kvm_spec_ctrl_test_value(u64 value)
13315 {
13316 	/*
13317 	 * test that setting IA32_SPEC_CTRL to given value
13318 	 * is allowed by the host processor
13319 	 */
13320 
13321 	u64 saved_value;
13322 	unsigned long flags;
13323 	int ret = 0;
13324 
13325 	local_irq_save(flags);
13326 
13327 	if (rdmsrl_safe(MSR_IA32_SPEC_CTRL, &saved_value))
13328 		ret = 1;
13329 	else if (wrmsrl_safe(MSR_IA32_SPEC_CTRL, value))
13330 		ret = 1;
13331 	else
13332 		wrmsrl(MSR_IA32_SPEC_CTRL, saved_value);
13333 
13334 	local_irq_restore(flags);
13335 
13336 	return ret;
13337 }
13338 EXPORT_SYMBOL_GPL(kvm_spec_ctrl_test_value);
13339 
kvm_fixup_and_inject_pf_error(struct kvm_vcpu * vcpu,gva_t gva,u16 error_code)13340 void kvm_fixup_and_inject_pf_error(struct kvm_vcpu *vcpu, gva_t gva, u16 error_code)
13341 {
13342 	struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
13343 	struct x86_exception fault;
13344 	u64 access = error_code &
13345 		(PFERR_WRITE_MASK | PFERR_FETCH_MASK | PFERR_USER_MASK);
13346 
13347 	if (!(error_code & PFERR_PRESENT_MASK) ||
13348 	    mmu->gva_to_gpa(vcpu, mmu, gva, access, &fault) != INVALID_GPA) {
13349 		/*
13350 		 * If vcpu->arch.walk_mmu->gva_to_gpa succeeded, the page
13351 		 * tables probably do not match the TLB.  Just proceed
13352 		 * with the error code that the processor gave.
13353 		 */
13354 		fault.vector = PF_VECTOR;
13355 		fault.error_code_valid = true;
13356 		fault.error_code = error_code;
13357 		fault.nested_page_fault = false;
13358 		fault.address = gva;
13359 		fault.async_page_fault = false;
13360 	}
13361 	vcpu->arch.walk_mmu->inject_page_fault(vcpu, &fault);
13362 }
13363 EXPORT_SYMBOL_GPL(kvm_fixup_and_inject_pf_error);
13364 
13365 /*
13366  * Handles kvm_read/write_guest_virt*() result and either injects #PF or returns
13367  * KVM_EXIT_INTERNAL_ERROR for cases not currently handled by KVM. Return value
13368  * indicates whether exit to userspace is needed.
13369  */
kvm_handle_memory_failure(struct kvm_vcpu * vcpu,int r,struct x86_exception * e)13370 int kvm_handle_memory_failure(struct kvm_vcpu *vcpu, int r,
13371 			      struct x86_exception *e)
13372 {
13373 	if (r == X86EMUL_PROPAGATE_FAULT) {
13374 		if (KVM_BUG_ON(!e, vcpu->kvm))
13375 			return -EIO;
13376 
13377 		kvm_inject_emulated_page_fault(vcpu, e);
13378 		return 1;
13379 	}
13380 
13381 	/*
13382 	 * In case kvm_read/write_guest_virt*() failed with X86EMUL_IO_NEEDED
13383 	 * while handling a VMX instruction KVM could've handled the request
13384 	 * correctly by exiting to userspace and performing I/O but there
13385 	 * doesn't seem to be a real use-case behind such requests, just return
13386 	 * KVM_EXIT_INTERNAL_ERROR for now.
13387 	 */
13388 	kvm_prepare_emulation_failure_exit(vcpu);
13389 
13390 	return 0;
13391 }
13392 EXPORT_SYMBOL_GPL(kvm_handle_memory_failure);
13393 
kvm_handle_invpcid(struct kvm_vcpu * vcpu,unsigned long type,gva_t gva)13394 int kvm_handle_invpcid(struct kvm_vcpu *vcpu, unsigned long type, gva_t gva)
13395 {
13396 	bool pcid_enabled;
13397 	struct x86_exception e;
13398 	struct {
13399 		u64 pcid;
13400 		u64 gla;
13401 	} operand;
13402 	int r;
13403 
13404 	r = kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e);
13405 	if (r != X86EMUL_CONTINUE)
13406 		return kvm_handle_memory_failure(vcpu, r, &e);
13407 
13408 	if (operand.pcid >> 12 != 0) {
13409 		kvm_inject_gp(vcpu, 0);
13410 		return 1;
13411 	}
13412 
13413 	pcid_enabled = kvm_is_cr4_bit_set(vcpu, X86_CR4_PCIDE);
13414 
13415 	switch (type) {
13416 	case INVPCID_TYPE_INDIV_ADDR:
13417 		if ((!pcid_enabled && (operand.pcid != 0)) ||
13418 		    is_noncanonical_address(operand.gla, vcpu)) {
13419 			kvm_inject_gp(vcpu, 0);
13420 			return 1;
13421 		}
13422 		kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
13423 		return kvm_skip_emulated_instruction(vcpu);
13424 
13425 	case INVPCID_TYPE_SINGLE_CTXT:
13426 		if (!pcid_enabled && (operand.pcid != 0)) {
13427 			kvm_inject_gp(vcpu, 0);
13428 			return 1;
13429 		}
13430 
13431 		kvm_invalidate_pcid(vcpu, operand.pcid);
13432 		return kvm_skip_emulated_instruction(vcpu);
13433 
13434 	case INVPCID_TYPE_ALL_NON_GLOBAL:
13435 		/*
13436 		 * Currently, KVM doesn't mark global entries in the shadow
13437 		 * page tables, so a non-global flush just degenerates to a
13438 		 * global flush. If needed, we could optimize this later by
13439 		 * keeping track of global entries in shadow page tables.
13440 		 */
13441 
13442 		fallthrough;
13443 	case INVPCID_TYPE_ALL_INCL_GLOBAL:
13444 		kvm_make_request(KVM_REQ_TLB_FLUSH_GUEST, vcpu);
13445 		return kvm_skip_emulated_instruction(vcpu);
13446 
13447 	default:
13448 		kvm_inject_gp(vcpu, 0);
13449 		return 1;
13450 	}
13451 }
13452 EXPORT_SYMBOL_GPL(kvm_handle_invpcid);
13453 
complete_sev_es_emulated_mmio(struct kvm_vcpu * vcpu)13454 static int complete_sev_es_emulated_mmio(struct kvm_vcpu *vcpu)
13455 {
13456 	struct kvm_run *run = vcpu->run;
13457 	struct kvm_mmio_fragment *frag;
13458 	unsigned int len;
13459 
13460 	BUG_ON(!vcpu->mmio_needed);
13461 
13462 	/* Complete previous fragment */
13463 	frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
13464 	len = min(8u, frag->len);
13465 	if (!vcpu->mmio_is_write)
13466 		memcpy(frag->data, run->mmio.data, len);
13467 
13468 	if (frag->len <= 8) {
13469 		/* Switch to the next fragment. */
13470 		frag++;
13471 		vcpu->mmio_cur_fragment++;
13472 	} else {
13473 		/* Go forward to the next mmio piece. */
13474 		frag->data += len;
13475 		frag->gpa += len;
13476 		frag->len -= len;
13477 	}
13478 
13479 	if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
13480 		vcpu->mmio_needed = 0;
13481 
13482 		// VMG change, at this point, we're always done
13483 		// RIP has already been advanced
13484 		return 1;
13485 	}
13486 
13487 	// More MMIO is needed
13488 	run->mmio.phys_addr = frag->gpa;
13489 	run->mmio.len = min(8u, frag->len);
13490 	run->mmio.is_write = vcpu->mmio_is_write;
13491 	if (run->mmio.is_write)
13492 		memcpy(run->mmio.data, frag->data, min(8u, frag->len));
13493 	run->exit_reason = KVM_EXIT_MMIO;
13494 
13495 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13496 
13497 	return 0;
13498 }
13499 
kvm_sev_es_mmio_write(struct kvm_vcpu * vcpu,gpa_t gpa,unsigned int bytes,void * data)13500 int kvm_sev_es_mmio_write(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13501 			  void *data)
13502 {
13503 	int handled;
13504 	struct kvm_mmio_fragment *frag;
13505 
13506 	if (!data)
13507 		return -EINVAL;
13508 
13509 	handled = write_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13510 	if (handled == bytes)
13511 		return 1;
13512 
13513 	bytes -= handled;
13514 	gpa += handled;
13515 	data += handled;
13516 
13517 	/*TODO: Check if need to increment number of frags */
13518 	frag = vcpu->mmio_fragments;
13519 	vcpu->mmio_nr_fragments = 1;
13520 	frag->len = bytes;
13521 	frag->gpa = gpa;
13522 	frag->data = data;
13523 
13524 	vcpu->mmio_needed = 1;
13525 	vcpu->mmio_cur_fragment = 0;
13526 
13527 	vcpu->run->mmio.phys_addr = gpa;
13528 	vcpu->run->mmio.len = min(8u, frag->len);
13529 	vcpu->run->mmio.is_write = 1;
13530 	memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
13531 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
13532 
13533 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13534 
13535 	return 0;
13536 }
13537 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_write);
13538 
kvm_sev_es_mmio_read(struct kvm_vcpu * vcpu,gpa_t gpa,unsigned int bytes,void * data)13539 int kvm_sev_es_mmio_read(struct kvm_vcpu *vcpu, gpa_t gpa, unsigned int bytes,
13540 			 void *data)
13541 {
13542 	int handled;
13543 	struct kvm_mmio_fragment *frag;
13544 
13545 	if (!data)
13546 		return -EINVAL;
13547 
13548 	handled = read_emultor.read_write_mmio(vcpu, gpa, bytes, data);
13549 	if (handled == bytes)
13550 		return 1;
13551 
13552 	bytes -= handled;
13553 	gpa += handled;
13554 	data += handled;
13555 
13556 	/*TODO: Check if need to increment number of frags */
13557 	frag = vcpu->mmio_fragments;
13558 	vcpu->mmio_nr_fragments = 1;
13559 	frag->len = bytes;
13560 	frag->gpa = gpa;
13561 	frag->data = data;
13562 
13563 	vcpu->mmio_needed = 1;
13564 	vcpu->mmio_cur_fragment = 0;
13565 
13566 	vcpu->run->mmio.phys_addr = gpa;
13567 	vcpu->run->mmio.len = min(8u, frag->len);
13568 	vcpu->run->mmio.is_write = 0;
13569 	vcpu->run->exit_reason = KVM_EXIT_MMIO;
13570 
13571 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_mmio;
13572 
13573 	return 0;
13574 }
13575 EXPORT_SYMBOL_GPL(kvm_sev_es_mmio_read);
13576 
advance_sev_es_emulated_pio(struct kvm_vcpu * vcpu,unsigned count,int size)13577 static void advance_sev_es_emulated_pio(struct kvm_vcpu *vcpu, unsigned count, int size)
13578 {
13579 	vcpu->arch.sev_pio_count -= count;
13580 	vcpu->arch.sev_pio_data += count * size;
13581 }
13582 
13583 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13584 			   unsigned int port);
13585 
complete_sev_es_emulated_outs(struct kvm_vcpu * vcpu)13586 static int complete_sev_es_emulated_outs(struct kvm_vcpu *vcpu)
13587 {
13588 	int size = vcpu->arch.pio.size;
13589 	int port = vcpu->arch.pio.port;
13590 
13591 	vcpu->arch.pio.count = 0;
13592 	if (vcpu->arch.sev_pio_count)
13593 		return kvm_sev_es_outs(vcpu, size, port);
13594 	return 1;
13595 }
13596 
kvm_sev_es_outs(struct kvm_vcpu * vcpu,unsigned int size,unsigned int port)13597 static int kvm_sev_es_outs(struct kvm_vcpu *vcpu, unsigned int size,
13598 			   unsigned int port)
13599 {
13600 	for (;;) {
13601 		unsigned int count =
13602 			min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13603 		int ret = emulator_pio_out(vcpu, size, port, vcpu->arch.sev_pio_data, count);
13604 
13605 		/* memcpy done already by emulator_pio_out.  */
13606 		advance_sev_es_emulated_pio(vcpu, count, size);
13607 		if (!ret)
13608 			break;
13609 
13610 		/* Emulation done by the kernel.  */
13611 		if (!vcpu->arch.sev_pio_count)
13612 			return 1;
13613 	}
13614 
13615 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_outs;
13616 	return 0;
13617 }
13618 
13619 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13620 			  unsigned int port);
13621 
complete_sev_es_emulated_ins(struct kvm_vcpu * vcpu)13622 static int complete_sev_es_emulated_ins(struct kvm_vcpu *vcpu)
13623 {
13624 	unsigned count = vcpu->arch.pio.count;
13625 	int size = vcpu->arch.pio.size;
13626 	int port = vcpu->arch.pio.port;
13627 
13628 	complete_emulator_pio_in(vcpu, vcpu->arch.sev_pio_data);
13629 	advance_sev_es_emulated_pio(vcpu, count, size);
13630 	if (vcpu->arch.sev_pio_count)
13631 		return kvm_sev_es_ins(vcpu, size, port);
13632 	return 1;
13633 }
13634 
kvm_sev_es_ins(struct kvm_vcpu * vcpu,unsigned int size,unsigned int port)13635 static int kvm_sev_es_ins(struct kvm_vcpu *vcpu, unsigned int size,
13636 			  unsigned int port)
13637 {
13638 	for (;;) {
13639 		unsigned int count =
13640 			min_t(unsigned int, PAGE_SIZE / size, vcpu->arch.sev_pio_count);
13641 		if (!emulator_pio_in(vcpu, size, port, vcpu->arch.sev_pio_data, count))
13642 			break;
13643 
13644 		/* Emulation done by the kernel.  */
13645 		advance_sev_es_emulated_pio(vcpu, count, size);
13646 		if (!vcpu->arch.sev_pio_count)
13647 			return 1;
13648 	}
13649 
13650 	vcpu->arch.complete_userspace_io = complete_sev_es_emulated_ins;
13651 	return 0;
13652 }
13653 
kvm_sev_es_string_io(struct kvm_vcpu * vcpu,unsigned int size,unsigned int port,void * data,unsigned int count,int in)13654 int kvm_sev_es_string_io(struct kvm_vcpu *vcpu, unsigned int size,
13655 			 unsigned int port, void *data,  unsigned int count,
13656 			 int in)
13657 {
13658 	vcpu->arch.sev_pio_data = data;
13659 	vcpu->arch.sev_pio_count = count;
13660 	return in ? kvm_sev_es_ins(vcpu, size, port)
13661 		  : kvm_sev_es_outs(vcpu, size, port);
13662 }
13663 EXPORT_SYMBOL_GPL(kvm_sev_es_string_io);
13664 
13665 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_entry);
13666 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
13667 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
13668 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
13669 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
13670 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
13671 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
13672 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter);
13673 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
13674 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
13675 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
13676 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmenter_failed);
13677 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
13678 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
13679 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
13680 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
13681 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update);
13682 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
13683 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
13684 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
13685 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);
13686 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_ga_log);
13687 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_kick_vcpu_slowpath);
13688 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_doorbell);
13689 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_apicv_accept_irq);
13690 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_enter);
13691 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_exit);
13692 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_enter);
13693 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_vmgexit_msr_protocol_exit);
13694 
kvm_x86_init(void)13695 static int __init kvm_x86_init(void)
13696 {
13697 	kvm_mmu_x86_module_init();
13698 	mitigate_smt_rsb &= boot_cpu_has_bug(X86_BUG_SMT_RSB) && cpu_smt_possible();
13699 	return 0;
13700 }
13701 module_init(kvm_x86_init);
13702 
kvm_x86_exit(void)13703 static void __exit kvm_x86_exit(void)
13704 {
13705 	/*
13706 	 * If module_init() is implemented, module_exit() must also be
13707 	 * implemented to allow module unload.
13708 	 */
13709 }
13710 module_exit(kvm_x86_exit);
13711