xref: /openbmc/qemu/linux-headers/asm-riscv/kvm.h (revision 5f69e42d)
1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*
3  * Copyright (C) 2019 Western Digital Corporation or its affiliates.
4  *
5  * Authors:
6  *     Anup Patel <anup.patel@wdc.com>
7  */
8 
9 #ifndef __LINUX_KVM_RISCV_H
10 #define __LINUX_KVM_RISCV_H
11 
12 #ifndef __ASSEMBLY__
13 
14 #include <linux/types.h>
15 #include <asm/bitsperlong.h>
16 #include <asm/ptrace.h>
17 
18 #define __KVM_HAVE_IRQ_LINE
19 
20 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
21 
22 #define KVM_INTERRUPT_SET	-1U
23 #define KVM_INTERRUPT_UNSET	-2U
24 
25 /* for KVM_GET_REGS and KVM_SET_REGS */
26 struct kvm_regs {
27 };
28 
29 /* for KVM_GET_FPU and KVM_SET_FPU */
30 struct kvm_fpu {
31 };
32 
33 /* KVM Debug exit structure */
34 struct kvm_debug_exit_arch {
35 };
36 
37 /* for KVM_SET_GUEST_DEBUG */
38 struct kvm_guest_debug_arch {
39 };
40 
41 /* definition of registers in kvm_run */
42 struct kvm_sync_regs {
43 };
44 
45 /* for KVM_GET_SREGS and KVM_SET_SREGS */
46 struct kvm_sregs {
47 };
48 
49 /* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
50 struct kvm_riscv_config {
51 	unsigned long isa;
52 	unsigned long zicbom_block_size;
53 	unsigned long mvendorid;
54 	unsigned long marchid;
55 	unsigned long mimpid;
56 	unsigned long zicboz_block_size;
57 	unsigned long satp_mode;
58 };
59 
60 /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
61 struct kvm_riscv_core {
62 	struct user_regs_struct regs;
63 	unsigned long mode;
64 };
65 
66 /* Possible privilege modes for kvm_riscv_core */
67 #define KVM_RISCV_MODE_S	1
68 #define KVM_RISCV_MODE_U	0
69 
70 /* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
71 struct kvm_riscv_csr {
72 	unsigned long sstatus;
73 	unsigned long sie;
74 	unsigned long stvec;
75 	unsigned long sscratch;
76 	unsigned long sepc;
77 	unsigned long scause;
78 	unsigned long stval;
79 	unsigned long sip;
80 	unsigned long satp;
81 	unsigned long scounteren;
82 	unsigned long senvcfg;
83 };
84 
85 /* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
86 struct kvm_riscv_aia_csr {
87 	unsigned long siselect;
88 	unsigned long iprio1;
89 	unsigned long iprio2;
90 	unsigned long sieh;
91 	unsigned long siph;
92 	unsigned long iprio1h;
93 	unsigned long iprio2h;
94 };
95 
96 /* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
97 struct kvm_riscv_smstateen_csr {
98 	unsigned long sstateen0;
99 };
100 
101 /* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
102 struct kvm_riscv_timer {
103 	__u64 frequency;
104 	__u64 time;
105 	__u64 compare;
106 	__u64 state;
107 };
108 
109 /*
110  * ISA extension IDs specific to KVM. This is not the same as the host ISA
111  * extension IDs as that is internal to the host and should not be exposed
112  * to the guest. This should always be contiguous to keep the mapping simple
113  * in KVM implementation.
114  */
115 enum KVM_RISCV_ISA_EXT_ID {
116 	KVM_RISCV_ISA_EXT_A = 0,
117 	KVM_RISCV_ISA_EXT_C,
118 	KVM_RISCV_ISA_EXT_D,
119 	KVM_RISCV_ISA_EXT_F,
120 	KVM_RISCV_ISA_EXT_H,
121 	KVM_RISCV_ISA_EXT_I,
122 	KVM_RISCV_ISA_EXT_M,
123 	KVM_RISCV_ISA_EXT_SVPBMT,
124 	KVM_RISCV_ISA_EXT_SSTC,
125 	KVM_RISCV_ISA_EXT_SVINVAL,
126 	KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
127 	KVM_RISCV_ISA_EXT_ZICBOM,
128 	KVM_RISCV_ISA_EXT_ZICBOZ,
129 	KVM_RISCV_ISA_EXT_ZBB,
130 	KVM_RISCV_ISA_EXT_SSAIA,
131 	KVM_RISCV_ISA_EXT_V,
132 	KVM_RISCV_ISA_EXT_SVNAPOT,
133 	KVM_RISCV_ISA_EXT_ZBA,
134 	KVM_RISCV_ISA_EXT_ZBS,
135 	KVM_RISCV_ISA_EXT_ZICNTR,
136 	KVM_RISCV_ISA_EXT_ZICSR,
137 	KVM_RISCV_ISA_EXT_ZIFENCEI,
138 	KVM_RISCV_ISA_EXT_ZIHPM,
139 	KVM_RISCV_ISA_EXT_SMSTATEEN,
140 	KVM_RISCV_ISA_EXT_ZICOND,
141 	KVM_RISCV_ISA_EXT_ZBC,
142 	KVM_RISCV_ISA_EXT_ZBKB,
143 	KVM_RISCV_ISA_EXT_ZBKC,
144 	KVM_RISCV_ISA_EXT_ZBKX,
145 	KVM_RISCV_ISA_EXT_ZKND,
146 	KVM_RISCV_ISA_EXT_ZKNE,
147 	KVM_RISCV_ISA_EXT_ZKNH,
148 	KVM_RISCV_ISA_EXT_ZKR,
149 	KVM_RISCV_ISA_EXT_ZKSED,
150 	KVM_RISCV_ISA_EXT_ZKSH,
151 	KVM_RISCV_ISA_EXT_ZKT,
152 	KVM_RISCV_ISA_EXT_ZVBB,
153 	KVM_RISCV_ISA_EXT_ZVBC,
154 	KVM_RISCV_ISA_EXT_ZVKB,
155 	KVM_RISCV_ISA_EXT_ZVKG,
156 	KVM_RISCV_ISA_EXT_ZVKNED,
157 	KVM_RISCV_ISA_EXT_ZVKNHA,
158 	KVM_RISCV_ISA_EXT_ZVKNHB,
159 	KVM_RISCV_ISA_EXT_ZVKSED,
160 	KVM_RISCV_ISA_EXT_ZVKSH,
161 	KVM_RISCV_ISA_EXT_ZVKT,
162 	KVM_RISCV_ISA_EXT_ZFH,
163 	KVM_RISCV_ISA_EXT_ZFHMIN,
164 	KVM_RISCV_ISA_EXT_ZIHINTNTL,
165 	KVM_RISCV_ISA_EXT_ZVFH,
166 	KVM_RISCV_ISA_EXT_ZVFHMIN,
167 	KVM_RISCV_ISA_EXT_ZFA,
168 	KVM_RISCV_ISA_EXT_ZTSO,
169 	KVM_RISCV_ISA_EXT_ZACAS,
170 	KVM_RISCV_ISA_EXT_SSCOFPMF,
171 	KVM_RISCV_ISA_EXT_MAX,
172 };
173 
174 /*
175  * SBI extension IDs specific to KVM. This is not the same as the SBI
176  * extension IDs defined by the RISC-V SBI specification.
177  */
178 enum KVM_RISCV_SBI_EXT_ID {
179 	KVM_RISCV_SBI_EXT_V01 = 0,
180 	KVM_RISCV_SBI_EXT_TIME,
181 	KVM_RISCV_SBI_EXT_IPI,
182 	KVM_RISCV_SBI_EXT_RFENCE,
183 	KVM_RISCV_SBI_EXT_SRST,
184 	KVM_RISCV_SBI_EXT_HSM,
185 	KVM_RISCV_SBI_EXT_PMU,
186 	KVM_RISCV_SBI_EXT_EXPERIMENTAL,
187 	KVM_RISCV_SBI_EXT_VENDOR,
188 	KVM_RISCV_SBI_EXT_DBCN,
189 	KVM_RISCV_SBI_EXT_STA,
190 	KVM_RISCV_SBI_EXT_MAX,
191 };
192 
193 /* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
194 struct kvm_riscv_sbi_sta {
195 	unsigned long shmem_lo;
196 	unsigned long shmem_hi;
197 };
198 
199 /* Possible states for kvm_riscv_timer */
200 #define KVM_RISCV_TIMER_STATE_OFF	0
201 #define KVM_RISCV_TIMER_STATE_ON	1
202 
203 #define KVM_REG_SIZE(id)		\
204 	(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
205 
206 /* If you need to interpret the index values, here is the key: */
207 #define KVM_REG_RISCV_TYPE_MASK		0x00000000FF000000
208 #define KVM_REG_RISCV_TYPE_SHIFT	24
209 #define KVM_REG_RISCV_SUBTYPE_MASK	0x0000000000FF0000
210 #define KVM_REG_RISCV_SUBTYPE_SHIFT	16
211 
212 /* Config registers are mapped as type 1 */
213 #define KVM_REG_RISCV_CONFIG		(0x01 << KVM_REG_RISCV_TYPE_SHIFT)
214 #define KVM_REG_RISCV_CONFIG_REG(name)	\
215 	(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
216 
217 /* Core registers are mapped as type 2 */
218 #define KVM_REG_RISCV_CORE		(0x02 << KVM_REG_RISCV_TYPE_SHIFT)
219 #define KVM_REG_RISCV_CORE_REG(name)	\
220 		(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
221 
222 /* Control and status registers are mapped as type 3 */
223 #define KVM_REG_RISCV_CSR		(0x03 << KVM_REG_RISCV_TYPE_SHIFT)
224 #define KVM_REG_RISCV_CSR_GENERAL	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
225 #define KVM_REG_RISCV_CSR_AIA		(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
226 #define KVM_REG_RISCV_CSR_SMSTATEEN	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
227 #define KVM_REG_RISCV_CSR_REG(name)	\
228 		(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
229 #define KVM_REG_RISCV_CSR_AIA_REG(name)	\
230 	(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
231 #define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name)  \
232 	(offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
233 
234 /* Timer registers are mapped as type 4 */
235 #define KVM_REG_RISCV_TIMER		(0x04 << KVM_REG_RISCV_TYPE_SHIFT)
236 #define KVM_REG_RISCV_TIMER_REG(name)	\
237 		(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
238 
239 /* F extension registers are mapped as type 5 */
240 #define KVM_REG_RISCV_FP_F		(0x05 << KVM_REG_RISCV_TYPE_SHIFT)
241 #define KVM_REG_RISCV_FP_F_REG(name)	\
242 		(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
243 
244 /* D extension registers are mapped as type 6 */
245 #define KVM_REG_RISCV_FP_D		(0x06 << KVM_REG_RISCV_TYPE_SHIFT)
246 #define KVM_REG_RISCV_FP_D_REG(name)	\
247 		(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
248 
249 /* ISA Extension registers are mapped as type 7 */
250 #define KVM_REG_RISCV_ISA_EXT		(0x07 << KVM_REG_RISCV_TYPE_SHIFT)
251 #define KVM_REG_RISCV_ISA_SINGLE	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
252 #define KVM_REG_RISCV_ISA_MULTI_EN	(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
253 #define KVM_REG_RISCV_ISA_MULTI_DIS	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
254 #define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id)	\
255 		((__ext_id) / __BITS_PER_LONG)
256 #define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id)	\
257 		(1UL << ((__ext_id) % __BITS_PER_LONG))
258 #define KVM_REG_RISCV_ISA_MULTI_REG_LAST	\
259 		KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)
260 
261 /* SBI extension registers are mapped as type 8 */
262 #define KVM_REG_RISCV_SBI_EXT		(0x08 << KVM_REG_RISCV_TYPE_SHIFT)
263 #define KVM_REG_RISCV_SBI_SINGLE	(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
264 #define KVM_REG_RISCV_SBI_MULTI_EN	(0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
265 #define KVM_REG_RISCV_SBI_MULTI_DIS	(0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
266 #define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id)	\
267 		((__ext_id) / __BITS_PER_LONG)
268 #define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id)	\
269 		(1UL << ((__ext_id) % __BITS_PER_LONG))
270 #define KVM_REG_RISCV_SBI_MULTI_REG_LAST	\
271 		KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
272 
273 /* V extension registers are mapped as type 9 */
274 #define KVM_REG_RISCV_VECTOR		(0x09 << KVM_REG_RISCV_TYPE_SHIFT)
275 #define KVM_REG_RISCV_VECTOR_CSR_REG(name)	\
276 		(offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
277 #define KVM_REG_RISCV_VECTOR_REG(n)	\
278 		((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
279 
280 /* Registers for specific SBI extensions are mapped as type 10 */
281 #define KVM_REG_RISCV_SBI_STATE		(0x0a << KVM_REG_RISCV_TYPE_SHIFT)
282 #define KVM_REG_RISCV_SBI_STA		(0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
283 #define KVM_REG_RISCV_SBI_STA_REG(name)		\
284 		(offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
285 
286 /* Device Control API: RISC-V AIA */
287 #define KVM_DEV_RISCV_APLIC_ALIGN		0x1000
288 #define KVM_DEV_RISCV_APLIC_SIZE		0x4000
289 #define KVM_DEV_RISCV_APLIC_MAX_HARTS		0x4000
290 #define KVM_DEV_RISCV_IMSIC_ALIGN		0x1000
291 #define KVM_DEV_RISCV_IMSIC_SIZE		0x1000
292 
293 #define KVM_DEV_RISCV_AIA_GRP_CONFIG		0
294 #define KVM_DEV_RISCV_AIA_CONFIG_MODE		0
295 #define KVM_DEV_RISCV_AIA_CONFIG_IDS		1
296 #define KVM_DEV_RISCV_AIA_CONFIG_SRCS		2
297 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS	3
298 #define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT	4
299 #define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS	5
300 #define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS	6
301 
302 /*
303  * Modes of RISC-V AIA device:
304  * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
305  * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
306  * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
307  *    available otherwise fallback to trap-n-emulation
308  */
309 #define KVM_DEV_RISCV_AIA_MODE_EMUL		0
310 #define KVM_DEV_RISCV_AIA_MODE_HWACCEL		1
311 #define KVM_DEV_RISCV_AIA_MODE_AUTO		2
312 
313 #define KVM_DEV_RISCV_AIA_IDS_MIN		63
314 #define KVM_DEV_RISCV_AIA_IDS_MAX		2048
315 #define KVM_DEV_RISCV_AIA_SRCS_MAX		1024
316 #define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX	8
317 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN	24
318 #define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX	56
319 #define KVM_DEV_RISCV_AIA_HART_BITS_MAX		16
320 #define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX	8
321 
322 #define KVM_DEV_RISCV_AIA_GRP_ADDR		1
323 #define KVM_DEV_RISCV_AIA_ADDR_APLIC		0
324 #define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu)	(1 + (__vcpu))
325 #define KVM_DEV_RISCV_AIA_ADDR_MAX		\
326 		(1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
327 
328 #define KVM_DEV_RISCV_AIA_GRP_CTRL		2
329 #define KVM_DEV_RISCV_AIA_CTRL_INIT		0
330 
331 /*
332  * The device attribute type contains the memory mapped offset of the
333  * APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
334  */
335 #define KVM_DEV_RISCV_AIA_GRP_APLIC		3
336 
337 /*
338  * The lower 12-bits of the device attribute type contains the iselect
339  * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
340  * bits contains the VCPU id.
341  */
342 #define KVM_DEV_RISCV_AIA_GRP_IMSIC		4
343 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS	12
344 #define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK	\
345 		((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
346 #define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel)	\
347 		(((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
348 		 ((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
349 #define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr)	\
350 		((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
351 #define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr)	\
352 		((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
353 
354 /* One single KVM irqchip, ie. the AIA */
355 #define KVM_NR_IRQCHIPS			1
356 
357 #endif
358 
359 #endif /* __LINUX_KVM_RISCV_H */
360