1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Keystone2: Common SoC definitions, structures etc.
4  *
5  * (C) Copyright 2012-2014
6  *     Texas Instruments Incorporated, <www.ti.com>
7  */
8 #ifndef __ASM_ARCH_HARDWARE_H
9 #define __ASM_ARCH_HARDWARE_H
10 
11 #include <config.h>
12 
13 #ifndef __ASSEMBLY__
14 
15 #include <linux/sizes.h>
16 #include <asm/io.h>
17 
18 #define	REG(addr)        (*(volatile unsigned int *)(addr))
19 #define REG_P(addr)      ((volatile unsigned int *)(addr))
20 
21 typedef volatile unsigned int   dv_reg;
22 typedef volatile unsigned int   *dv_reg_p;
23 
24 #endif
25 
26 #define KS2_DDRPHY_PIR_OFFSET           0x04
27 #define KS2_DDRPHY_PGCR0_OFFSET         0x08
28 #define KS2_DDRPHY_PGCR1_OFFSET         0x0C
29 #define KS2_DDRPHY_PGSR0_OFFSET         0x10
30 #define KS2_DDRPHY_PGSR1_OFFSET         0x14
31 #define KS2_DDRPHY_PLLCR_OFFSET         0x18
32 #define KS2_DDRPHY_PTR0_OFFSET          0x1C
33 #define KS2_DDRPHY_PTR1_OFFSET          0x20
34 #define KS2_DDRPHY_PTR2_OFFSET          0x24
35 #define KS2_DDRPHY_PTR3_OFFSET          0x28
36 #define KS2_DDRPHY_PTR4_OFFSET          0x2C
37 #define KS2_DDRPHY_DCR_OFFSET           0x44
38 
39 #define KS2_DDRPHY_DTPR0_OFFSET         0x48
40 #define KS2_DDRPHY_DTPR1_OFFSET         0x4C
41 #define KS2_DDRPHY_DTPR2_OFFSET         0x50
42 
43 #define KS2_DDRPHY_MR0_OFFSET           0x54
44 #define KS2_DDRPHY_MR1_OFFSET           0x58
45 #define KS2_DDRPHY_MR2_OFFSET           0x5C
46 #define KS2_DDRPHY_DTCR_OFFSET          0x68
47 #define KS2_DDRPHY_PGCR2_OFFSET         0x8C
48 
49 #define KS2_DDRPHY_ZQ0CR1_OFFSET        0x184
50 #define KS2_DDRPHY_ZQ1CR1_OFFSET        0x194
51 #define KS2_DDRPHY_ZQ2CR1_OFFSET        0x1A4
52 #define KS2_DDRPHY_ZQ3CR1_OFFSET        0x1B4
53 
54 #define KS2_DDRPHY_DATX8_2_OFFSET       0x240
55 #define KS2_DDRPHY_DATX8_3_OFFSET       0x280
56 #define KS2_DDRPHY_DATX8_4_OFFSET       0x2C0
57 #define KS2_DDRPHY_DATX8_5_OFFSET       0x300
58 #define KS2_DDRPHY_DATX8_6_OFFSET       0x340
59 #define KS2_DDRPHY_DATX8_7_OFFSET       0x380
60 #define KS2_DDRPHY_DATX8_8_OFFSET       0x3C0
61 
62 #define IODDRM_MASK                     0x00000180
63 #define ZCKSEL_MASK                     0x01800000
64 #define CL_MASK                         0x00000072
65 #define WR_MASK                         0x00000E00
66 #define BL_MASK                         0x00000003
67 #define RRMODE_MASK                     0x00040000
68 #define UDIMM_MASK                      0x20000000
69 #define BYTEMASK_MASK                   0x0003FC00
70 #define MPRDQ_MASK                      0x00000080
71 #define PDQ_MASK                        0x00000070
72 #define NOSRA_MASK                      0x08000000
73 #define ECC_MASK                        0x00000001
74 #define DXEN_MASK                       0x00000001
75 
76 /* DDR3 definitions */
77 #define KS2_DDR3A_EMIF_CTRL_BASE	0x21010000
78 #define KS2_DDR3A_EMIF_DATA_BASE	0x80000000
79 #define KS2_DDR3A_DDRPHYC		0x02329000
80 #define EMIF1_BASE			KS2_DDR3A_EMIF_CTRL_BASE
81 
82 #define KS2_DDR3_MIDR_OFFSET            0x00
83 #define KS2_DDR3_STATUS_OFFSET          0x04
84 #define KS2_DDR3_SDCFG_OFFSET           0x08
85 #define KS2_DDR3_SDRFC_OFFSET           0x10
86 #define KS2_DDR3_SDTIM1_OFFSET          0x18
87 #define KS2_DDR3_SDTIM2_OFFSET          0x1C
88 #define KS2_DDR3_SDTIM3_OFFSET          0x20
89 #define KS2_DDR3_SDTIM4_OFFSET          0x28
90 #define KS2_DDR3_PMCTL_OFFSET           0x38
91 #define KS2_DDR3_ZQCFG_OFFSET           0xC8
92 
93 #define KS2_DDR3_PLLCTRL_PHY_RESET	0x80000000
94 
95 /* DDR3 ECC */
96 #define KS2_DDR3_ECC_INT_STATUS_OFFSET			0x0AC
97 #define KS2_DDR3_ECC_INT_ENABLE_SET_SYS_OFFSET		0x0B4
98 #define KS2_DDR3_ECC_CTRL_OFFSET			0x110
99 #define KS2_DDR3_ECC_ADDR_RANGE1_OFFSET			0x114
100 #define KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET		0x130
101 #define KS2_DDR3_ONE_BIT_ECC_ERR_ADDR_LOG_OFFSET	0x13C
102 
103 /* DDR3 ECC Interrupt Status register */
104 #define KS2_DDR3_1B_ECC_ERR_SYS		BIT(5)
105 #define KS2_DDR3_2B_ECC_ERR_SYS		BIT(4)
106 #define KS2_DDR3_WR_ECC_ERR_SYS		BIT(3)
107 
108 /* DDR3 ECC Control register */
109 #define KS2_DDR3_ECC_EN			BIT(31)
110 #define KS2_DDR3_ECC_ADDR_RNG_PROT	BIT(30)
111 #define KS2_DDR3_ECC_VERIFY_EN		BIT(29)
112 #define KS2_DDR3_ECC_RMW_EN		BIT(28)
113 #define KS2_DDR3_ECC_ADDR_RNG_1_EN	BIT(0)
114 
115 #define KS2_DDR3_ECC_ENABLE		(KS2_DDR3_ECC_EN | \
116 					KS2_DDR3_ECC_ADDR_RNG_PROT | \
117 					KS2_DDR3_ECC_VERIFY_EN)
118 
119 /* EDMA */
120 #define KS2_EDMA0_BASE			0x02700000
121 
122 /* EDMA3 register offsets */
123 #define KS2_EDMA_QCHMAP0		0x0200
124 #define KS2_EDMA_IPR			0x1068
125 #define KS2_EDMA_ICR			0x1070
126 #define KS2_EDMA_QEECR			0x1088
127 #define KS2_EDMA_QEESR			0x108c
128 #define KS2_EDMA_PARAM_1(x)		(0x4020 + (4 * x))
129 
130 /* NETCP pktdma */
131 #ifdef CONFIG_SOC_K2G
132 #define KS2_NETCP_PDMA_RX_FREE_QUEUE	113
133 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	114
134 #else
135 #define KS2_NETCP_PDMA_RX_FREE_QUEUE	4001
136 #define KS2_NETCP_PDMA_RX_RCV_QUEUE	4002
137 #endif
138 
139 /* Chip Interrupt Controller */
140 #define KS2_CIC2_BASE			0x02608000
141 
142 /* Chip Interrupt Controller register offsets */
143 #define KS2_CIC_CTRL			0x04
144 #define KS2_CIC_HOST_CTRL		0x0C
145 #define KS2_CIC_GLOBAL_ENABLE		0x10
146 #define KS2_CIC_SYS_ENABLE_IDX_SET	0x28
147 #define KS2_CIC_HOST_ENABLE_IDX_SET	0x34
148 #define KS2_CIC_CHAN_MAP(n)		(0x0400 + (n << 2))
149 
150 #define KS2_UART0_BASE                	0x02530c00
151 #define KS2_UART1_BASE                	0x02531000
152 
153 /* Boot Config */
154 #define KS2_DEVICE_STATE_CTRL_BASE	0x02620000
155 #define KS2_JTAG_ID_REG			(KS2_DEVICE_STATE_CTRL_BASE + 0x18)
156 #define KS2_DEVSTAT			(KS2_DEVICE_STATE_CTRL_BASE + 0x20)
157 #define KS2_DEVCFG			(KS2_DEVICE_STATE_CTRL_BASE + 0x14c)
158 #define KS2_ETHERNET_CFG		(KS2_DEVICE_STATE_CTRL_BASE + 0xe20)
159 #define KS2_ETHERNET_RGMII		2
160 
161 /* PSC */
162 #define KS2_PSC_BASE			0x02350000
163 #define KS2_LPSC_GEM_0			15
164 #define KS2_LPSC_TETRIS			52
165 #define KS2_TETRIS_PWR_DOMAIN		31
166 #define KS2_GEM_0_PWR_DOMAIN		8
167 
168 /* Chip configuration unlock codes and registers */
169 #define KS2_KICK0			(KS2_DEVICE_STATE_CTRL_BASE + 0x38)
170 #define KS2_KICK1			(KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
171 #define KS2_KICK0_MAGIC			0x83e70b13
172 #define KS2_KICK1_MAGIC			0x95a4f1e0
173 
174 /* PLL control registers */
175 #define KS2_MAINPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x350)
176 #define KS2_MAINPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x354)
177 #define KS2_PASSPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x358)
178 #define KS2_PASSPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
179 #define KS2_DDR3APLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x360)
180 #define KS2_DDR3APLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x364)
181 #define KS2_DDR3BPLLCTL0		(KS2_DEVICE_STATE_CTRL_BASE + 0x368)
182 #define KS2_DDR3BPLLCTL1		(KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
183 #define KS2_ARMPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x370)
184 #define KS2_ARMPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x374)
185 #define KS2_UARTPLLCTL0			(KS2_DEVICE_STATE_CTRL_BASE + 0x390)
186 #define KS2_UARTPLLCTL1			(KS2_DEVICE_STATE_CTRL_BASE + 0x394)
187 
188 #define KS2_PLL_CNTRL_BASE		0x02310000
189 #define KS2_CLOCK_BASE			KS2_PLL_CNTRL_BASE
190 #define KS2_RSTCTRL_RSTYPE		(KS2_PLL_CNTRL_BASE + 0xe4)
191 #define KS2_RSTCTRL			(KS2_PLL_CNTRL_BASE + 0xe8)
192 #define KS2_RSTCTRL_RSCFG		(KS2_PLL_CNTRL_BASE + 0xec)
193 #define KS2_RSTCTRL_KEY			0x5a69
194 #define KS2_RSTCTRL_MASK		0xffff0000
195 #define KS2_RSTCTRL_SWRST		0xfffe0000
196 #define KS2_RSTYPE_PLL_SOFT		BIT(13)
197 
198 /* SPI */
199 #ifdef CONFIG_SOC_K2G
200 #define KS2_SPI0_BASE			0x21805400
201 #define KS2_SPI1_BASE			0x21805800
202 #define KS2_SPI2_BASE			0x21805c00
203 #define KS2_SPI3_BASE			0x21806000
204 #else
205 #define KS2_SPI0_BASE			0x21000400
206 #define KS2_SPI1_BASE			0x21000600
207 #define KS2_SPI2_BASE			0x21000800
208 #define KS2_SPI_BASE			KS2_SPI0_BASE
209 #endif
210 
211 /* AEMIF */
212 #define KS2_AEMIF_CNTRL_BASE       	0x21000a00
213 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE   KS2_AEMIF_CNTRL_BASE
214 
215 /* Flag from ks2_debug options to check if DSPs need to stay ON */
216 #define DBG_LEAVE_DSPS_ON		0x1
217 
218 /* MSMC control */
219 #define KS2_MSMC_CTRL_BASE		0x0bc00000
220 #define KS2_MSMC_DATA_BASE		0x0c000000
221 
222 /* KS2 Generic Privilege ID Settings for MSMC2 */
223 #define KS2_MSMC_SEGMENT_C6X_0		0
224 #define KS2_MSMC_SEGMENT_C6X_1		1
225 #define KS2_MSMC_SEGMENT_C6X_2		2
226 #define KS2_MSMC_SEGMENT_C6X_3		3
227 #define KS2_MSMC_SEGMENT_C6X_4		4
228 #define KS2_MSMC_SEGMENT_C6X_5		5
229 #define KS2_MSMC_SEGMENT_C6X_6		6
230 #define KS2_MSMC_SEGMENT_C6X_7		7
231 
232 #define KS2_MSMC_SEGMENT_DEBUG		12
233 
234 /* KS2 HK/L/E MSMC PRIVIDs  for MSMC2 */
235 #define K2HKLE_MSMC_SEGMENT_ARM		8
236 #define K2HKLE_MSMC_SEGMENT_NETCP	9
237 #define K2HKLE_MSMC_SEGMENT_QM_PDSP	10
238 #define K2HKLE_MSMC_SEGMENT_PCIE0	11
239 
240 /* K2HK specific Privilege ID Settings */
241 #define K2HKE_MSMC_SEGMENT_HYPERLINK	14
242 
243 /* K2L specific Privilege ID Settings */
244 #define K2L_MSMC_SEGMENT_PCIE1		14
245 
246 /* K2E specific Privilege ID Settings */
247 #define K2E_MSMC_SEGMENT_PCIE1		13
248 #define K2E_MSMC_SEGMENT_TSIP		15
249 
250 /* K2G specific Privilege ID Settings */
251 #define K2G_MSMC_SEGMENT_ARM		1
252 #define K2G_MSMC_SEGMENT_ICSS0		2
253 #define K2G_MSMC_SEGMENT_ICSS1		3
254 #define K2G_MSMC_SEGMENT_NSS		4
255 #define K2G_MSMC_SEGMENT_PCIE		5
256 #define K2G_MSMC_SEGMENT_USB		6
257 #define K2G_MSMC_SEGMENT_MLB		8
258 #define K2G_MSMC_SEGMENT_PMMC		9
259 #define K2G_MSMC_SEGMENT_DSS		10
260 #define K2G_MSMC_SEGMENT_MMC		11
261 
262 /* MSMC segment size shift bits */
263 #define KS2_MSMC_SEG_SIZE_SHIFT		12
264 #define KS2_MSMC_MAP_SEG_NUM		(2 << (30 - KS2_MSMC_SEG_SIZE_SHIFT))
265 #define KS2_MSMC_DST_SEG_BASE		(CONFIG_SYS_LPAE_SDRAM_BASE >> \
266 					KS2_MSMC_SEG_SIZE_SHIFT)
267 
268 /* Device speed */
269 #define KS2_REV1_DEVSPEED		(KS2_DEVICE_STATE_CTRL_BASE + 0xc98)
270 #define KS2_EFUSE_BOOTROM		(KS2_DEVICE_STATE_CTRL_BASE + 0xc90)
271 #define KS2_MISC_CTRL			(KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
272 
273 /* Queue manager */
274 #ifdef CONFIG_SOC_K2G
275 #define KS2_QM_BASE_ADDRESS		0x040C0000
276 #define KS2_QM_CONF_BASE		0x04040000
277 #define KS2_QM_DESC_SETUP_BASE		0x04080000
278 #define KS2_QM_STATUS_RAM_BASE		0x0 /* K2G doesn't have it */
279 #define KS2_QM_INTD_CONF_BASE		0x0
280 #define KS2_QM_PDSP1_CMD_BASE		0x0
281 #define KS2_QM_PDSP1_CTRL_BASE		0x0
282 #define KS2_QM_PDSP1_IRAM_BASE		0x0
283 #define KS2_QM_MANAGER_QUEUES_BASE	0x040c0000
284 #define KS2_QM_MANAGER_Q_PROXY_BASE	0x04040200
285 #define KS2_QM_QUEUE_STATUS_BASE	0x04100000
286 #define KS2_QM_LINK_RAM_BASE		0x04020000
287 #define KS2_QM_REGION_NUM		8
288 #define KS2_QM_QPOOL_NUM		112
289 #else
290 #define KS2_QM_BASE_ADDRESS		0x23a80000
291 #define KS2_QM_CONF_BASE		0x02a02000
292 #define KS2_QM_DESC_SETUP_BASE		0x02a03000
293 #define KS2_QM_STATUS_RAM_BASE		0x02a06000
294 #define KS2_QM_INTD_CONF_BASE		0x02a0c000
295 #define KS2_QM_PDSP1_CMD_BASE		0x02a20000
296 #define KS2_QM_PDSP1_CTRL_BASE		0x02a0f000
297 #define KS2_QM_PDSP1_IRAM_BASE		0x02a10000
298 #define KS2_QM_MANAGER_QUEUES_BASE	0x02a80000
299 #define KS2_QM_MANAGER_Q_PROXY_BASE	0x02ac0000
300 #define KS2_QM_QUEUE_STATUS_BASE	0x02a40000
301 #define KS2_QM_LINK_RAM_BASE		0x00100000
302 #define KS2_QM_REGION_NUM		64
303 #define KS2_QM_QPOOL_NUM		4000
304 #endif
305 
306 /* USB */
307 #define KS2_USB_SS_BASE			0x02680000
308 #define KS2_USB_HOST_XHCI_BASE		(KS2_USB_SS_BASE + 0x10000)
309 #define KS2_DEV_USB_PHY_BASE		0x02620738
310 #define KS2_USB_PHY_CFG_BASE		0x02630000
311 
312 #define KS2_MAC_ID_BASE_ADDR		(KS2_DEVICE_STATE_CTRL_BASE + 0x110)
313 
314 /* SGMII SerDes */
315 #define KS2_SGMII_SERDES_BASE		0x0232a000
316 
317 /* JTAG ID register */
318 #define JTAGID_VARIANT_SHIFT	28
319 #define JTAGID_VARIANT_MASK	(0xf << 28)
320 #define JTAGID_PART_NUM_SHIFT	12
321 #define JTAGID_PART_NUM_MASK	(0xffff << 12)
322 
323 /* PART NUMBER definitions */
324 #define CPU_66AK2Hx	0xb981
325 #define CPU_66AK2Ex	0xb9a6
326 #define CPU_66AK2Lx	0xb9a7
327 #define CPU_66AK2Gx	0xbb06
328 
329 /* Variant definitions */
330 #define CPU_66AK2G1x	0x08
331 
332 /* DEVSPEED register */
333 #define DEVSPEED_DEVSPEED_SHIFT	16
334 #define DEVSPEED_DEVSPEED_MASK	(0xfff << 16)
335 #define DEVSPEED_ARMSPEED_SHIFT	0
336 #define DEVSPEED_ARMSPEED_MASK	0xfff
337 #define DEVSPEED_NUMSPDS	12
338 
339 #ifdef CONFIG_SOC_K2HK
340 #include <asm/arch/hardware-k2hk.h>
341 #endif
342 
343 #ifdef CONFIG_SOC_K2E
344 #include <asm/arch/hardware-k2e.h>
345 #endif
346 
347 #ifdef CONFIG_SOC_K2L
348 #include <asm/arch/hardware-k2l.h>
349 #endif
350 
351 #ifdef CONFIG_SOC_K2G
352 #include <asm/arch/hardware-k2g.h>
353 #endif
354 
355 #ifndef __ASSEMBLY__
356 
get_part_number(void)357 static inline u16 get_part_number(void)
358 {
359 	u32 jtag_id = __raw_readl(KS2_JTAG_ID_REG);
360 
361 	return (jtag_id & JTAGID_PART_NUM_MASK) >> JTAGID_PART_NUM_SHIFT;
362 }
363 
cpu_is_k2hk(void)364 static inline u8 cpu_is_k2hk(void)
365 {
366 	return get_part_number() == CPU_66AK2Hx;
367 }
368 
cpu_is_k2e(void)369 static inline u8 cpu_is_k2e(void)
370 {
371 	return get_part_number() == CPU_66AK2Ex;
372 }
373 
cpu_is_k2l(void)374 static inline u8 cpu_is_k2l(void)
375 {
376 	return get_part_number() == CPU_66AK2Lx;
377 }
378 
cpu_is_k2g(void)379 static inline u8 cpu_is_k2g(void)
380 {
381 	return get_part_number() == CPU_66AK2Gx;
382 }
383 
cpu_revision(void)384 static inline u8 cpu_revision(void)
385 {
386 	u32 jtag_id	= __raw_readl(KS2_JTAG_ID_REG);
387 	u8 rev	= (jtag_id & JTAGID_VARIANT_MASK) >> JTAGID_VARIANT_SHIFT;
388 
389 	return rev;
390 }
391 
392 int cpu_to_bus(u32 *ptr, u32 length);
393 void sdelay(unsigned long);
394 
395 #endif
396 
397 #endif /* __ASM_ARCH_HARDWARE_H */
398