1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de
5 */
6
7 #include <common.h>
8 #include <nand.h>
9 #include <asm/io.h>
10
11 #define CONFIG_NAND_MODE_REG (void *)(CONFIG_SYS_NAND_BASE + 0x20000)
12 #define CONFIG_NAND_DATA_REG (void *)(CONFIG_SYS_NAND_BASE + 0x30000)
13
14 #define read_mode() in_8(CONFIG_NAND_MODE_REG)
15 #define write_mode(val) out_8(CONFIG_NAND_MODE_REG, val)
16 #define read_data() in_8(CONFIG_NAND_DATA_REG)
17 #define write_data(val) out_8(CONFIG_NAND_DATA_REG, val)
18
19 #define KPN_RDY2 (1 << 7)
20 #define KPN_RDY1 (1 << 6)
21 #define KPN_WPN (1 << 4)
22 #define KPN_CE2N (1 << 3)
23 #define KPN_CE1N (1 << 2)
24 #define KPN_ALE (1 << 1)
25 #define KPN_CLE (1 << 0)
26
27 #define KPN_DEFAULT_CHIP_DELAY 50
28
kpn_chip_ready(void)29 static int kpn_chip_ready(void)
30 {
31 if (read_mode() & KPN_RDY1)
32 return 1;
33
34 return 0;
35 }
36
kpn_wait_rdy(void)37 static void kpn_wait_rdy(void)
38 {
39 int cnt = 1000000;
40
41 while (--cnt && !kpn_chip_ready())
42 udelay(1);
43
44 if (!cnt)
45 printf ("timeout while waiting for RDY\n");
46 }
47
kpn_nand_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)48 static void kpn_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
49 {
50 u8 reg_val = read_mode();
51
52 if (ctrl & NAND_CTRL_CHANGE) {
53 reg_val = reg_val & ~(KPN_ALE + KPN_CLE);
54
55 if (ctrl & NAND_CLE)
56 reg_val = reg_val | KPN_CLE;
57 if (ctrl & NAND_ALE)
58 reg_val = reg_val | KPN_ALE;
59 if (ctrl & NAND_NCE)
60 reg_val = reg_val & ~KPN_CE1N;
61 else
62 reg_val = reg_val | KPN_CE1N;
63
64 write_mode(reg_val);
65 }
66 if (cmd != NAND_CMD_NONE)
67 write_data(cmd);
68
69 /* wait until flash is ready */
70 kpn_wait_rdy();
71 }
72
kpn_nand_read_byte(struct mtd_info * mtd)73 static u_char kpn_nand_read_byte(struct mtd_info *mtd)
74 {
75 return read_data();
76 }
77
kpn_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)78 static void kpn_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
79 {
80 int i;
81
82 for (i = 0; i < len; i++) {
83 write_data(buf[i]);
84 kpn_wait_rdy();
85 }
86 }
87
kpn_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)88 static void kpn_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
89 {
90 int i;
91
92 for (i = 0; i < len; i++)
93 buf[i] = read_data();
94 }
95
kpn_nand_dev_ready(struct mtd_info * mtd)96 static int kpn_nand_dev_ready(struct mtd_info *mtd)
97 {
98 kpn_wait_rdy();
99
100 return 1;
101 }
102
board_nand_init(struct nand_chip * nand)103 int board_nand_init(struct nand_chip *nand)
104 {
105 #if defined(CONFIG_NAND_ECC_BCH)
106 nand->ecc.mode = NAND_ECC_SOFT_BCH;
107 #else
108 nand->ecc.mode = NAND_ECC_SOFT;
109 #endif
110
111 /* Reference hardware control function */
112 nand->cmd_ctrl = kpn_nand_hwcontrol;
113 nand->read_byte = kpn_nand_read_byte;
114 nand->write_buf = kpn_nand_write_buf;
115 nand->read_buf = kpn_nand_read_buf;
116 nand->dev_ready = kpn_nand_dev_ready;
117 nand->chip_delay = KPN_DEFAULT_CHIP_DELAY;
118
119 /* reset mode register */
120 write_mode(KPN_CE1N + KPN_CE2N + KPN_WPN);
121 return 0;
122 }
123