xref: /openbmc/qemu/target/riscv/debug.h (revision 6ce1c9d0)
1 /*
2  * QEMU RISC-V Native Debug Support
3  *
4  * Copyright (c) 2022 Wind River Systems, Inc.
5  *
6  * Author:
7  *   Bin Meng <bin.meng@windriver.com>
8  *
9  * This program is free software; you can redistribute it and/or modify it
10  * under the terms and conditions of the GNU General Public License,
11  * version 2 or later, as published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program.  If not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #ifndef RISCV_DEBUG_H
23 #define RISCV_DEBUG_H
24 
25 #include "exec/breakpoint.h"
26 
27 #define RV_MAX_TRIGGERS         2
28 
29 /* register index of tdata CSRs */
30 enum {
31     TDATA1 = 0,
32     TDATA2,
33     TDATA3,
34     TDATA_NUM
35 };
36 
37 typedef enum {
38     TRIGGER_TYPE_NO_EXIST = 0,      /* trigger does not exist */
39     TRIGGER_TYPE_AD_MATCH = 2,      /* address/data match trigger */
40     TRIGGER_TYPE_INST_CNT = 3,      /* instruction count trigger */
41     TRIGGER_TYPE_INT = 4,           /* interrupt trigger */
42     TRIGGER_TYPE_EXCP = 5,          /* exception trigger */
43     TRIGGER_TYPE_AD_MATCH6 = 6,     /* new address/data match trigger */
44     TRIGGER_TYPE_EXT_SRC = 7,       /* external source trigger */
45     TRIGGER_TYPE_UNAVAIL = 15,      /* trigger exists, but unavailable */
46     TRIGGER_TYPE_NUM
47 } trigger_type_t;
48 
49 /* actions */
50 typedef enum {
51     DBG_ACTION_NONE = -1,           /* sentinel value */
52     DBG_ACTION_BP = 0,
53     DBG_ACTION_DBG_MODE,
54     DBG_ACTION_TRACE0,
55     DBG_ACTION_TRACE1,
56     DBG_ACTION_TRACE2,
57     DBG_ACTION_TRACE3,
58     DBG_ACTION_EXT_DBG0 = 8,
59     DBG_ACTION_EXT_DBG1
60 } trigger_action_t;
61 
62 /* tdata1 field masks */
63 
64 #define RV32_TYPE(t)    ((uint32_t)(t) << 28)
65 #define RV32_TYPE_MASK  (0xf << 28)
66 #define RV32_DMODE      BIT(27)
67 #define RV32_DATA_MASK  0x7ffffff
68 #define RV64_TYPE(t)    ((uint64_t)(t) << 60)
69 #define RV64_TYPE_MASK  (0xfULL << 60)
70 #define RV64_DMODE      BIT_ULL(59)
71 #define RV64_DATA_MASK  0x7ffffffffffffff
72 
73 /* mcontrol field masks */
74 
75 #define TYPE2_LOAD      BIT(0)
76 #define TYPE2_STORE     BIT(1)
77 #define TYPE2_EXEC      BIT(2)
78 #define TYPE2_U         BIT(3)
79 #define TYPE2_S         BIT(4)
80 #define TYPE2_M         BIT(6)
81 #define TYPE2_MATCH     (0xf << 7)
82 #define TYPE2_CHAIN     BIT(11)
83 #define TYPE2_ACTION    (0xf << 12)
84 #define TYPE2_SIZELO    (0x3 << 16)
85 #define TYPE2_TIMING    BIT(18)
86 #define TYPE2_SELECT    BIT(19)
87 #define TYPE2_HIT       BIT(20)
88 #define TYPE2_SIZEHI    (0x3 << 21) /* RV64 only */
89 
90 /* mcontrol6 field masks */
91 
92 #define TYPE6_LOAD      BIT(0)
93 #define TYPE6_STORE     BIT(1)
94 #define TYPE6_EXEC      BIT(2)
95 #define TYPE6_U         BIT(3)
96 #define TYPE6_S         BIT(4)
97 #define TYPE6_M         BIT(6)
98 #define TYPE6_MATCH     (0xf << 7)
99 #define TYPE6_CHAIN     BIT(11)
100 #define TYPE6_ACTION    (0xf << 12)
101 #define TYPE6_SIZE      (0xf << 16)
102 #define TYPE6_TIMING    BIT(20)
103 #define TYPE6_SELECT    BIT(21)
104 #define TYPE6_HIT       BIT(22)
105 #define TYPE6_VU        BIT(23)
106 #define TYPE6_VS        BIT(24)
107 
108 /* access size */
109 enum {
110     SIZE_ANY = 0,
111     SIZE_1B,
112     SIZE_2B,
113     SIZE_4B,
114     SIZE_6B,
115     SIZE_8B,
116     SIZE_10B,
117     SIZE_12B,
118     SIZE_14B,
119     SIZE_16B,
120     SIZE_NUM = 16
121 };
122 
123 /* itrigger filed masks */
124 #define ITRIGGER_ACTION       0x3f
125 #define ITRIGGER_U            BIT(6)
126 #define ITRIGGER_S            BIT(7)
127 #define ITRIGGER_PENDING      BIT(8)
128 #define ITRIGGER_M            BIT(9)
129 #define ITRIGGER_COUNT        (0x3fff << 10)
130 #define ITRIGGER_HIT          BIT(24)
131 #define ITRIGGER_VU           BIT(25)
132 #define ITRIGGER_VS           BIT(26)
133 
134 bool tdata_available(CPURISCVState *env, int tdata_index);
135 
136 target_ulong tselect_csr_read(CPURISCVState *env);
137 void tselect_csr_write(CPURISCVState *env, target_ulong val);
138 
139 target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
140 void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
141 
142 target_ulong tinfo_csr_read(CPURISCVState *env);
143 
144 void riscv_cpu_debug_excp_handler(CPUState *cs);
145 bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
146 bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
147 
148 void riscv_trigger_realize(CPURISCVState *env);
149 void riscv_trigger_reset_hold(CPURISCVState *env);
150 
151 bool riscv_itrigger_enabled(CPURISCVState *env);
152 void riscv_itrigger_update_priv(CPURISCVState *env);
153 #endif /* RISCV_DEBUG_H */
154