1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include <linux/pm_qos.h>
36
37 #include <drm/ttm/ttm_device.h>
38
39 #include "display/intel_display_limits.h"
40 #include "display/intel_display_core.h"
41
42 #include "gem/i915_gem_context_types.h"
43 #include "gem/i915_gem_shrinker.h"
44 #include "gem/i915_gem_stolen.h"
45
46 #include "gt/intel_engine.h"
47 #include "gt/intel_gt_types.h"
48 #include "gt/intel_region_lmem.h"
49 #include "gt/intel_workarounds.h"
50 #include "gt/uc/intel_uc.h"
51
52 #include "soc/intel_pch.h"
53
54 #include "i915_drm_client.h"
55 #include "i915_gem.h"
56 #include "i915_gpu_error.h"
57 #include "i915_params.h"
58 #include "i915_perf_types.h"
59 #include "i915_scheduler.h"
60 #include "i915_utils.h"
61 #include "intel_device_info.h"
62 #include "intel_memory_region.h"
63 #include "intel_runtime_pm.h"
64 #include "intel_step.h"
65 #include "intel_uncore.h"
66
67 struct drm_i915_clock_gating_funcs;
68 struct vlv_s0ix_state;
69 struct intel_pxp;
70
71 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
72
73 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
74 struct i915_dsm {
75 /*
76 * The start and end of DSM which we can optionally use to create GEM
77 * objects backed by stolen memory.
78 *
79 * Note that usable_size tells us exactly how much of this we are
80 * actually allowed to use, given that some portion of it is in fact
81 * reserved for use by hardware functions.
82 */
83 struct resource stolen;
84
85 /*
86 * Reserved portion of DSM.
87 */
88 struct resource reserved;
89
90 /*
91 * Total size minus reserved ranges.
92 *
93 * DSM is segmented in hardware with different portions offlimits to
94 * certain functions.
95 *
96 * The drm_mm is initialised to the total accessible range, as found
97 * from the PCI config. On Broadwell+, this is further restricted to
98 * avoid the first page! The upper end of DSM is reserved for hardware
99 * functions and similarly removed from the accessible range.
100 */
101 resource_size_t usable_size;
102 };
103
104 struct i915_suspend_saved_registers {
105 u32 saveDSPARB;
106 u32 saveSWF0[16];
107 u32 saveSWF1[16];
108 u32 saveSWF3[3];
109 u16 saveGCDGMBUS;
110 };
111
112 #define MAX_L3_SLICES 2
113 struct intel_l3_parity {
114 u32 *remap_info[MAX_L3_SLICES];
115 struct work_struct error_work;
116 int which_slice;
117 };
118
119 struct i915_gem_mm {
120 /*
121 * Shortcut for the stolen region. This points to either
122 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
123 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
124 * support stolen.
125 */
126 struct intel_memory_region *stolen_region;
127 /** Memory allocator for GTT stolen memory */
128 struct drm_mm stolen;
129 /** Protects the usage of the GTT stolen memory allocator. This is
130 * always the inner lock when overlapping with struct_mutex. */
131 struct mutex stolen_lock;
132
133 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
134 spinlock_t obj_lock;
135
136 /**
137 * List of objects which are purgeable.
138 */
139 struct list_head purge_list;
140
141 /**
142 * List of objects which have allocated pages and are shrinkable.
143 */
144 struct list_head shrink_list;
145
146 /**
147 * List of objects which are pending destruction.
148 */
149 struct llist_head free_list;
150 struct work_struct free_work;
151 /**
152 * Count of objects pending destructions. Used to skip needlessly
153 * waiting on an RCU barrier if no objects are waiting to be freed.
154 */
155 atomic_t free_count;
156
157 /**
158 * tmpfs instance used for shmem backed objects
159 */
160 struct vfsmount *gemfs;
161
162 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
163
164 struct notifier_block oom_notifier;
165 struct notifier_block vmap_notifier;
166 struct shrinker shrinker;
167
168 #ifdef CONFIG_MMU_NOTIFIER
169 /**
170 * notifier_lock for mmu notifiers, memory may not be allocated
171 * while holding this lock.
172 */
173 rwlock_t notifier_lock;
174 #endif
175
176 /* shrinker accounting, also useful for userland debugging */
177 u64 shrink_memory;
178 u32 shrink_count;
179 };
180
181 struct i915_virtual_gpu {
182 struct mutex lock; /* serialises sending of g2v_notify command pkts */
183 bool active;
184 u32 caps;
185 u32 *initial_mmio;
186 u8 *initial_cfg_space;
187 struct list_head entry;
188 };
189
190 struct i915_selftest_stash {
191 atomic_t counter;
192 struct ida mock_region_instances;
193 };
194
195 struct drm_i915_private {
196 struct drm_device drm;
197
198 struct intel_display display;
199
200 /* FIXME: Device release actions should all be moved to drmm_ */
201 bool do_release;
202
203 /* i915 device parameters */
204 struct i915_params params;
205
206 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
207 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
208 struct intel_driver_caps caps;
209
210 struct i915_dsm dsm;
211
212 struct intel_uncore uncore;
213 struct intel_uncore_mmio_debug mmio_debug;
214
215 struct i915_virtual_gpu vgpu;
216
217 struct intel_gvt *gvt;
218
219 struct {
220 struct pci_dev *pdev;
221 struct resource mch_res;
222 bool mchbar_need_disable;
223 } gmch;
224
225 struct rb_root uabi_engines;
226 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
227
228 /* protects the irq masks */
229 spinlock_t irq_lock;
230
231 bool display_irqs_enabled;
232
233 /* Sideband mailbox protection */
234 struct mutex sb_lock;
235 struct pm_qos_request sb_qos;
236
237 /** Cached value of IMR to avoid reads in updating the bitfield */
238 union {
239 u32 irq_mask;
240 u32 de_irq_mask[I915_MAX_PIPES];
241 };
242 u32 pipestat_irq_mask[I915_MAX_PIPES];
243
244 bool preserve_bios_swizzle;
245
246 unsigned int fsb_freq, mem_freq, is_ddr3;
247 unsigned int skl_preferred_vco_freq;
248
249 unsigned int max_dotclk_freq;
250 unsigned int hpll_freq;
251 unsigned int czclk_freq;
252
253 /**
254 * wq - Driver workqueue for GEM.
255 *
256 * NOTE: Work items scheduled here are not allowed to grab any modeset
257 * locks, for otherwise the flushing done in the pageflip code will
258 * result in deadlocks.
259 */
260 struct workqueue_struct *wq;
261
262 /**
263 * unordered_wq - internal workqueue for unordered work
264 *
265 * This workqueue should be used for all unordered work
266 * scheduling within i915, which used to be scheduled on the
267 * system_wq before moving to a driver instance due
268 * deprecation of flush_scheduled_work().
269 */
270 struct workqueue_struct *unordered_wq;
271
272 /* pm private clock gating functions */
273 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
274
275 /* PCH chipset type */
276 enum intel_pch pch_type;
277 unsigned short pch_id;
278
279 unsigned long gem_quirks;
280
281 struct i915_gem_mm mm;
282
283 struct intel_l3_parity l3_parity;
284
285 /*
286 * edram size in MB.
287 * Cannot be determined by PCIID. You must always read a register.
288 */
289 u32 edram_size_mb;
290
291 struct i915_gpu_error gpu_error;
292
293 u32 suspend_count;
294 struct i915_suspend_saved_registers regfile;
295 struct vlv_s0ix_state *vlv_s0ix_state;
296
297 struct dram_info {
298 bool wm_lv_0_adjust_needed;
299 u8 num_channels;
300 bool symmetric_memory;
301 enum intel_dram_type {
302 INTEL_DRAM_UNKNOWN,
303 INTEL_DRAM_DDR3,
304 INTEL_DRAM_DDR4,
305 INTEL_DRAM_LPDDR3,
306 INTEL_DRAM_LPDDR4,
307 INTEL_DRAM_DDR5,
308 INTEL_DRAM_LPDDR5,
309 } type;
310 u8 num_qgv_points;
311 u8 num_psf_gv_points;
312 } dram_info;
313
314 struct intel_runtime_pm runtime_pm;
315
316 struct i915_perf perf;
317
318 struct i915_hwmon *hwmon;
319
320 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
321 struct intel_gt gt0;
322
323 /*
324 * i915->gt[0] == &i915->gt0
325 */
326 struct intel_gt *gt[I915_MAX_GT];
327
328 struct kobject *sysfs_gt;
329
330 /* Quick lookup of media GT (current platforms only have one) */
331 struct intel_gt *media_gt;
332
333 struct {
334 struct i915_gem_contexts {
335 spinlock_t lock; /* locks list */
336 struct list_head list;
337 } contexts;
338
339 /*
340 * We replace the local file with a global mappings as the
341 * backing storage for the mmap is on the device and not
342 * on the struct file, and we do not want to prolong the
343 * lifetime of the local fd. To minimise the number of
344 * anonymous inodes we create, we use a global singleton to
345 * share the global mapping.
346 */
347 struct file *mmap_singleton;
348 } gem;
349
350 struct intel_pxp *pxp;
351
352 /* For i915gm/i945gm vblank irq workaround */
353 u8 vblank_enabled;
354
355 bool irq_enabled;
356
357 struct i915_pmu pmu;
358
359 /* The TTM device structure. */
360 struct ttm_device bdev;
361
362 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
363
364 /*
365 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
366 * will be rejected. Instead look for a better place.
367 */
368 };
369
to_i915(const struct drm_device * dev)370 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
371 {
372 return container_of(dev, struct drm_i915_private, drm);
373 }
374
kdev_to_i915(struct device * kdev)375 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
376 {
377 return dev_get_drvdata(kdev);
378 }
379
pdev_to_i915(struct pci_dev * pdev)380 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
381 {
382 return pci_get_drvdata(pdev);
383 }
384
to_gt(struct drm_i915_private * i915)385 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
386 {
387 return &i915->gt0;
388 }
389
390 /* Simple iterator over all initialised engines */
391 #define for_each_engine(engine__, gt__, id__) \
392 for ((id__) = 0; \
393 (id__) < I915_NUM_ENGINES; \
394 (id__)++) \
395 for_each_if ((engine__) = (gt__)->engine[(id__)])
396
397 /* Iterator over subset of engines selected by mask */
398 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
399 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
400 (tmp__) ? \
401 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
402 0;)
403
404 #define rb_to_uabi_engine(rb) \
405 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
406
407 #define for_each_uabi_engine(engine__, i915__) \
408 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
409 (engine__); \
410 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
411
412 #define for_each_uabi_class_engine(engine__, class__, i915__) \
413 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
414 (engine__) && (engine__)->uabi_class == (class__); \
415 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
416
417 #define INTEL_INFO(i915) ((i915)->__info)
418 #define RUNTIME_INFO(i915) (&(i915)->__runtime)
419 #define DISPLAY_INFO(i915) ((i915)->display.info.__device_info)
420 #define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info)
421 #define DRIVER_CAPS(i915) (&(i915)->caps)
422
423 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
424
425 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
426
427 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
428 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
429 RUNTIME_INFO(i915)->graphics.ip.rel)
430 #define IS_GRAPHICS_VER(i915, from, until) \
431 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
432
433 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
434 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
435 RUNTIME_INFO(i915)->media.ip.rel)
436 #define IS_MEDIA_VER(i915, from, until) \
437 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
438
439 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
440 #define IS_DISPLAY_VER(i915, from, until) \
441 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
442
443 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision)
444
445 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
446 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
447 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
448 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
449
450 #define IS_DISPLAY_STEP(__i915, since, until) \
451 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
452 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
453
454 #define IS_GRAPHICS_STEP(__i915, since, until) \
455 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
456 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
457
458 #define IS_MEDIA_STEP(__i915, since, until) \
459 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
460 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
461
462 #define IS_BASEDIE_STEP(__i915, since, until) \
463 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
464 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
465
466 static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info * info,enum intel_platform p)467 __platform_mask_index(const struct intel_runtime_info *info,
468 enum intel_platform p)
469 {
470 const unsigned int pbits =
471 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
472
473 /* Expand the platform_mask array if this fails. */
474 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
475 pbits * ARRAY_SIZE(info->platform_mask));
476
477 return p / pbits;
478 }
479
480 static __always_inline unsigned int
__platform_mask_bit(const struct intel_runtime_info * info,enum intel_platform p)481 __platform_mask_bit(const struct intel_runtime_info *info,
482 enum intel_platform p)
483 {
484 const unsigned int pbits =
485 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
486
487 return p % pbits + INTEL_SUBPLATFORM_BITS;
488 }
489
490 static inline u32
intel_subplatform(const struct intel_runtime_info * info,enum intel_platform p)491 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
492 {
493 const unsigned int pi = __platform_mask_index(info, p);
494
495 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
496 }
497
498 static __always_inline bool
IS_PLATFORM(const struct drm_i915_private * i915,enum intel_platform p)499 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
500 {
501 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
502 const unsigned int pi = __platform_mask_index(info, p);
503 const unsigned int pb = __platform_mask_bit(info, p);
504
505 BUILD_BUG_ON(!__builtin_constant_p(p));
506
507 return info->platform_mask[pi] & BIT(pb);
508 }
509
510 static __always_inline bool
IS_SUBPLATFORM(const struct drm_i915_private * i915,enum intel_platform p,unsigned int s)511 IS_SUBPLATFORM(const struct drm_i915_private *i915,
512 enum intel_platform p, unsigned int s)
513 {
514 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
515 const unsigned int pi = __platform_mask_index(info, p);
516 const unsigned int pb = __platform_mask_bit(info, p);
517 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
518 const u32 mask = info->platform_mask[pi];
519
520 BUILD_BUG_ON(!__builtin_constant_p(p));
521 BUILD_BUG_ON(!__builtin_constant_p(s));
522 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
523
524 /* Shift and test on the MSB position so sign flag can be used. */
525 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
526 }
527
528 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
529 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
530
531 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
532 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
533 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
534 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
535 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
536 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
537 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
538 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
539 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
540 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
541 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
542 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
543 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
544 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
545 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
546 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
547 #define IS_IRONLAKE_M(i915) \
548 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
549 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
550 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
551 #define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
552 INTEL_INFO(i915)->gt == 1)
553 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
554 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
555 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
556 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
557 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
558 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
559 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
560 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
561 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
562 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
563 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
564 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
565 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
566 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
567 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
568 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
569 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
570 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
571 #define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
572 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
573 #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
574 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
575
576 #define IS_METEORLAKE_M(i915) \
577 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
578 #define IS_METEORLAKE_P(i915) \
579 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
580 #define IS_DG2_G10(i915) \
581 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
582 #define IS_DG2_G11(i915) \
583 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
584 #define IS_DG2_G12(i915) \
585 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
586 #define IS_RAPTORLAKE_S(i915) \
587 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
588 #define IS_ALDERLAKE_P_N(i915) \
589 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
590 #define IS_RAPTORLAKE_P(i915) \
591 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
592 #define IS_RAPTORLAKE_U(i915) \
593 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
594 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
595 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
596 #define IS_BROADWELL_ULT(i915) \
597 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
598 #define IS_BROADWELL_ULX(i915) \
599 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
600 #define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
601 INTEL_INFO(i915)->gt == 3)
602 #define IS_HASWELL_ULT(i915) \
603 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
604 #define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
605 INTEL_INFO(i915)->gt == 3)
606 #define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
607 INTEL_INFO(i915)->gt == 1)
608 /* ULX machines are also considered ULT. */
609 #define IS_HASWELL_ULX(i915) \
610 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
611 #define IS_SKYLAKE_ULT(i915) \
612 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
613 #define IS_SKYLAKE_ULX(i915) \
614 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
615 #define IS_KABYLAKE_ULT(i915) \
616 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
617 #define IS_KABYLAKE_ULX(i915) \
618 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
619 #define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
620 INTEL_INFO(i915)->gt == 2)
621 #define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
622 INTEL_INFO(i915)->gt == 3)
623 #define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
624 INTEL_INFO(i915)->gt == 4)
625 #define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
626 INTEL_INFO(i915)->gt == 2)
627 #define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
628 INTEL_INFO(i915)->gt == 3)
629 #define IS_COFFEELAKE_ULT(i915) \
630 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
631 #define IS_COFFEELAKE_ULX(i915) \
632 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
633 #define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
634 INTEL_INFO(i915)->gt == 2)
635 #define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
636 INTEL_INFO(i915)->gt == 3)
637
638 #define IS_COMETLAKE_ULT(i915) \
639 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
640 #define IS_COMETLAKE_ULX(i915) \
641 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
642 #define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
643 INTEL_INFO(i915)->gt == 2)
644
645 #define IS_ICL_WITH_PORT_F(i915) \
646 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
647
648 #define IS_TIGERLAKE_UY(i915) \
649 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
650
651
652
653
654
655
656
657
658 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
659 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
660
661 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
662 (IS_METEORLAKE(__i915) && \
663 IS_DISPLAY_STEP(__i915, since, until))
664
665 #define IS_MTL_MEDIA_STEP(__i915, since, until) \
666 (IS_METEORLAKE(__i915) && \
667 IS_MEDIA_STEP(__i915, since, until))
668
669 /*
670 * DG2 hardware steppings are a bit unusual. The hardware design was forked to
671 * create three variants (G10, G11, and G12) which each have distinct
672 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT
673 * stepping back to "A0" for their first iterations, even though they're more
674 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
675 * functionality and workarounds. However the display stepping does not reset
676 * in the same manner --- a specific stepping like "B0" has a consistent
677 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
678 *
679 * TLDR: All GT workarounds and stepping-specific logic must be applied in
680 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
681 * and stepping-specific logic will be applied with a general DG2-wide stepping
682 * number.
683 */
684 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
685 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
686 IS_GRAPHICS_STEP(__i915, since, until))
687
688 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
689 (IS_DG2(__i915) && \
690 IS_DISPLAY_STEP(__i915, since, until))
691
692 #define IS_PVC_BD_STEP(__i915, since, until) \
693 (IS_PONTEVECCHIO(__i915) && \
694 IS_BASEDIE_STEP(__i915, since, until))
695
696 #define IS_PVC_CT_STEP(__i915, since, until) \
697 (IS_PONTEVECCHIO(__i915) && \
698 IS_GRAPHICS_STEP(__i915, since, until))
699
700 #define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
701 #define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
702 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
703
704 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
705 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
706
707 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
708 unsigned int first__ = (first); \
709 unsigned int count__ = (count); \
710 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
711 })
712
713 #define ENGINE_INSTANCES_MASK(gt, first, count) \
714 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
715
716 #define RCS_MASK(gt) \
717 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
718 #define BCS_MASK(gt) \
719 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
720 #define VDBOX_MASK(gt) \
721 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
722 #define VEBOX_MASK(gt) \
723 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
724 #define CCS_MASK(gt) \
725 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
726
727 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
728
729 /*
730 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
731 * All later gens can run the final buffer from the ppgtt
732 */
733 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
734
735 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
736 #define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
737 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
738 #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
739 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
740 #define HAS_WT(i915) HAS_EDRAM(i915)
741
742 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
743
744 #define HAS_LOGICAL_RING_CONTEXTS(i915) \
745 (INTEL_INFO(i915)->has_logical_ring_contexts)
746 #define HAS_LOGICAL_RING_ELSQ(i915) \
747 (INTEL_INFO(i915)->has_logical_ring_elsq)
748
749 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
750
751 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
752 #define HAS_PPGTT(i915) \
753 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
754 #define HAS_FULL_PPGTT(i915) \
755 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
756
757 #define HAS_PAGE_SIZES(i915, sizes) ({ \
758 GEM_BUG_ON((sizes) == 0); \
759 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
760 })
761
762 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
763 #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
764
765 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
766 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
767
768 /* WaRsDisableCoarsePowerGating:skl,cnl */
769 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \
770 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
771
772 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
773 * rows, which changed the alignment requirements and fence programming.
774 */
775 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
776 !(IS_I915G(i915) || IS_I915GM(i915)))
777
778 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
779 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
780 #define HAS_RC6pp(i915) (false) /* HW was never validated */
781
782 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
783
784 #define HAS_HECI_PXP(i915) \
785 (INTEL_INFO(i915)->has_heci_pxp)
786
787 #define HAS_HECI_GSCFI(i915) \
788 (INTEL_INFO(i915)->has_heci_gscfi)
789
790 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
791
792 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
793 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
794
795 #define HAS_OA_BPC_REPORTING(i915) \
796 (INTEL_INFO(i915)->has_oa_bpc_reporting)
797 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
798 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
799 #define HAS_OAM(i915) \
800 (INTEL_INFO(i915)->has_oam)
801
802 /*
803 * Set this flag, when platform requires 64K GTT page sizes or larger for
804 * device local memory access.
805 */
806 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
807
808 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
809 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
810
811 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
812
813 /*
814 * Platform has the dedicated compression control state for each lmem surfaces
815 * stored in lmem to support the 3D and media compression formats.
816 */
817 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
818
819 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
820
821 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
822
823 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
824
825 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
826
827 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
828
829 /* DPF == dynamic parity feature */
830 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
831 #define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
832 2 : HAS_L3_DPF(i915))
833
834 /* Only valid when HAS_DISPLAY() is true */
835 #define INTEL_DISPLAY_ENABLED(i915) \
836 (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \
837 !(i915)->params.disable_display && \
838 !intel_opregion_headless_sku(i915))
839
840 #define HAS_GUC_DEPRIVILEGE(i915) \
841 (INTEL_INFO(i915)->has_guc_deprivilege)
842
843 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
844
845 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
846
847 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
848 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
849
850 #endif
851