1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.
5 */
6
7 #ifndef __DPU_ENCODER_PHYS_H__
8 #define __DPU_ENCODER_PHYS_H__
9
10 #include <drm/drm_writeback.h>
11 #include <linux/jiffies.h>
12
13 #include "dpu_kms.h"
14 #include "dpu_hw_intf.h"
15 #include "dpu_hw_wb.h"
16 #include "dpu_hw_pingpong.h"
17 #include "dpu_hw_ctl.h"
18 #include "dpu_hw_top.h"
19 #include "dpu_encoder.h"
20 #include "dpu_crtc.h"
21
22 #define DPU_ENCODER_NAME_MAX 16
23
24 /* wait for at most 2 vsync for lowest refresh rate (24hz) */
25 #define KICKOFF_TIMEOUT_MS 84
26 #define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS)
27
28 /**
29 * enum dpu_enc_split_role - Role this physical encoder will play in a
30 * split-panel configuration, where one panel is master, and others slaves.
31 * Masters have extra responsibilities, like managing the VBLANK IRQ.
32 * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master.
33 * @ENC_ROLE_MASTER: This encoder is the master of a split panel config.
34 * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config.
35 */
36 enum dpu_enc_split_role {
37 ENC_ROLE_SOLO,
38 ENC_ROLE_MASTER,
39 ENC_ROLE_SLAVE,
40 };
41
42 /**
43 * enum dpu_enc_enable_state - current enabled state of the physical encoder
44 * @DPU_ENC_DISABLING: Encoder transitioning to disable state
45 * Events bounding transition are encoder type specific
46 * @DPU_ENC_DISABLED: Encoder is disabled
47 * @DPU_ENC_ENABLING: Encoder transitioning to enabled
48 * Events bounding transition are encoder type specific
49 * @DPU_ENC_ENABLED: Encoder is enabled
50 * @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset
51 * to recover from a previous error
52 */
53 enum dpu_enc_enable_state {
54 DPU_ENC_DISABLING,
55 DPU_ENC_DISABLED,
56 DPU_ENC_ENABLING,
57 DPU_ENC_ENABLED,
58 DPU_ENC_ERR_NEEDS_HW_RESET
59 };
60
61 struct dpu_encoder_phys;
62
63 /**
64 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to
65 * the containing virtual encoder.
66 * @prepare_commit: MSM Atomic Call, start of atomic commit sequence
67 * @is_master: Whether this phys_enc is the current master
68 * encoder. Can be switched at enable time. Based
69 * on split_role and current mode (CMD/VID).
70 * @atomic_mode_set: DRM Call. Set a DRM mode.
71 * This likely caches the mode, for use at enable.
72 * @enable: DRM Call. Enable a DRM mode.
73 * @disable: DRM Call. Disable mode.
74 * @atomic_check: DRM Call. Atomic check new DRM state.
75 * @destroy: DRM Call. Destroy and release resources.
76 * @control_vblank_irq Register/Deregister for VBLANK IRQ
77 * @wait_for_commit_done: Wait for hardware to have flushed the
78 * current pending frames to hardware
79 * @wait_for_tx_complete: Wait for hardware to transfer the pixels
80 * to the panel
81 * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use
82 * @prepare_for_kickoff: Do any work necessary prior to a kickoff
83 * For CMD encoder, may wait for previous tx done
84 * @handle_post_kickoff: Do any work necessary post-kickoff work
85 * @trigger_start: Process start event on physical encoder
86 * @needs_single_flush: Whether encoder slaves need to be flushed
87 * @irq_control: Handler to enable/disable all the encoder IRQs
88 * @prepare_idle_pc: phys encoder can update the vsync_enable status
89 * on idle power collapse prepare
90 * @restore: Restore all the encoder configs.
91 * @get_line_count: Obtain current vertical line count
92 */
93
94 struct dpu_encoder_phys_ops {
95 void (*prepare_commit)(struct dpu_encoder_phys *encoder);
96 bool (*is_master)(struct dpu_encoder_phys *encoder);
97 void (*atomic_mode_set)(struct dpu_encoder_phys *encoder,
98 struct drm_crtc_state *crtc_state,
99 struct drm_connector_state *conn_state);
100 void (*enable)(struct dpu_encoder_phys *encoder);
101 void (*disable)(struct dpu_encoder_phys *encoder);
102 int (*atomic_check)(struct dpu_encoder_phys *encoder,
103 struct drm_crtc_state *crtc_state,
104 struct drm_connector_state *conn_state);
105 void (*destroy)(struct dpu_encoder_phys *encoder);
106 int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);
107 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);
108 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);
109 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc);
110 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc);
111 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc);
112 void (*trigger_start)(struct dpu_encoder_phys *phys_enc);
113 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc);
114 void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
115 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
116 void (*restore)(struct dpu_encoder_phys *phys);
117 int (*get_line_count)(struct dpu_encoder_phys *phys);
118 int (*get_frame_count)(struct dpu_encoder_phys *phys);
119 void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc,
120 struct drm_writeback_job *job);
121 void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc,
122 struct drm_writeback_job *job);
123 bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc);
124 };
125
126 /**
127 * enum dpu_intr_idx - dpu encoder interrupt index
128 * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel
129 * @INTR_IDX_PINGPONG: Pingpong done interrupt for cmd mode panel
130 * @INTR_IDX_UNDERRUN: Underrun interrupt for video and cmd mode panel
131 * @INTR_IDX_RDPTR: Readpointer done interrupt for cmd mode panel
132 * @INTR_IDX_WB_DONE: Writeback done interrupt for virtual connector
133 */
134 enum dpu_intr_idx {
135 INTR_IDX_VSYNC,
136 INTR_IDX_PINGPONG,
137 INTR_IDX_UNDERRUN,
138 INTR_IDX_CTL_START,
139 INTR_IDX_RDPTR,
140 INTR_IDX_WB_DONE,
141 INTR_IDX_MAX,
142 };
143
144 /**
145 * struct dpu_encoder_phys - physical encoder that drives a single INTF block
146 * tied to a specific panel / sub-panel. Abstract type, sub-classed by
147 * phys_vid or phys_cmd for video mode or command mode encs respectively.
148 * @parent: Pointer to the containing virtual encoder
149 * @ops: Operations exposed to the virtual encoder
150 * @parent_ops: Callbacks exposed by the parent to the phys_enc
151 * @hw_mdptop: Hardware interface to the top registers
152 * @hw_ctl: Hardware interface to the ctl registers
153 * @hw_pp: Hardware interface to the ping pong registers
154 * @hw_intf: Hardware interface to the intf registers
155 * @hw_wb: Hardware interface to the wb registers
156 * @dpu_kms: Pointer to the dpu_kms top level
157 * @cached_mode: DRM mode cached at mode_set time, acted on in enable
158 * @enabled: Whether the encoder has enabled and running a mode
159 * @split_role: Role to play in a split-panel configuration
160 * @intf_mode: Interface mode
161 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
162 * @enable_state: Enable state tracking
163 * @vblank_refcount: Reference count of vblank request
164 * @vsync_cnt: Vsync count for the physical encoder
165 * @underrun_cnt: Underrun count for the physical encoder
166 * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs
167 * vs. the number of done/vblank irqs. Should hover
168 * between 0-2 Incremented when a new kickoff is
169 * scheduled. Decremented in irq handler
170 * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start
171 * pending.
172 * @pending_kickoff_wq: Wait queue for blocking until kickoff completes
173 * @irq: IRQ indices
174 * @has_intf_te: Interface TE configuration support
175 */
176 struct dpu_encoder_phys {
177 struct drm_encoder *parent;
178 struct dpu_encoder_phys_ops ops;
179 struct dpu_hw_mdp *hw_mdptop;
180 struct dpu_hw_ctl *hw_ctl;
181 struct dpu_hw_pingpong *hw_pp;
182 struct dpu_hw_intf *hw_intf;
183 struct dpu_hw_wb *hw_wb;
184 struct dpu_kms *dpu_kms;
185 struct drm_display_mode cached_mode;
186 enum dpu_enc_split_role split_role;
187 enum dpu_intf_mode intf_mode;
188 spinlock_t *enc_spinlock;
189 enum dpu_enc_enable_state enable_state;
190 atomic_t vblank_refcount;
191 atomic_t vsync_cnt;
192 atomic_t underrun_cnt;
193 atomic_t pending_ctlstart_cnt;
194 atomic_t pending_kickoff_cnt;
195 wait_queue_head_t pending_kickoff_wq;
196 int irq[INTR_IDX_MAX];
197 bool has_intf_te;
198 };
199
dpu_encoder_phys_inc_pending(struct dpu_encoder_phys * phys)200 static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys)
201 {
202 atomic_inc_return(&phys->pending_ctlstart_cnt);
203 return atomic_inc_return(&phys->pending_kickoff_cnt);
204 }
205
206 /**
207 * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command
208 * mode specific operations
209 * @base: Baseclass physical encoder structure
210 * @wbirq_refcount: Reference count of writeback interrupt
211 * @wb_done_timeout_cnt: number of wb done irq timeout errors
212 * @wb_cfg: writeback block config to store fb related details
213 * @wb_conn: backpointer to writeback connector
214 * @wb_job: backpointer to current writeback job
215 * @dest: dpu buffer layout for current writeback output buffer
216 */
217 struct dpu_encoder_phys_wb {
218 struct dpu_encoder_phys base;
219 atomic_t wbirq_refcount;
220 int wb_done_timeout_cnt;
221 struct dpu_hw_wb_cfg wb_cfg;
222 struct drm_writeback_connector *wb_conn;
223 struct drm_writeback_job *wb_job;
224 struct dpu_hw_fmt_layout dest;
225 };
226
227 /**
228 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command
229 * mode specific operations
230 * @base: Baseclass physical encoder structure
231 * @intf_idx: Intf Block index used by this phys encoder
232 * @stream_sel: Stream selection for multi-stream interfaces
233 * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt
234 * after ctl_start instead of before next frame kickoff
235 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors
236 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK
237 * @pending_vblank_wq: Wait queue for blocking until VBLANK received
238 */
239 struct dpu_encoder_phys_cmd {
240 struct dpu_encoder_phys base;
241 int stream_sel;
242 bool serialize_wait4pp;
243 int pp_timeout_report_cnt;
244 atomic_t pending_vblank_cnt;
245 wait_queue_head_t pending_vblank_wq;
246 };
247
248 /**
249 * struct dpu_enc_phys_init_params - initialization parameters for phys encs
250 * @dpu_kms: Pointer to the dpu_kms top level
251 * @parent: Pointer to the containing virtual encoder
252 * @parent_ops: Callbacks exposed by the parent to the phys_enc
253 * @split_role: Role to play in a split-panel configuration
254 * @hw_intf: Hardware interface to the intf registers
255 * @hw_wb: Hardware interface to the wb registers
256 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
257 */
258 struct dpu_enc_phys_init_params {
259 struct dpu_kms *dpu_kms;
260 struct drm_encoder *parent;
261 enum dpu_enc_split_role split_role;
262 struct dpu_hw_intf *hw_intf;
263 struct dpu_hw_wb *hw_wb;
264 spinlock_t *enc_spinlock;
265 };
266
267 /**
268 * dpu_encoder_wait_info - container for passing arguments to irq wait functions
269 * @wq: wait queue structure
270 * @atomic_cnt: wait until atomic_cnt equals zero
271 * @timeout_ms: timeout value in milliseconds
272 */
273 struct dpu_encoder_wait_info {
274 wait_queue_head_t *wq;
275 atomic_t *atomic_cnt;
276 s64 timeout_ms;
277 };
278
279 /**
280 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder
281 * @p: Pointer to init params structure
282 * Return: Error code or newly allocated encoder
283 */
284 struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
285 struct dpu_enc_phys_init_params *p);
286
287 /**
288 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder
289 * @p: Pointer to init params structure
290 * Return: Error code or newly allocated encoder
291 */
292 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
293 struct dpu_enc_phys_init_params *p);
294
295 /**
296 * dpu_encoder_phys_wb_init - initialize writeback encoder
297 * @init: Pointer to init info structure with initialization params
298 */
299 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(
300 struct dpu_enc_phys_init_params *p);
301
302 /**
303 * dpu_encoder_helper_trigger_start - control start helper function
304 * This helper function may be optionally specified by physical
305 * encoders if they require ctl_start triggering.
306 * @phys_enc: Pointer to physical encoder structure
307 */
308 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc);
309
dpu_encoder_helper_get_3d_blend_mode(struct dpu_encoder_phys * phys_enc)310 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
311 struct dpu_encoder_phys *phys_enc)
312 {
313 struct dpu_crtc_state *dpu_cstate;
314
315 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
316 return BLEND_3D_NONE;
317
318 dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
319
320 /* Use merge_3d unless DSC MERGE topology is used */
321 if (phys_enc->split_role == ENC_ROLE_SOLO &&
322 dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
323 !dpu_encoder_use_dsc_merge(phys_enc->parent))
324 return BLEND_3D_H_ROW_INT;
325
326 return BLEND_3D_NONE;
327 }
328
329 /**
330 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
331 * This helper function is used by physical encoder to get DSC blocks mask
332 * used for this encoder.
333 * @phys_enc: Pointer to physical encoder structure
334 */
335 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
336
337 /**
338 * dpu_encoder_helper_split_config - split display configuration helper function
339 * This helper function may be used by physical encoders to configure
340 * the split display related registers.
341 * @phys_enc: Pointer to physical encoder structure
342 * @interface: enum dpu_intf setting
343 */
344 void dpu_encoder_helper_split_config(
345 struct dpu_encoder_phys *phys_enc,
346 enum dpu_intf interface);
347
348 /**
349 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has
350 * timed out, including reporting frame error event to crtc and debug dump
351 * @phys_enc: Pointer to physical encoder structure
352 * @intr_idx: Failing interrupt index
353 */
354 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc,
355 enum dpu_intr_idx intr_idx);
356
357 /**
358 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq.
359 * note: will call dpu_encoder_helper_wait_for_irq on timeout
360 * @phys_enc: Pointer to physical encoder structure
361 * @irq: IRQ index
362 * @func: IRQ callback to be called in case of timeout
363 * @wait_info: wait info struct
364 * @Return: 0 or -ERROR
365 */
366 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc,
367 int irq,
368 void (*func)(void *arg),
369 struct dpu_encoder_wait_info *wait_info);
370
371 /**
372 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline
373 * @phys_enc: Pointer to physical encoder structure
374 */
375 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc);
376
377 /**
378 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception
379 * @drm_enc: Pointer to drm encoder structure
380 * @phys_enc: Pointer to physical encoder
381 * Note: This is called from IRQ handler context.
382 */
383 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
384 struct dpu_encoder_phys *phy_enc);
385
386 /** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception
387 * @drm_enc: Pointer to drm encoder structure
388 * @phys_enc: Pointer to physical encoder
389 * Note: This is called from IRQ handler context.
390 */
391 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc,
392 struct dpu_encoder_phys *phy_enc);
393
394 /** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame
395 * @drm_enc: Pointer to drm encoder structure
396 * @phys_enc: Pointer to physical encoder
397 * @event: Event to process
398 */
399 void dpu_encoder_frame_done_callback(
400 struct drm_encoder *drm_enc,
401 struct dpu_encoder_phys *ready_phys, u32 event);
402
403 void dpu_encoder_phys_init(struct dpu_encoder_phys *phys,
404 struct dpu_enc_phys_init_params *p);
405
406 #endif /* __dpu_encoder_phys_H__ */
407