xref: /openbmc/linux/include/linux/firmware/imx/svc/pm.h (revision 0a914a49)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
4  * Copyright 2017-2018 NXP
5  *
6  * Header file containing the public API for the System Controller (SC)
7  * Power Management (PM) function. This includes functions for power state
8  * control, clock control, reset control, and wake-up event control.
9  *
10  * PM_SVC (SVC) Power Management Service
11  *
12  * Module for the Power Management (PM) service.
13  */
14 
15 #ifndef _SC_PM_API_H
16 #define _SC_PM_API_H
17 
18 #include <linux/firmware/imx/sci.h>
19 
20 /*
21  * This type is used to indicate RPC PM function calls.
22  */
23 enum imx_sc_pm_func {
24 	IMX_SC_PM_FUNC_UNKNOWN = 0,
25 	IMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19,
26 	IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1,
27 	IMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2,
28 	IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3,
29 	IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4,
30 	IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16,
31 	IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17,
32 	IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18,
33 	IMX_SC_PM_FUNC_SET_CLOCK_RATE = 5,
34 	IMX_SC_PM_FUNC_GET_CLOCK_RATE = 6,
35 	IMX_SC_PM_FUNC_CLOCK_ENABLE = 7,
36 	IMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14,
37 	IMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15,
38 	IMX_SC_PM_FUNC_RESET = 13,
39 	IMX_SC_PM_FUNC_RESET_REASON = 10,
40 	IMX_SC_PM_FUNC_BOOT = 8,
41 	IMX_SC_PM_FUNC_REBOOT = 9,
42 	IMX_SC_PM_FUNC_REBOOT_PARTITION = 12,
43 	IMX_SC_PM_FUNC_CPU_START = 11,
44 };
45 
46 /*
47  * Defines for ALL parameters
48  */
49 #define IMX_SC_PM_CLK_ALL		UINT8_MAX	/* All clocks */
50 
51 /*
52  * Defines for SC PM Power Mode
53  */
54 #define IMX_SC_PM_PW_MODE_OFF	0	/* Power off */
55 #define IMX_SC_PM_PW_MODE_STBY	1	/* Power in standby */
56 #define IMX_SC_PM_PW_MODE_LP	2	/* Power in low-power */
57 #define IMX_SC_PM_PW_MODE_ON	3	/* Power on */
58 
59 /*
60  * Defines for SC PM CLK
61  */
62 #define IMX_SC_PM_CLK_SLV_BUS	0	/* Slave bus clock */
63 #define IMX_SC_PM_CLK_MST_BUS	1	/* Master bus clock */
64 #define IMX_SC_PM_CLK_PER	2	/* Peripheral clock */
65 #define IMX_SC_PM_CLK_PHY	3	/* Phy clock */
66 #define IMX_SC_PM_CLK_MISC	4	/* Misc clock */
67 #define IMX_SC_PM_CLK_MISC0	0	/* Misc 0 clock */
68 #define IMX_SC_PM_CLK_MISC1	1	/* Misc 1 clock */
69 #define IMX_SC_PM_CLK_MISC2	2	/* Misc 2 clock */
70 #define IMX_SC_PM_CLK_MISC3	3	/* Misc 3 clock */
71 #define IMX_SC_PM_CLK_MISC4	4	/* Misc 4 clock */
72 #define IMX_SC_PM_CLK_CPU	2	/* CPU clock */
73 #define IMX_SC_PM_CLK_PLL	4	/* PLL */
74 #define IMX_SC_PM_CLK_BYPASS	4	/* Bypass clock */
75 
76 /*
77  * Defines for SC PM CLK Parent
78  */
79 #define IMX_SC_PM_PARENT_XTAL	0	/* Parent is XTAL. */
80 #define IMX_SC_PM_PARENT_PLL0	1	/* Parent is PLL0 */
81 #define IMX_SC_PM_PARENT_PLL1	2	/* Parent is PLL1 or PLL0/2 */
82 #define IMX_SC_PM_PARENT_PLL2	3	/* Parent in PLL2 or PLL0/4 */
83 #define IMX_SC_PM_PARENT_BYPS	4	/* Parent is a bypass clock. */
84 
85 #endif /* _SC_PM_API_H */
86