xref: /openbmc/linux/arch/m68k/include/asm/MC68328.h (revision b2441318)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
4  *
5  * Copyright (C) 1999  Vladimir Gurevich <vgurevic@cisco.com>
6  *                     Bear & Hare Software, Inc.
7  *
8  * Based on include/asm-m68knommu/MC68332.h
9  * Copyright (C) 1998  Kenneth Albanowski <kjahds@kjahds.com>,
10  *
11  */
12 #include <linux/compiler.h>
13 
14 #ifndef _MC68328_H_
15 #define _MC68328_H_
16 
17 #define BYTE_REF(addr) (*((volatile unsigned char*)addr))
18 #define WORD_REF(addr) (*((volatile unsigned short*)addr))
19 #define LONG_REF(addr) (*((volatile unsigned long*)addr))
20 
21 #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK)
22 #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT)
23 
24 /**********
25  *
26  * 0xFFFFF0xx -- System Control
27  *
28  **********/
29 
30 /*
31  * System Control Register (SCR)
32  */
33 #define SCR_ADDR	0xfffff000
34 #define SCR		BYTE_REF(SCR_ADDR)
35 
36 #define SCR_WDTH8	0x01	/* 8-Bit Width Select */
37 #define SCR_DMAP	0x04	/* Double Map */
38 #define SCR_SO		0x08	/* Supervisor Only */
39 #define SCR_BETEN	0x10	/* Bus-Error Time-Out Enable */
40 #define SCR_PRV		0x20	/* Privilege Violation */
41 #define SCR_WPV		0x40	/* Write Protect Violation */
42 #define SCR_BETO	0x80	/* Bus-Error TimeOut */
43 
44 /*
45  * Mask Revision Register
46  */
47 #define MRR_ADDR 0xfffff004
48 #define MRR      LONG_REF(MRR_ADDR)
49 
50 /**********
51  *
52  * 0xFFFFF1xx -- Chip-Select logic
53  *
54  **********/
55 
56 /**********
57  *
58  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
59  *
60  **********/
61 
62 /*
63  * Group Base Address Registers
64  */
65 #define GRPBASEA_ADDR	0xfffff100
66 #define GRPBASEB_ADDR	0xfffff102
67 #define GRPBASEC_ADDR	0xfffff104
68 #define GRPBASED_ADDR	0xfffff106
69 
70 #define GRPBASEA	WORD_REF(GRPBASEA_ADDR)
71 #define GRPBASEB	WORD_REF(GRPBASEB_ADDR)
72 #define GRPBASEC	WORD_REF(GRPBASEC_ADDR)
73 #define GRPBASED	WORD_REF(GRPBASED_ADDR)
74 
75 #define GRPBASE_V	  0x0001	/* Valid */
76 #define GRPBASE_GBA_MASK  0xfff0	/* Group Base Address (bits 31-20) */
77 
78 /*
79  * Group Base Address Mask Registers
80  */
81 #define GRPMASKA_ADDR	0xfffff108
82 #define GRPMASKB_ADDR	0xfffff10a
83 #define GRPMASKC_ADDR	0xfffff10c
84 #define GRPMASKD_ADDR	0xfffff10e
85 
86 #define GRPMASKA	WORD_REF(GRPMASKA_ADDR)
87 #define GRPMASKB	WORD_REF(GRPMASKB_ADDR)
88 #define GRPMASKC	WORD_REF(GRPMASKC_ADDR)
89 #define GRPMASKD	WORD_REF(GRPMASKD_ADDR)
90 
91 #define GRMMASK_GMA_MASK 0xfffff0	/* Group Base Mask (bits 31-20) */
92 
93 /*
94  * Chip-Select Option Registers (group A)
95  */
96 #define CSA0_ADDR	0xfffff110
97 #define CSA1_ADDR	0xfffff114
98 #define CSA2_ADDR	0xfffff118
99 #define CSA3_ADDR	0xfffff11c
100 
101 #define CSA0		LONG_REF(CSA0_ADDR)
102 #define CSA1		LONG_REF(CSA1_ADDR)
103 #define CSA2		LONG_REF(CSA2_ADDR)
104 #define CSA3		LONG_REF(CSA3_ADDR)
105 
106 #define CSA_WAIT_MASK	0x00000007	/* Wait State Selection */
107 #define CSA_WAIT_SHIFT	0
108 #define CSA_RO		0x00000008	/* Read-Only */
109 #define CSA_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
110 #define CSA_AM_SHIFT	8
111 #define CSA_BUSW	0x00010000	/* Bus Width Select */
112 #define CSA_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
113 #define CSA_AC_SHIFT	24
114 
115 /*
116  * Chip-Select Option Registers (group B)
117  */
118 #define CSB0_ADDR	0xfffff120
119 #define CSB1_ADDR	0xfffff124
120 #define CSB2_ADDR	0xfffff128
121 #define CSB3_ADDR	0xfffff12c
122 
123 #define CSB0		LONG_REF(CSB0_ADDR)
124 #define CSB1		LONG_REF(CSB1_ADDR)
125 #define CSB2		LONG_REF(CSB2_ADDR)
126 #define CSB3		LONG_REF(CSB3_ADDR)
127 
128 #define CSB_WAIT_MASK	0x00000007	/* Wait State Selection */
129 #define CSB_WAIT_SHIFT	0
130 #define CSB_RO		0x00000008	/* Read-Only */
131 #define CSB_AM_MASK	0x0000ff00	/* Address Mask (bits 23-16) */
132 #define CSB_AM_SHIFT	8
133 #define CSB_BUSW	0x00010000	/* Bus Width Select */
134 #define CSB_AC_MASK	0xff000000	/* Address Compare (bits 23-16) */
135 #define CSB_AC_SHIFT	24
136 
137 /*
138  * Chip-Select Option Registers (group C)
139  */
140 #define CSC0_ADDR	0xfffff130
141 #define CSC1_ADDR	0xfffff134
142 #define CSC2_ADDR	0xfffff138
143 #define CSC3_ADDR	0xfffff13c
144 
145 #define CSC0		LONG_REF(CSC0_ADDR)
146 #define CSC1		LONG_REF(CSC1_ADDR)
147 #define CSC2		LONG_REF(CSC2_ADDR)
148 #define CSC3		LONG_REF(CSC3_ADDR)
149 
150 #define CSC_WAIT_MASK	0x00000007	/* Wait State Selection */
151 #define CSC_WAIT_SHIFT	0
152 #define CSC_RO		0x00000008	/* Read-Only */
153 #define CSC_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
154 #define CSC_AM_SHIFT	4
155 #define CSC_BUSW	0x00010000	/* Bus Width Select */
156 #define CSC_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
157 #define CSC_AC_SHIFT	20
158 
159 /*
160  * Chip-Select Option Registers (group D)
161  */
162 #define CSD0_ADDR	0xfffff140
163 #define CSD1_ADDR	0xfffff144
164 #define CSD2_ADDR	0xfffff148
165 #define CSD3_ADDR	0xfffff14c
166 
167 #define CSD0		LONG_REF(CSD0_ADDR)
168 #define CSD1		LONG_REF(CSD1_ADDR)
169 #define CSD2		LONG_REF(CSD2_ADDR)
170 #define CSD3		LONG_REF(CSD3_ADDR)
171 
172 #define CSD_WAIT_MASK	0x00000007	/* Wait State Selection */
173 #define CSD_WAIT_SHIFT	0
174 #define CSD_RO		0x00000008	/* Read-Only */
175 #define CSD_AM_MASK	0x0000fff0	/* Address Mask (bits 23-12) */
176 #define CSD_AM_SHIFT	4
177 #define CSD_BUSW	0x00010000	/* Bus Width Select */
178 #define CSD_AC_MASK	0xfff00000	/* Address Compare (bits 23-12) */
179 #define CSD_AC_SHIFT	20
180 
181 /**********
182  *
183  * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control
184  *
185  **********/
186 
187 /*
188  * PLL Control Register
189  */
190 #define PLLCR_ADDR	0xfffff200
191 #define PLLCR		WORD_REF(PLLCR_ADDR)
192 
193 #define PLLCR_DISPLL	       0x0008	/* Disable PLL */
194 #define PLLCR_CLKEN	       0x0010	/* Clock (CLKO pin) enable */
195 #define PLLCR_SYSCLK_SEL_MASK  0x0700	/* System Clock Selection */
196 #define PLLCR_SYSCLK_SEL_SHIFT 8
197 #define PLLCR_PIXCLK_SEL_MASK  0x3800	/* LCD Clock Selection */
198 #define PLLCR_PIXCLK_SEL_SHIFT 11
199 
200 /* 'EZ328-compatible definitions */
201 #define PLLCR_LCDCLK_SEL_MASK	PLLCR_PIXCLK_SEL_MASK
202 #define PLLCR_LCDCLK_SEL_SHIFT	PLLCR_PIXCLK_SEL_SHIFT
203 
204 /*
205  * PLL Frequency Select Register
206  */
207 #define PLLFSR_ADDR	0xfffff202
208 #define PLLFSR		WORD_REF(PLLFSR_ADDR)
209 
210 #define PLLFSR_PC_MASK	0x00ff		/* P Count */
211 #define PLLFSR_PC_SHIFT 0
212 #define PLLFSR_QC_MASK	0x0f00		/* Q Count */
213 #define PLLFSR_QC_SHIFT 8
214 #define PLLFSR_PROT	0x4000		/* Protect P & Q */
215 #define PLLFSR_CLK32	0x8000		/* Clock 32 (kHz) */
216 
217 /*
218  * Power Control Register
219  */
220 #define PCTRL_ADDR	0xfffff207
221 #define PCTRL		BYTE_REF(PCTRL_ADDR)
222 
223 #define PCTRL_WIDTH_MASK	0x1f	/* CPU Clock bursts width */
224 #define PCTRL_WIDTH_SHIFT	0
225 #define PCTRL_STOP		0x40	/* Enter power-save mode immediately */
226 #define PCTRL_PCEN		0x80	/* Power Control Enable */
227 
228 /**********
229  *
230  * 0xFFFFF3xx -- Interrupt Controller
231  *
232  **********/
233 
234 /*
235  * Interrupt Vector Register
236  */
237 #define IVR_ADDR	0xfffff300
238 #define IVR		BYTE_REF(IVR_ADDR)
239 
240 #define IVR_VECTOR_MASK 0xF8
241 
242 /*
243  * Interrupt control Register
244  */
245 #define ICR_ADRR	0xfffff302
246 #define ICR		WORD_REF(ICR_ADDR)
247 
248 #define ICR_ET6		0x0100	/* Edge Trigger Select for IRQ6 */
249 #define ICR_ET3		0x0200	/* Edge Trigger Select for IRQ3 */
250 #define ICR_ET2		0x0400	/* Edge Trigger Select for IRQ2 */
251 #define ICR_ET1		0x0800	/* Edge Trigger Select for IRQ1 */
252 #define ICR_POL6	0x1000	/* Polarity Control for IRQ6 */
253 #define ICR_POL3	0x2000	/* Polarity Control for IRQ3 */
254 #define ICR_POL2	0x4000	/* Polarity Control for IRQ2 */
255 #define ICR_POL1	0x8000	/* Polarity Control for IRQ1 */
256 
257 /*
258  * Interrupt Mask Register
259  */
260 #define IMR_ADDR	0xfffff304
261 #define IMR		LONG_REF(IMR_ADDR)
262 
263 /*
264  * Define the names for bit positions first. This is useful for
265  * request_irq
266  */
267 #define SPIM_IRQ_NUM	0	/* SPI Master interrupt */
268 #define	TMR2_IRQ_NUM	1	/* Timer 2 interrupt */
269 #define UART_IRQ_NUM	2	/* UART interrupt */
270 #define	WDT_IRQ_NUM	3	/* Watchdog Timer interrupt */
271 #define RTC_IRQ_NUM	4	/* RTC interrupt */
272 #define	KB_IRQ_NUM	6	/* Keyboard Interrupt */
273 #define PWM_IRQ_NUM	7	/* Pulse-Width Modulator int. */
274 #define	INT0_IRQ_NUM	8	/* External INT0 */
275 #define	INT1_IRQ_NUM	9	/* External INT1 */
276 #define	INT2_IRQ_NUM	10	/* External INT2 */
277 #define	INT3_IRQ_NUM	11	/* External INT3 */
278 #define	INT4_IRQ_NUM	12	/* External INT4 */
279 #define	INT5_IRQ_NUM	13	/* External INT5 */
280 #define	INT6_IRQ_NUM	14	/* External INT6 */
281 #define	INT7_IRQ_NUM	15	/* External INT7 */
282 #define IRQ1_IRQ_NUM	16	/* IRQ1 */
283 #define IRQ2_IRQ_NUM	17	/* IRQ2 */
284 #define IRQ3_IRQ_NUM	18	/* IRQ3 */
285 #define IRQ6_IRQ_NUM	19	/* IRQ6 */
286 #define PEN_IRQ_NUM	20	/* Pen Interrupt */
287 #define SPIS_IRQ_NUM	21	/* SPI Slave Interrupt */
288 #define TMR1_IRQ_NUM	22	/* Timer 1 interrupt */
289 #define IRQ7_IRQ_NUM	23	/* IRQ7 */
290 
291 /* '328-compatible definitions */
292 #define SPI_IRQ_NUM	SPIM_IRQ_NUM
293 #define TMR_IRQ_NUM	TMR1_IRQ_NUM
294 
295 /*
296  * Here go the bitmasks themselves
297  */
298 #define IMR_MSPIM 	(1 << SPIM_IRQ_NUM)	/* Mask SPI Master interrupt */
299 #define	IMR_MTMR2	(1 << TMR2_IRQ_NUM)	/* Mask Timer 2 interrupt */
300 #define IMR_MUART	(1 << UART_IRQ_NUM)	/* Mask UART interrupt */
301 #define	IMR_MWDT	(1 << WDT_IRQ_NUM)	/* Mask Watchdog Timer interrupt */
302 #define IMR_MRTC	(1 << RTC_IRQ_NUM)	/* Mask RTC interrupt */
303 #define	IMR_MKB		(1 << KB_IRQ_NUM)	/* Mask Keyboard Interrupt */
304 #define IMR_MPWM	(1 << PWM_IRQ_NUM)	/* Mask Pulse-Width Modulator int. */
305 #define	IMR_MINT0	(1 << INT0_IRQ_NUM)	/* Mask External INT0 */
306 #define	IMR_MINT1	(1 << INT1_IRQ_NUM)	/* Mask External INT1 */
307 #define	IMR_MINT2	(1 << INT2_IRQ_NUM)	/* Mask External INT2 */
308 #define	IMR_MINT3	(1 << INT3_IRQ_NUM)	/* Mask External INT3 */
309 #define	IMR_MINT4	(1 << INT4_IRQ_NUM)	/* Mask External INT4 */
310 #define	IMR_MINT5	(1 << INT5_IRQ_NUM)	/* Mask External INT5 */
311 #define	IMR_MINT6	(1 << INT6_IRQ_NUM)	/* Mask External INT6 */
312 #define	IMR_MINT7	(1 << INT7_IRQ_NUM)	/* Mask External INT7 */
313 #define IMR_MIRQ1	(1 << IRQ1_IRQ_NUM)	/* Mask IRQ1 */
314 #define IMR_MIRQ2	(1 << IRQ2_IRQ_NUM)	/* Mask IRQ2 */
315 #define IMR_MIRQ3	(1 << IRQ3_IRQ_NUM)	/* Mask IRQ3 */
316 #define IMR_MIRQ6	(1 << IRQ6_IRQ_NUM)	/* Mask IRQ6 */
317 #define IMR_MPEN	(1 << PEN_IRQ_NUM)	/* Mask Pen Interrupt */
318 #define IMR_MSPIS	(1 << SPIS_IRQ_NUM)	/* Mask SPI Slave Interrupt */
319 #define IMR_MTMR1	(1 << TMR1_IRQ_NUM)	/* Mask Timer 1 interrupt */
320 #define IMR_MIRQ7	(1 << IRQ7_IRQ_NUM)	/* Mask IRQ7 */
321 
322 /* 'EZ328-compatible definitions */
323 #define IMR_MSPI	IMR_MSPIM
324 #define IMR_MTMR	IMR_MTMR1
325 
326 /*
327  * Interrupt Wake-Up Enable Register
328  */
329 #define IWR_ADDR	0xfffff308
330 #define IWR		LONG_REF(IWR_ADDR)
331 
332 #define IWR_SPIM 	(1 << SPIM_IRQ_NUM)	/* SPI Master interrupt */
333 #define	IWR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
334 #define IWR_UART	(1 << UART_IRQ_NUM)	/* UART interrupt */
335 #define	IWR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
336 #define IWR_RTC		(1 << RTC_IRQ_NUM)	/* RTC interrupt */
337 #define	IWR_KB		(1 << KB_IRQ_NUM)	/* Keyboard Interrupt */
338 #define IWR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
339 #define	IWR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
340 #define	IWR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
341 #define	IWR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
342 #define	IWR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
343 #define	IWR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
344 #define	IWR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
345 #define	IWR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
346 #define	IWR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
347 #define IWR_IRQ1	(1 << IRQ1_IRQ_NUM)	/* IRQ1 */
348 #define IWR_IRQ2	(1 << IRQ2_IRQ_NUM)	/* IRQ2 */
349 #define IWR_IRQ3	(1 << IRQ3_IRQ_NUM)	/* IRQ3 */
350 #define IWR_IRQ6	(1 << IRQ6_IRQ_NUM)	/* IRQ6 */
351 #define IWR_PEN		(1 << PEN_IRQ_NUM)	/* Pen Interrupt */
352 #define IWR_SPIS	(1 << SPIS_IRQ_NUM)	/* SPI Slave Interrupt */
353 #define IWR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
354 #define IWR_IRQ7	(1 << IRQ7_IRQ_NUM)	/* IRQ7 */
355 
356 /*
357  * Interrupt Status Register
358  */
359 #define ISR_ADDR	0xfffff30c
360 #define ISR		LONG_REF(ISR_ADDR)
361 
362 #define ISR_SPIM 	(1 << SPIM_IRQ_NUM)	/* SPI Master interrupt */
363 #define	ISR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
364 #define ISR_UART	(1 << UART_IRQ_NUM)	/* UART interrupt */
365 #define	ISR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
366 #define ISR_RTC		(1 << RTC_IRQ_NUM)	/* RTC interrupt */
367 #define	ISR_KB		(1 << KB_IRQ_NUM)	/* Keyboard Interrupt */
368 #define ISR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
369 #define	ISR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
370 #define	ISR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
371 #define	ISR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
372 #define	ISR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
373 #define	ISR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
374 #define	ISR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
375 #define	ISR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
376 #define	ISR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
377 #define ISR_IRQ1	(1 << IRQ1_IRQ_NUM)	/* IRQ1 */
378 #define ISR_IRQ2	(1 << IRQ2_IRQ_NUM)	/* IRQ2 */
379 #define ISR_IRQ3	(1 << IRQ3_IRQ_NUM)	/* IRQ3 */
380 #define ISR_IRQ6	(1 << IRQ6_IRQ_NUM)	/* IRQ6 */
381 #define ISR_PEN		(1 << PEN_IRQ_NUM)	/* Pen Interrupt */
382 #define ISR_SPIS	(1 << SPIS_IRQ_NUM)	/* SPI Slave Interrupt */
383 #define ISR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
384 #define ISR_IRQ7	(1 << IRQ7_IRQ_NUM)	/* IRQ7 */
385 
386 /* 'EZ328-compatible definitions */
387 #define ISR_SPI	ISR_SPIM
388 #define ISR_TMR	ISR_TMR1
389 
390 /*
391  * Interrupt Pending Register
392  */
393 #define IPR_ADDR	0xfffff310
394 #define IPR		LONG_REF(IPR_ADDR)
395 
396 #define IPR_SPIM 	(1 << SPIM_IRQ_NUM)	/* SPI Master interrupt */
397 #define	IPR_TMR2	(1 << TMR2_IRQ_NUM)	/* Timer 2 interrupt */
398 #define IPR_UART	(1 << UART_IRQ_NUM)	/* UART interrupt */
399 #define	IPR_WDT		(1 << WDT_IRQ_NUM)	/* Watchdog Timer interrupt */
400 #define IPR_RTC		(1 << RTC_IRQ_NUM)	/* RTC interrupt */
401 #define	IPR_KB		(1 << KB_IRQ_NUM)	/* Keyboard Interrupt */
402 #define IPR_PWM		(1 << PWM_IRQ_NUM)	/* Pulse-Width Modulator int. */
403 #define	IPR_INT0	(1 << INT0_IRQ_NUM)	/* External INT0 */
404 #define	IPR_INT1	(1 << INT1_IRQ_NUM)	/* External INT1 */
405 #define	IPR_INT2	(1 << INT2_IRQ_NUM)	/* External INT2 */
406 #define	IPR_INT3	(1 << INT3_IRQ_NUM)	/* External INT3 */
407 #define	IPR_INT4	(1 << INT4_IRQ_NUM)	/* External INT4 */
408 #define	IPR_INT5	(1 << INT5_IRQ_NUM)	/* External INT5 */
409 #define	IPR_INT6	(1 << INT6_IRQ_NUM)	/* External INT6 */
410 #define	IPR_INT7	(1 << INT7_IRQ_NUM)	/* External INT7 */
411 #define IPR_IRQ1	(1 << IRQ1_IRQ_NUM)	/* IRQ1 */
412 #define IPR_IRQ2	(1 << IRQ2_IRQ_NUM)	/* IRQ2 */
413 #define IPR_IRQ3	(1 << IRQ3_IRQ_NUM)	/* IRQ3 */
414 #define IPR_IRQ6	(1 << IRQ6_IRQ_NUM)	/* IRQ6 */
415 #define IPR_PEN		(1 << PEN_IRQ_NUM)	/* Pen Interrupt */
416 #define IPR_SPIS	(1 << SPIS_IRQ_NUM)	/* SPI Slave Interrupt */
417 #define IPR_TMR1	(1 << TMR1_IRQ_NUM)	/* Timer 1 interrupt */
418 #define IPR_IRQ7	(1 << IRQ7_IRQ_NUM)	/* IRQ7 */
419 
420 /* 'EZ328-compatible definitions */
421 #define IPR_SPI	IPR_SPIM
422 #define IPR_TMR	IPR_TMR1
423 
424 /**********
425  *
426  * 0xFFFFF4xx -- Parallel Ports
427  *
428  **********/
429 
430 /*
431  * Port A
432  */
433 #define PADIR_ADDR	0xfffff400		/* Port A direction reg */
434 #define PADATA_ADDR	0xfffff401		/* Port A data register */
435 #define PASEL_ADDR	0xfffff403		/* Port A Select register */
436 
437 #define PADIR		BYTE_REF(PADIR_ADDR)
438 #define PADATA		BYTE_REF(PADATA_ADDR)
439 #define PASEL		BYTE_REF(PASEL_ADDR)
440 
441 #define PA(x)           (1 << (x))
442 #define PA_A(x)		PA((x) - 16)	/* This is specific to PA only! */
443 
444 #define PA_A16		PA(0)		/* Use A16 as PA(0) */
445 #define PA_A17		PA(1)		/* Use A17 as PA(1) */
446 #define PA_A18		PA(2)		/* Use A18 as PA(2) */
447 #define PA_A19		PA(3)		/* Use A19 as PA(3) */
448 #define PA_A20		PA(4)		/* Use A20 as PA(4) */
449 #define PA_A21		PA(5)		/* Use A21 as PA(5) */
450 #define PA_A22		PA(6)		/* Use A22 as PA(6) */
451 #define PA_A23		PA(7)		/* Use A23 as PA(7) */
452 
453 /*
454  * Port B
455  */
456 #define PBDIR_ADDR	0xfffff408		/* Port B direction reg */
457 #define PBDATA_ADDR	0xfffff409		/* Port B data register */
458 #define PBSEL_ADDR	0xfffff40b		/* Port B Select Register */
459 
460 #define PBDIR		BYTE_REF(PBDIR_ADDR)
461 #define PBDATA		BYTE_REF(PBDATA_ADDR)
462 #define PBSEL		BYTE_REF(PBSEL_ADDR)
463 
464 #define PB(x)           (1 << (x))
465 #define PB_D(x)		PB(x)		/* This is specific to port B only */
466 
467 #define PB_D0		PB(0)		/* Use D0 as PB(0) */
468 #define PB_D1		PB(1)		/* Use D1 as PB(1) */
469 #define PB_D2		PB(2)		/* Use D2 as PB(2) */
470 #define PB_D3		PB(3)		/* Use D3 as PB(3) */
471 #define PB_D4		PB(4)		/* Use D4 as PB(4) */
472 #define PB_D5		PB(5)		/* Use D5 as PB(5) */
473 #define PB_D6		PB(6)		/* Use D6 as PB(6) */
474 #define PB_D7		PB(7)		/* Use D7 as PB(7) */
475 
476 /*
477  * Port C
478  */
479 #define PCDIR_ADDR	0xfffff410		/* Port C direction reg */
480 #define PCDATA_ADDR	0xfffff411		/* Port C data register */
481 #define PCSEL_ADDR	0xfffff413		/* Port C Select Register */
482 
483 #define PCDIR		BYTE_REF(PCDIR_ADDR)
484 #define PCDATA		BYTE_REF(PCDATA_ADDR)
485 #define PCSEL		BYTE_REF(PCSEL_ADDR)
486 
487 #define PC(x)           (1 << (x))
488 
489 #define PC_WE		PC(6)		/* Use WE    as PC(6) */
490 #define PC_DTACK	PC(5)		/* Use DTACK as PC(5) */
491 #define PC_IRQ7		PC(4)		/* Use IRQ7  as PC(4) */
492 #define PC_LDS		PC(2)		/* Use LDS   as PC(2) */
493 #define PC_UDS		PC(1)		/* Use UDS   as PC(1) */
494 #define PC_MOCLK	PC(0)		/* Use MOCLK as PC(0) */
495 
496 /*
497  * Port D
498  */
499 #define PDDIR_ADDR	0xfffff418		/* Port D direction reg */
500 #define PDDATA_ADDR	0xfffff419		/* Port D data register */
501 #define PDPUEN_ADDR	0xfffff41a		/* Port D Pull-Up enable reg */
502 #define PDPOL_ADDR	0xfffff41c		/* Port D Polarity Register */
503 #define PDIRQEN_ADDR	0xfffff41d		/* Port D IRQ enable register */
504 #define	PDIQEG_ADDR	0xfffff41f		/* Port D IRQ Edge Register */
505 
506 #define PDDIR		BYTE_REF(PDDIR_ADDR)
507 #define PDDATA		BYTE_REF(PDDATA_ADDR)
508 #define PDPUEN		BYTE_REF(PDPUEN_ADDR)
509 #define	PDPOL		BYTE_REF(PDPOL_ADDR)
510 #define PDIRQEN		BYTE_REF(PDIRQEN_ADDR)
511 #define PDIQEG		BYTE_REF(PDIQEG_ADDR)
512 
513 #define PD(x)           (1 << (x))
514 #define PD_KB(x)	PD(x)		/* This is specific for Port D only */
515 
516 #define PD_KB0		PD(0)	/* Use KB0 as PD(0) */
517 #define PD_KB1		PD(1)	/* Use KB1 as PD(1) */
518 #define PD_KB2		PD(2)	/* Use KB2 as PD(2) */
519 #define PD_KB3		PD(3)	/* Use KB3 as PD(3) */
520 #define PD_KB4		PD(4)	/* Use KB4 as PD(4) */
521 #define PD_KB5		PD(5)	/* Use KB5 as PD(5) */
522 #define PD_KB6		PD(6)	/* Use KB6 as PD(6) */
523 #define PD_KB7		PD(7)	/* Use KB7 as PD(7) */
524 
525 /*
526  * Port E
527  */
528 #define PEDIR_ADDR	0xfffff420		/* Port E direction reg */
529 #define PEDATA_ADDR	0xfffff421		/* Port E data register */
530 #define PEPUEN_ADDR	0xfffff422		/* Port E Pull-Up enable reg */
531 #define PESEL_ADDR	0xfffff423		/* Port E Select Register */
532 
533 #define PEDIR		BYTE_REF(PEDIR_ADDR)
534 #define PEDATA		BYTE_REF(PEDATA_ADDR)
535 #define PEPUEN		BYTE_REF(PEPUEN_ADDR)
536 #define PESEL		BYTE_REF(PESEL_ADDR)
537 
538 #define PE(x)           (1 << (x))
539 
540 #define PE_CSA1		PE(1)	/* Use CSA1 as PE(1) */
541 #define PE_CSA2		PE(2)	/* Use CSA2 as PE(2) */
542 #define PE_CSA3		PE(3)	/* Use CSA3 as PE(3) */
543 #define PE_CSB0		PE(4)	/* Use CSB0 as PE(4) */
544 #define PE_CSB1		PE(5)	/* Use CSB1 as PE(5) */
545 #define PE_CSB2		PE(6)	/* Use CSB2 as PE(6) */
546 #define PE_CSB3		PE(7)	/* Use CSB3 as PE(7) */
547 
548 /*
549  * Port F
550  */
551 #define PFDIR_ADDR	0xfffff428		/* Port F direction reg */
552 #define PFDATA_ADDR	0xfffff429		/* Port F data register */
553 #define PFPUEN_ADDR	0xfffff42a		/* Port F Pull-Up enable reg */
554 #define PFSEL_ADDR	0xfffff42b		/* Port F Select Register */
555 
556 #define PFDIR		BYTE_REF(PFDIR_ADDR)
557 #define PFDATA		BYTE_REF(PFDATA_ADDR)
558 #define PFPUEN		BYTE_REF(PFPUEN_ADDR)
559 #define PFSEL		BYTE_REF(PFSEL_ADDR)
560 
561 #define PF(x)           (1 << (x))
562 #define PF_A(x)		PF((x) - 24)	/* This is Port F specific only */
563 
564 #define PF_A24		PF(0)	/* Use A24 as PF(0) */
565 #define PF_A25		PF(1)	/* Use A25 as PF(1) */
566 #define PF_A26		PF(2)	/* Use A26 as PF(2) */
567 #define PF_A27		PF(3)	/* Use A27 as PF(3) */
568 #define PF_A28		PF(4)	/* Use A28 as PF(4) */
569 #define PF_A29		PF(5)	/* Use A29 as PF(5) */
570 #define PF_A30		PF(6)	/* Use A30 as PF(6) */
571 #define PF_A31		PF(7)	/* Use A31 as PF(7) */
572 
573 /*
574  * Port G
575  */
576 #define PGDIR_ADDR	0xfffff430		/* Port G direction reg */
577 #define PGDATA_ADDR	0xfffff431		/* Port G data register */
578 #define PGPUEN_ADDR	0xfffff432		/* Port G Pull-Up enable reg */
579 #define PGSEL_ADDR	0xfffff433		/* Port G Select Register */
580 
581 #define PGDIR		BYTE_REF(PGDIR_ADDR)
582 #define PGDATA		BYTE_REF(PGDATA_ADDR)
583 #define PGPUEN		BYTE_REF(PGPUEN_ADDR)
584 #define PGSEL		BYTE_REF(PGSEL_ADDR)
585 
586 #define PG(x)           (1 << (x))
587 
588 #define PG_UART_TXD	PG(0)	/* Use UART_TXD as PG(0) */
589 #define PG_UART_RXD	PG(1)	/* Use UART_RXD as PG(1) */
590 #define PG_PWMOUT	PG(2)	/* Use PWMOUT   as PG(2) */
591 #define PG_TOUT2	PG(3)   /* Use TOUT2    as PG(3) */
592 #define PG_TIN2		PG(4)	/* Use TIN2     as PG(4) */
593 #define PG_TOUT1	PG(5)   /* Use TOUT1    as PG(5) */
594 #define PG_TIN1		PG(6)	/* Use TIN1     as PG(6) */
595 #define PG_RTCOUT	PG(7)	/* Use RTCOUT   as PG(7) */
596 
597 /*
598  * Port J
599  */
600 #define PJDIR_ADDR	0xfffff438		/* Port J direction reg */
601 #define PJDATA_ADDR	0xfffff439		/* Port J data register */
602 #define PJSEL_ADDR	0xfffff43b		/* Port J Select Register */
603 
604 #define PJDIR		BYTE_REF(PJDIR_ADDR)
605 #define PJDATA		BYTE_REF(PJDATA_ADDR)
606 #define PJSEL		BYTE_REF(PJSEL_ADDR)
607 
608 #define PJ(x)           (1 << (x))
609 
610 #define PJ_CSD3		PJ(7)	/* Use CSD3 as PJ(7) */
611 
612 /*
613  * Port K
614  */
615 #define PKDIR_ADDR	0xfffff440		/* Port K direction reg */
616 #define PKDATA_ADDR	0xfffff441		/* Port K data register */
617 #define PKPUEN_ADDR	0xfffff442		/* Port K Pull-Up enable reg */
618 #define PKSEL_ADDR	0xfffff443		/* Port K Select Register */
619 
620 #define PKDIR		BYTE_REF(PKDIR_ADDR)
621 #define PKDATA		BYTE_REF(PKDATA_ADDR)
622 #define PKPUEN		BYTE_REF(PKPUEN_ADDR)
623 #define PKSEL		BYTE_REF(PKSEL_ADDR)
624 
625 #define PK(x)           (1 << (x))
626 
627 /*
628  * Port M
629  */
630 #define PMDIR_ADDR	0xfffff438		/* Port M direction reg */
631 #define PMDATA_ADDR	0xfffff439		/* Port M data register */
632 #define PMPUEN_ADDR	0xfffff43a		/* Port M Pull-Up enable reg */
633 #define PMSEL_ADDR	0xfffff43b		/* Port M Select Register */
634 
635 #define PMDIR		BYTE_REF(PMDIR_ADDR)
636 #define PMDATA		BYTE_REF(PMDATA_ADDR)
637 #define PMPUEN		BYTE_REF(PMPUEN_ADDR)
638 #define PMSEL		BYTE_REF(PMSEL_ADDR)
639 
640 #define PM(x)           (1 << (x))
641 
642 /**********
643  *
644  * 0xFFFFF5xx -- Pulse-Width Modulator (PWM)
645  *
646  **********/
647 
648 /*
649  * PWM Control Register
650  */
651 #define PWMC_ADDR	0xfffff500
652 #define PWMC		WORD_REF(PWMC_ADDR)
653 
654 #define PWMC_CLKSEL_MASK	0x0007	/* Clock Selection */
655 #define PWMC_CLKSEL_SHIFT	0
656 #define PWMC_PWMEN		0x0010	/* Enable PWM */
657 #define PMNC_POL		0x0020	/* PWM Output Bit Polarity */
658 #define PWMC_PIN		0x0080	/* Current PWM output pin status */
659 #define PWMC_LOAD		0x0100	/* Force a new period */
660 #define PWMC_IRQEN		0x4000	/* Interrupt Request Enable */
661 #define PWMC_CLKSRC		0x8000	/* Clock Source Select */
662 
663 /* 'EZ328-compatible definitions */
664 #define PWMC_EN	PWMC_PWMEN
665 
666 /*
667  * PWM Period Register
668  */
669 #define PWMP_ADDR	0xfffff502
670 #define PWMP		WORD_REF(PWMP_ADDR)
671 
672 /*
673  * PWM Width Register
674  */
675 #define PWMW_ADDR	0xfffff504
676 #define PWMW		WORD_REF(PWMW_ADDR)
677 
678 /*
679  * PWM Counter Register
680  */
681 #define PWMCNT_ADDR	0xfffff506
682 #define PWMCNT		WORD_REF(PWMCNT_ADDR)
683 
684 /**********
685  *
686  * 0xFFFFF6xx -- General-Purpose Timers
687  *
688  **********/
689 
690 /*
691  * Timer Unit 1 and 2 Control Registers
692  */
693 #define TCTL1_ADDR	0xfffff600
694 #define TCTL1		WORD_REF(TCTL1_ADDR)
695 #define TCTL2_ADDR	0xfffff60c
696 #define TCTL2		WORD_REF(TCTL2_ADDR)
697 
698 #define	TCTL_TEN		0x0001	/* Timer Enable  */
699 #define TCTL_CLKSOURCE_MASK 	0x000e	/* Clock Source: */
700 #define   TCTL_CLKSOURCE_STOP	   0x0000	/* Stop count (disabled)    */
701 #define   TCTL_CLKSOURCE_SYSCLK	   0x0002	/* SYSCLK to prescaler      */
702 #define   TCTL_CLKSOURCE_SYSCLK_16 0x0004	/* SYSCLK/16 to prescaler   */
703 #define   TCTL_CLKSOURCE_TIN	   0x0006	/* TIN to prescaler         */
704 #define   TCTL_CLKSOURCE_32KHZ	   0x0008	/* 32kHz clock to prescaler */
705 #define TCTL_IRQEN		0x0010	/* IRQ Enable    */
706 #define TCTL_OM			0x0020	/* Output Mode   */
707 #define TCTL_CAP_MASK		0x00c0	/* Capture Edge: */
708 #define	  TCTL_CAP_RE		0x0040		/* Capture on rizing edge   */
709 #define   TCTL_CAP_FE		0x0080		/* Capture on falling edge  */
710 #define TCTL_FRR		0x0010	/* Free-Run Mode */
711 
712 /* 'EZ328-compatible definitions */
713 #define TCTL_ADDR	TCTL1_ADDR
714 #define TCTL		TCTL1
715 
716 /*
717  * Timer Unit 1 and 2 Prescaler Registers
718  */
719 #define TPRER1_ADDR	0xfffff602
720 #define TPRER1		WORD_REF(TPRER1_ADDR)
721 #define TPRER2_ADDR	0xfffff60e
722 #define TPRER2		WORD_REF(TPRER2_ADDR)
723 
724 /* 'EZ328-compatible definitions */
725 #define TPRER_ADDR	TPRER1_ADDR
726 #define TPRER		TPRER1
727 
728 /*
729  * Timer Unit 1 and 2 Compare Registers
730  */
731 #define TCMP1_ADDR	0xfffff604
732 #define TCMP1		WORD_REF(TCMP1_ADDR)
733 #define TCMP2_ADDR	0xfffff610
734 #define TCMP2		WORD_REF(TCMP2_ADDR)
735 
736 /* 'EZ328-compatible definitions */
737 #define TCMP_ADDR	TCMP1_ADDR
738 #define TCMP		TCMP1
739 
740 /*
741  * Timer Unit 1 and 2 Capture Registers
742  */
743 #define TCR1_ADDR	0xfffff606
744 #define TCR1		WORD_REF(TCR1_ADDR)
745 #define TCR2_ADDR	0xfffff612
746 #define TCR2		WORD_REF(TCR2_ADDR)
747 
748 /* 'EZ328-compatible definitions */
749 #define TCR_ADDR	TCR1_ADDR
750 #define TCR		TCR1
751 
752 /*
753  * Timer Unit 1 and 2 Counter Registers
754  */
755 #define TCN1_ADDR	0xfffff608
756 #define TCN1		WORD_REF(TCN1_ADDR)
757 #define TCN2_ADDR	0xfffff614
758 #define TCN2		WORD_REF(TCN2_ADDR)
759 
760 /* 'EZ328-compatible definitions */
761 #define TCN_ADDR	TCN1_ADDR
762 #define TCN		TCN1
763 
764 /*
765  * Timer Unit 1 and 2 Status Registers
766  */
767 #define TSTAT1_ADDR	0xfffff60a
768 #define TSTAT1		WORD_REF(TSTAT1_ADDR)
769 #define TSTAT2_ADDR	0xfffff616
770 #define TSTAT2		WORD_REF(TSTAT2_ADDR)
771 
772 #define TSTAT_COMP	0x0001		/* Compare Event occurred */
773 #define TSTAT_CAPT	0x0001		/* Capture Event occurred */
774 
775 /* 'EZ328-compatible definitions */
776 #define TSTAT_ADDR	TSTAT1_ADDR
777 #define TSTAT		TSTAT1
778 
779 /*
780  * Watchdog Compare Register
781  */
782 #define WRR_ADDR	0xfffff61a
783 #define WRR		WORD_REF(WRR_ADDR)
784 
785 /*
786  * Watchdog Counter Register
787  */
788 #define WCN_ADDR	0xfffff61c
789 #define WCN		WORD_REF(WCN_ADDR)
790 
791 /*
792  * Watchdog Control and Status Register
793  */
794 #define WCSR_ADDR	0xfffff618
795 #define WCSR		WORD_REF(WCSR_ADDR)
796 
797 #define WCSR_WDEN	0x0001	/* Watchdog Enable */
798 #define WCSR_FI		0x0002	/* Forced Interrupt (instead of SW reset)*/
799 #define WCSR_WRST	0x0004	/* Watchdog Reset */
800 
801 /**********
802  *
803  * 0xFFFFF7xx -- Serial Peripheral Interface Slave (SPIS)
804  *
805  **********/
806 
807 /*
808  * SPI Slave Register
809  */
810 #define SPISR_ADDR	0xfffff700
811 #define SPISR		WORD_REF(SPISR_ADDR)
812 
813 #define SPISR_DATA_ADDR	0xfffff701
814 #define SPISR_DATA	BYTE_REF(SPISR_DATA_ADDR)
815 
816 #define SPISR_DATA_MASK	 0x00ff	/* Shifted data from the external device */
817 #define SPISR_DATA_SHIFT 0
818 #define SPISR_SPISEN	 0x0100	/* SPIS module enable */
819 #define SPISR_POL	 0x0200	/* SPSCLK polarity control */
820 #define SPISR_PHA	 0x0400	/* Phase relationship between SPSCLK & SPSRxD */
821 #define SPISR_OVWR	 0x0800	/* Data buffer has been overwritten */
822 #define SPISR_DATARDY	 0x1000	/* Data ready */
823 #define SPISR_ENPOL	 0x2000	/* Enable Polarity */
824 #define SPISR_IRQEN	 0x4000	/* SPIS IRQ Enable */
825 #define SPISR_SPISIRQ	 0x8000	/* SPIS IRQ posted */
826 
827 /**********
828  *
829  * 0xFFFFF8xx -- Serial Peripheral Interface Master (SPIM)
830  *
831  **********/
832 
833 /*
834  * SPIM Data Register
835  */
836 #define SPIMDATA_ADDR	0xfffff800
837 #define SPIMDATA	WORD_REF(SPIMDATA_ADDR)
838 
839 /*
840  * SPIM Control/Status Register
841  */
842 #define SPIMCONT_ADDR	0xfffff802
843 #define SPIMCONT	WORD_REF(SPIMCONT_ADDR)
844 
845 #define SPIMCONT_BIT_COUNT_MASK	 0x000f	/* Transfer Length in Bytes */
846 #define SPIMCONT_BIT_COUNT_SHIFT 0
847 #define SPIMCONT_POL		 0x0010	/* SPMCLK Signel Polarity */
848 #define	SPIMCONT_PHA		 0x0020	/* Clock/Data phase relationship */
849 #define SPIMCONT_IRQEN		 0x0040 /* IRQ Enable */
850 #define SPIMCONT_SPIMIRQ	 0x0080	/* Interrupt Request */
851 #define SPIMCONT_XCH		 0x0100	/* Exchange */
852 #define SPIMCONT_RSPIMEN	 0x0200	/* Enable SPIM */
853 #define SPIMCONT_DATA_RATE_MASK	 0xe000	/* SPIM Data Rate */
854 #define SPIMCONT_DATA_RATE_SHIFT 13
855 
856 /* 'EZ328-compatible definitions */
857 #define SPIMCONT_IRQ	SPIMCONT_SPIMIRQ
858 #define SPIMCONT_ENABLE	SPIMCONT_SPIMEN
859 /**********
860  *
861  * 0xFFFFF9xx -- UART
862  *
863  **********/
864 
865 /*
866  * UART Status/Control Register
867  */
868 #define USTCNT_ADDR	0xfffff900
869 #define USTCNT		WORD_REF(USTCNT_ADDR)
870 
871 #define USTCNT_TXAVAILEN	0x0001	/* Transmitter Available Int Enable */
872 #define USTCNT_TXHALFEN		0x0002	/* Transmitter Half Empty Int Enable */
873 #define USTCNT_TXEMPTYEN	0x0004	/* Transmitter Empty Int Enable */
874 #define USTCNT_RXREADYEN	0x0008	/* Receiver Ready Interrupt Enable */
875 #define USTCNT_RXHALFEN		0x0010	/* Receiver Half-Full Int Enable */
876 #define USTCNT_RXFULLEN		0x0020	/* Receiver Full Interrupt Enable */
877 #define USTCNT_CTSDELTAEN	0x0040	/* CTS Delta Interrupt Enable */
878 #define USTCNT_GPIODELTAEN	0x0080	/* Old Data Interrupt Enable */
879 #define USTCNT_8_7		0x0100	/* Eight or seven-bit transmission */
880 #define USTCNT_STOP		0x0200	/* Stop bit transmission */
881 #define USTCNT_ODD_EVEN		0x0400	/* Odd Parity */
882 #define	USTCNT_PARITYEN		0x0800	/* Parity Enable */
883 #define USTCNT_CLKMODE		0x1000	/* Clock Mode Select */
884 #define	USTCNT_TXEN		0x2000	/* Transmitter Enable */
885 #define USTCNT_RXEN		0x4000	/* Receiver Enable */
886 #define USTCNT_UARTEN		0x8000	/* UART Enable */
887 
888 /* 'EZ328-compatible definitions */
889 #define USTCNT_TXAE	USTCNT_TXAVAILEN
890 #define USTCNT_TXHE	USTCNT_TXHALFEN
891 #define USTCNT_TXEE	USTCNT_TXEMPTYEN
892 #define USTCNT_RXRE	USTCNT_RXREADYEN
893 #define USTCNT_RXHE	USTCNT_RXHALFEN
894 #define USTCNT_RXFE	USTCNT_RXFULLEN
895 #define USTCNT_CTSD	USTCNT_CTSDELTAEN
896 #define USTCNT_ODD	USTCNT_ODD_EVEN
897 #define USTCNT_PEN	USTCNT_PARITYEN
898 #define USTCNT_CLKM	USTCNT_CLKMODE
899 #define USTCNT_UEN	USTCNT_UARTEN
900 
901 /*
902  * UART Baud Control Register
903  */
904 #define UBAUD_ADDR	0xfffff902
905 #define UBAUD		WORD_REF(UBAUD_ADDR)
906 
907 #define UBAUD_PRESCALER_MASK	0x003f	/* Actual divisor is 65 - PRESCALER */
908 #define UBAUD_PRESCALER_SHIFT	0
909 #define UBAUD_DIVIDE_MASK	0x0700	/* Baud Rate freq. divisor */
910 #define UBAUD_DIVIDE_SHIFT	8
911 #define UBAUD_BAUD_SRC		0x0800	/* Baud Rate Source */
912 #define UBAUD_GPIOSRC		0x1000	/* GPIO source */
913 #define UBAUD_GPIODIR		0x2000	/* GPIO Direction */
914 #define UBAUD_GPIO		0x4000	/* Current GPIO pin status */
915 #define UBAUD_GPIODELTA		0x8000	/* GPIO pin value changed */
916 
917 /*
918  * UART Receiver Register
919  */
920 #define URX_ADDR	0xfffff904
921 #define URX		WORD_REF(URX_ADDR)
922 
923 #define URX_RXDATA_ADDR	0xfffff905
924 #define URX_RXDATA	BYTE_REF(URX_RXDATA_ADDR)
925 
926 #define URX_RXDATA_MASK	 0x00ff	/* Received data */
927 #define URX_RXDATA_SHIFT 0
928 #define URX_PARITY_ERROR 0x0100	/* Parity Error */
929 #define URX_BREAK	 0x0200	/* Break Detected */
930 #define URX_FRAME_ERROR	 0x0400	/* Framing Error */
931 #define URX_OVRUN	 0x0800	/* Serial Overrun */
932 #define URX_DATA_READY	 0x2000	/* Data Ready (FIFO not empty) */
933 #define URX_FIFO_HALF	 0x4000 /* FIFO is Half-Full */
934 #define URX_FIFO_FULL	 0x8000	/* FIFO is Full */
935 
936 /*
937  * UART Transmitter Register
938  */
939 #define UTX_ADDR	0xfffff906
940 #define UTX		WORD_REF(UTX_ADDR)
941 
942 #define UTX_TXDATA_ADDR	0xfffff907
943 #define UTX_TXDATA	BYTE_REF(UTX_TXDATA_ADDR)
944 
945 #define UTX_TXDATA_MASK	 0x00ff	/* Data to be transmitted */
946 #define UTX_TXDATA_SHIFT 0
947 #define UTX_CTS_DELTA	 0x0100	/* CTS changed */
948 #define UTX_CTS_STATUS	 0x0200	/* CTS State */
949 #define	UTX_IGNORE_CTS	 0x0800	/* Ignore CTS */
950 #define UTX_SEND_BREAK	 0x1000	/* Send a BREAK */
951 #define UTX_TX_AVAIL	 0x2000	/* Transmit FIFO has a slot available */
952 #define UTX_FIFO_HALF	 0x4000	/* Transmit FIFO is half empty */
953 #define UTX_FIFO_EMPTY	 0x8000	/* Transmit FIFO is empty */
954 
955 /* 'EZ328-compatible definitions */
956 #define UTX_CTS_STAT	UTX_CTS_STATUS
957 #define UTX_NOCTS	UTX_IGNORE_CTS
958 
959 /*
960  * UART Miscellaneous Register
961  */
962 #define UMISC_ADDR	0xfffff908
963 #define UMISC		WORD_REF(UMISC_ADDR)
964 
965 #define UMISC_TX_POL	 0x0004	/* Transmit Polarity */
966 #define UMISC_RX_POL	 0x0008	/* Receive Polarity */
967 #define UMISC_IRDA_LOOP	 0x0010	/* IrDA Loopback Enable */
968 #define UMISC_IRDA_EN	 0x0020	/* Infra-Red Enable */
969 #define UMISC_RTS	 0x0040	/* Set RTS status */
970 #define UMISC_RTSCONT	 0x0080	/* Choose RTS control */
971 #define UMISC_LOOP	 0x1000	/* Serial Loopback Enable */
972 #define UMISC_FORCE_PERR 0x2000	/* Force Parity Error */
973 #define UMISC_CLKSRC	 0x4000	/* Clock Source */
974 
975 
976 /* generalization of uart control registers to support multiple ports: */
977 typedef volatile struct {
978   volatile unsigned short int ustcnt;
979   volatile unsigned short int ubaud;
980   union {
981     volatile unsigned short int w;
982     struct {
983       volatile unsigned char status;
984       volatile unsigned char rxdata;
985     } b;
986   } urx;
987   union {
988     volatile unsigned short int w;
989     struct {
990       volatile unsigned char status;
991       volatile unsigned char txdata;
992     } b;
993   } utx;
994   volatile unsigned short int umisc;
995   volatile unsigned short int pad1;
996   volatile unsigned short int pad2;
997   volatile unsigned short int pad3;
998 } __packed m68328_uart;
999 
1000 
1001 /**********
1002  *
1003  * 0xFFFFFAxx -- LCD Controller
1004  *
1005  **********/
1006 
1007 /*
1008  * LCD Screen Starting Address Register
1009  */
1010 #define LSSA_ADDR	0xfffffa00
1011 #define LSSA		LONG_REF(LSSA_ADDR)
1012 
1013 #define LSSA_SSA_MASK	0xfffffffe	/* Bit 0 is reserved */
1014 
1015 /*
1016  * LCD Virtual Page Width Register
1017  */
1018 #define LVPW_ADDR	0xfffffa05
1019 #define LVPW		BYTE_REF(LVPW_ADDR)
1020 
1021 /*
1022  * LCD Screen Width Register (not compatible with 'EZ328 !!!)
1023  */
1024 #define LXMAX_ADDR	0xfffffa08
1025 #define LXMAX		WORD_REF(LXMAX_ADDR)
1026 
1027 #define LXMAX_XM_MASK	0x02ff		/* Bits 0-3 are reserved */
1028 
1029 /*
1030  * LCD Screen Height Register
1031  */
1032 #define LYMAX_ADDR	0xfffffa0a
1033 #define LYMAX		WORD_REF(LYMAX_ADDR)
1034 
1035 #define LYMAX_YM_MASK	0x02ff		/* Bits 10-15 are reserved */
1036 
1037 /*
1038  * LCD Cursor X Position Register
1039  */
1040 #define LCXP_ADDR	0xfffffa18
1041 #define LCXP		WORD_REF(LCXP_ADDR)
1042 
1043 #define LCXP_CC_MASK	0xc000		/* Cursor Control */
1044 #define   LCXP_CC_TRAMSPARENT	0x0000
1045 #define   LCXP_CC_BLACK		0x4000
1046 #define   LCXP_CC_REVERSED	0x8000
1047 #define   LCXP_CC_WHITE		0xc000
1048 #define LCXP_CXP_MASK	0x02ff		/* Cursor X position */
1049 
1050 /*
1051  * LCD Cursor Y Position Register
1052  */
1053 #define LCYP_ADDR	0xfffffa1a
1054 #define LCYP		WORD_REF(LCYP_ADDR)
1055 
1056 #define LCYP_CYP_MASK	0x01ff		/* Cursor Y Position */
1057 
1058 /*
1059  * LCD Cursor Width and Heigth Register
1060  */
1061 #define LCWCH_ADDR	0xfffffa1c
1062 #define LCWCH		WORD_REF(LCWCH_ADDR)
1063 
1064 #define LCWCH_CH_MASK	0x001f		/* Cursor Height */
1065 #define LCWCH_CH_SHIFT	0
1066 #define LCWCH_CW_MASK	0x1f00		/* Cursor Width */
1067 #define LCWCH_CW_SHIFT	8
1068 
1069 /*
1070  * LCD Blink Control Register
1071  */
1072 #define LBLKC_ADDR	0xfffffa1f
1073 #define LBLKC		BYTE_REF(LBLKC_ADDR)
1074 
1075 #define LBLKC_BD_MASK	0x7f	/* Blink Divisor */
1076 #define LBLKC_BD_SHIFT	0
1077 #define LBLKC_BKEN	0x80	/* Blink Enabled */
1078 
1079 /*
1080  * LCD Panel Interface Configuration Register
1081  */
1082 #define LPICF_ADDR	0xfffffa20
1083 #define LPICF		BYTE_REF(LPICF_ADDR)
1084 
1085 #define LPICF_GS_MASK	 0x01	 /* Gray-Scale Mode */
1086 #define	  LPICF_GS_BW	   0x00
1087 #define   LPICF_GS_GRAY_4  0x01
1088 #define LPICF_PBSIZ_MASK 0x06	/* Panel Bus Width */
1089 #define   LPICF_PBSIZ_1	   0x00
1090 #define   LPICF_PBSIZ_2    0x02
1091 #define   LPICF_PBSIZ_4    0x04
1092 
1093 /*
1094  * LCD Polarity Configuration Register
1095  */
1096 #define LPOLCF_ADDR	0xfffffa21
1097 #define LPOLCF		BYTE_REF(LPOLCF_ADDR)
1098 
1099 #define LPOLCF_PIXPOL	0x01	/* Pixel Polarity */
1100 #define LPOLCF_LPPOL	0x02	/* Line Pulse Polarity */
1101 #define LPOLCF_FLMPOL	0x04	/* Frame Marker Polarity */
1102 #define LPOLCF_LCKPOL	0x08	/* LCD Shift Lock Polarity */
1103 
1104 /*
1105  * LACD (LCD Alternate Crystal Direction) Rate Control Register
1106  */
1107 #define LACDRC_ADDR	0xfffffa23
1108 #define LACDRC		BYTE_REF(LACDRC_ADDR)
1109 
1110 #define LACDRC_ACD_MASK	 0x0f	/* Alternate Crystal Direction Control */
1111 #define LACDRC_ACD_SHIFT 0
1112 
1113 /*
1114  * LCD Pixel Clock Divider Register
1115  */
1116 #define LPXCD_ADDR	0xfffffa25
1117 #define LPXCD		BYTE_REF(LPXCD_ADDR)
1118 
1119 #define	LPXCD_PCD_MASK	0x3f 	/* Pixel Clock Divider */
1120 #define LPXCD_PCD_SHIFT	0
1121 
1122 /*
1123  * LCD Clocking Control Register
1124  */
1125 #define LCKCON_ADDR	0xfffffa27
1126 #define LCKCON		BYTE_REF(LCKCON_ADDR)
1127 
1128 #define LCKCON_PCDS	 0x01	/* Pixel Clock Divider Source Select */
1129 #define LCKCON_DWIDTH	 0x02	/* Display Memory Width  */
1130 #define LCKCON_DWS_MASK	 0x3c	/* Display Wait-State */
1131 #define LCKCON_DWS_SHIFT 2
1132 #define LCKCON_DMA16	 0x40	/* DMA burst length */
1133 #define LCKCON_LCDON	 0x80	/* Enable LCD Controller */
1134 
1135 /* 'EZ328-compatible definitions */
1136 #define LCKCON_DW_MASK	LCKCON_DWS_MASK
1137 #define LCKCON_DW_SHIFT	LCKCON_DWS_SHIFT
1138 
1139 /*
1140  * LCD Last Buffer Address Register
1141  */
1142 #define LLBAR_ADDR	0xfffffa29
1143 #define LLBAR		BYTE_REF(LLBAR_ADDR)
1144 
1145 #define LLBAR_LBAR_MASK	 0x7f	/* Number of memory words to fill 1 line */
1146 #define LLBAR_LBAR_SHIFT 0
1147 
1148 /*
1149  * LCD Octet Terminal Count Register
1150  */
1151 #define LOTCR_ADDR	0xfffffa2b
1152 #define LOTCR		BYTE_REF(LOTCR_ADDR)
1153 
1154 /*
1155  * LCD Panning Offset Register
1156  */
1157 #define LPOSR_ADDR	0xfffffa2d
1158 #define LPOSR		BYTE_REF(LPOSR_ADDR)
1159 
1160 #define LPOSR_BOS	0x08	/* Byte offset (for B/W mode only */
1161 #define LPOSR_POS_MASK	0x07	/* Pixel Offset Code */
1162 #define LPOSR_POS_SHIFT	0
1163 
1164 /*
1165  * LCD Frame Rate Control Modulation Register
1166  */
1167 #define LFRCM_ADDR	0xfffffa31
1168 #define LFRCM		BYTE_REF(LFRCM_ADDR)
1169 
1170 #define LFRCM_YMOD_MASK	 0x0f	/* Vertical Modulation */
1171 #define LFRCM_YMOD_SHIFT 0
1172 #define LFRCM_XMOD_MASK	 0xf0	/* Horizontal Modulation */
1173 #define LFRCM_XMOD_SHIFT 4
1174 
1175 /*
1176  * LCD Gray Palette Mapping Register
1177  */
1178 #define LGPMR_ADDR	0xfffffa32
1179 #define LGPMR		WORD_REF(LGPMR_ADDR)
1180 
1181 #define LGPMR_GLEVEL3_MASK	0x000f
1182 #define LGPMR_GLEVEL3_SHIFT	0
1183 #define LGPMR_GLEVEL2_MASK	0x00f0
1184 #define LGPMR_GLEVEL2_SHIFT	4
1185 #define LGPMR_GLEVEL0_MASK	0x0f00
1186 #define LGPMR_GLEVEL0_SHIFT	8
1187 #define LGPMR_GLEVEL1_MASK	0xf000
1188 #define LGPMR_GLEVEL1_SHIFT	12
1189 
1190 /**********
1191  *
1192  * 0xFFFFFBxx -- Real-Time Clock (RTC)
1193  *
1194  **********/
1195 
1196 /*
1197  * RTC Hours Minutes and Seconds Register
1198  */
1199 #define RTCTIME_ADDR	0xfffffb00
1200 #define RTCTIME		LONG_REF(RTCTIME_ADDR)
1201 
1202 #define RTCTIME_SECONDS_MASK	0x0000003f	/* Seconds */
1203 #define RTCTIME_SECONDS_SHIFT	0
1204 #define RTCTIME_MINUTES_MASK	0x003f0000	/* Minutes */
1205 #define RTCTIME_MINUTES_SHIFT	16
1206 #define RTCTIME_HOURS_MASK	0x1f000000	/* Hours */
1207 #define RTCTIME_HOURS_SHIFT	24
1208 
1209 /*
1210  *  RTC Alarm Register
1211  */
1212 #define RTCALRM_ADDR    0xfffffb04
1213 #define RTCALRM         LONG_REF(RTCALRM_ADDR)
1214 
1215 #define RTCALRM_SECONDS_MASK    0x0000003f      /* Seconds */
1216 #define RTCALRM_SECONDS_SHIFT   0
1217 #define RTCALRM_MINUTES_MASK    0x003f0000      /* Minutes */
1218 #define RTCALRM_MINUTES_SHIFT   16
1219 #define RTCALRM_HOURS_MASK      0x1f000000      /* Hours */
1220 #define RTCALRM_HOURS_SHIFT     24
1221 
1222 /*
1223  * RTC Control Register
1224  */
1225 #define RTCCTL_ADDR	0xfffffb0c
1226 #define RTCCTL		WORD_REF(RTCCTL_ADDR)
1227 
1228 #define RTCCTL_384	0x0020	/* Crystal Selection */
1229 #define RTCCTL_ENABLE	0x0080	/* RTC Enable */
1230 
1231 /* 'EZ328-compatible definitions */
1232 #define RTCCTL_XTL	RTCCTL_384
1233 #define RTCCTL_EN	RTCCTL_ENABLE
1234 
1235 /*
1236  * RTC Interrupt Status Register
1237  */
1238 #define RTCISR_ADDR	0xfffffb0e
1239 #define RTCISR		WORD_REF(RTCISR_ADDR)
1240 
1241 #define RTCISR_SW	0x0001	/* Stopwatch timed out */
1242 #define RTCISR_MIN	0x0002	/* 1-minute interrupt has occurred */
1243 #define RTCISR_ALM	0x0004	/* Alarm interrupt has occurred */
1244 #define RTCISR_DAY	0x0008	/* 24-hour rollover interrupt has occurred */
1245 #define RTCISR_1HZ	0x0010	/* 1Hz interrupt has occurred */
1246 
1247 /*
1248  * RTC Interrupt Enable Register
1249  */
1250 #define RTCIENR_ADDR	0xfffffb10
1251 #define RTCIENR		WORD_REF(RTCIENR_ADDR)
1252 
1253 #define RTCIENR_SW	0x0001	/* Stopwatch interrupt enable */
1254 #define RTCIENR_MIN	0x0002	/* 1-minute interrupt enable */
1255 #define RTCIENR_ALM	0x0004	/* Alarm interrupt enable */
1256 #define RTCIENR_DAY	0x0008	/* 24-hour rollover interrupt enable */
1257 #define RTCIENR_1HZ	0x0010	/* 1Hz interrupt enable */
1258 
1259 /*
1260  * Stopwatch Minutes Register
1261  */
1262 #define STPWCH_ADDR	0xfffffb12
1263 #define STPWCH		WORD_REF(STPWCH)
1264 
1265 #define STPWCH_CNT_MASK	 0x00ff	/* Stopwatch countdown value */
1266 #define SPTWCH_CNT_SHIFT 0
1267 
1268 #endif /* _MC68328_H_ */
1269