1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Intel E3-1200
4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
5 *
6 * Support for the E3-1200 processor family. Heavily based on previous
7 * Intel EDAC drivers.
8 *
9 * Since the DRAM controller is on the cpu chip, we can use its PCI device
10 * id to identify these processors.
11 *
12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/)
13 *
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
22 * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
23 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
24 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers
25 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers
26 *
27 * Based on Intel specification:
28 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
29 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
30 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf
32 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
33 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html
34 *
35 * According to the above datasheet (p.16):
36 * "
37 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
38 * requests that cross a DW boundary.
39 * "
40 *
41 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
42 * 2 readl() calls. This restriction may be lifted in subsequent chip releases,
43 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
44 */
45
46 #include <linux/module.h>
47 #include <linux/init.h>
48 #include <linux/pci.h>
49 #include <linux/pci_ids.h>
50 #include <linux/edac.h>
51
52 #include <linux/io-64-nonatomic-lo-hi.h>
53 #include "edac_module.h"
54
55 #define EDAC_MOD_STR "ie31200_edac"
56
57 #define ie31200_printk(level, fmt, arg...) \
58 edac_printk(level, "ie31200", fmt, ##arg)
59
60 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F
68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918
69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
71
72 /* Coffee Lake-S */
73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f
75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18
76 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f
77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30
78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31
79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32
80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33
81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2
82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6
83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca
84
85 /* Test if HB is for Skylake or later. */
86 #define DEVICE_ID_SKYLAKE_OR_LATER(did) \
87 (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \
88 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \
89 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \
90 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \
91 (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \
92 PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
93
94 #define IE31200_RANKS_PER_CHANNEL 4
95 #define IE31200_DIMMS_PER_CHANNEL 2
96 #define IE31200_CHANNELS 2
97
98 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
99 #define IE31200_MCHBAR_LOW 0x48
100 #define IE31200_MCHBAR_HIGH 0x4c
101 #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
102 #define IE31200_MMR_WINDOW_SIZE BIT(15)
103
104 /*
105 * Error Status Register (16b)
106 *
107 * 15 reserved
108 * 14 Isochronous TBWRR Run Behind FIFO Full
109 * (ITCV)
110 * 13 Isochronous TBWRR Run Behind FIFO Put
111 * (ITSTV)
112 * 12 reserved
113 * 11 MCH Thermal Sensor Event
114 * for SMI/SCI/SERR (GTSE)
115 * 10 reserved
116 * 9 LOCK to non-DRAM Memory Flag (LCKF)
117 * 8 reserved
118 * 7 DRAM Throttle Flag (DTF)
119 * 6:2 reserved
120 * 1 Multi-bit DRAM ECC Error Flag (DMERR)
121 * 0 Single-bit DRAM ECC Error Flag (DSERR)
122 */
123 #define IE31200_ERRSTS 0xc8
124 #define IE31200_ERRSTS_UE BIT(1)
125 #define IE31200_ERRSTS_CE BIT(0)
126 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
127
128 /*
129 * Channel 0 ECC Error Log (64b)
130 *
131 * 63:48 Error Column Address (ERRCOL)
132 * 47:32 Error Row Address (ERRROW)
133 * 31:29 Error Bank Address (ERRBANK)
134 * 28:27 Error Rank Address (ERRRANK)
135 * 26:24 reserved
136 * 23:16 Error Syndrome (ERRSYND)
137 * 15: 2 reserved
138 * 1 Multiple Bit Error Status (MERRSTS)
139 * 0 Correctable Error Status (CERRSTS)
140 */
141
142 #define IE31200_C0ECCERRLOG 0x40c8
143 #define IE31200_C1ECCERRLOG 0x44c8
144 #define IE31200_C0ECCERRLOG_SKL 0x4048
145 #define IE31200_C1ECCERRLOG_SKL 0x4448
146 #define IE31200_ECCERRLOG_CE BIT(0)
147 #define IE31200_ECCERRLOG_UE BIT(1)
148 #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
149 #define IE31200_ECCERRLOG_RANK_SHIFT 27
150 #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
151 #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
152
153 #define IE31200_ECCERRLOG_SYNDROME(log) \
154 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
155 IE31200_ECCERRLOG_SYNDROME_SHIFT)
156
157 #define IE31200_CAPID0 0xe4
158 #define IE31200_CAPID0_PDCD BIT(4)
159 #define IE31200_CAPID0_DDPCD BIT(6)
160 #define IE31200_CAPID0_ECC BIT(1)
161
162 #define IE31200_MAD_DIMM_0_OFFSET 0x5004
163 #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C
164 #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
165 #define IE31200_MAD_DIMM_SIZE_SKL GENMASK_ULL(5, 0)
166 #define IE31200_MAD_DIMM_A_RANK BIT(17)
167 #define IE31200_MAD_DIMM_A_RANK_SHIFT 17
168 #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10)
169 #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10
170 #define IE31200_MAD_DIMM_A_WIDTH BIT(19)
171 #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19
172 #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8)
173 #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8
174
175 /* Skylake reports 1GB increments, everything else is 256MB */
176 #define IE31200_PAGES(n, skl) \
177 (n << (28 + (2 * skl) - PAGE_SHIFT))
178
179 static int nr_channels;
180 static struct pci_dev *mci_pdev;
181 static int ie31200_registered = 1;
182
183 struct ie31200_priv {
184 void __iomem *window;
185 void __iomem *c0errlog;
186 void __iomem *c1errlog;
187 };
188
189 enum ie31200_chips {
190 IE31200 = 0,
191 };
192
193 struct ie31200_dev_info {
194 const char *ctl_name;
195 };
196
197 struct ie31200_error_info {
198 u16 errsts;
199 u16 errsts2;
200 u64 eccerrlog[IE31200_CHANNELS];
201 };
202
203 static const struct ie31200_dev_info ie31200_devs[] = {
204 [IE31200] = {
205 .ctl_name = "IE31200"
206 },
207 };
208
209 struct dimm_data {
210 u8 size; /* in multiples of 256MB, except Skylake is 1GB */
211 u8 dual_rank : 1,
212 x16_width : 2; /* 0 means x8 width */
213 };
214
how_many_channels(struct pci_dev * pdev)215 static int how_many_channels(struct pci_dev *pdev)
216 {
217 int n_channels;
218 unsigned char capid0_2b; /* 2nd byte of CAPID0 */
219
220 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
221
222 /* check PDCD: Dual Channel Disable */
223 if (capid0_2b & IE31200_CAPID0_PDCD) {
224 edac_dbg(0, "In single channel mode\n");
225 n_channels = 1;
226 } else {
227 edac_dbg(0, "In dual channel mode\n");
228 n_channels = 2;
229 }
230
231 /* check DDPCD - check if both channels are filled */
232 if (capid0_2b & IE31200_CAPID0_DDPCD)
233 edac_dbg(0, "2 DIMMS per channel disabled\n");
234 else
235 edac_dbg(0, "2 DIMMS per channel enabled\n");
236
237 return n_channels;
238 }
239
ecc_capable(struct pci_dev * pdev)240 static bool ecc_capable(struct pci_dev *pdev)
241 {
242 unsigned char capid0_4b; /* 4th byte of CAPID0 */
243
244 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
245 if (capid0_4b & IE31200_CAPID0_ECC)
246 return false;
247 return true;
248 }
249
eccerrlog_row(u64 log)250 static int eccerrlog_row(u64 log)
251 {
252 return ((log & IE31200_ECCERRLOG_RANK_BITS) >>
253 IE31200_ECCERRLOG_RANK_SHIFT);
254 }
255
ie31200_clear_error_info(struct mem_ctl_info * mci)256 static void ie31200_clear_error_info(struct mem_ctl_info *mci)
257 {
258 /*
259 * Clear any error bits.
260 * (Yes, we really clear bits by writing 1 to them.)
261 */
262 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
263 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
264 }
265
ie31200_get_and_clear_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)266 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
267 struct ie31200_error_info *info)
268 {
269 struct pci_dev *pdev;
270 struct ie31200_priv *priv = mci->pvt_info;
271
272 pdev = to_pci_dev(mci->pdev);
273
274 /*
275 * This is a mess because there is no atomic way to read all the
276 * registers at once and the registers can transition from CE being
277 * overwritten by UE.
278 */
279 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
280 if (!(info->errsts & IE31200_ERRSTS_BITS))
281 return;
282
283 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
284 if (nr_channels == 2)
285 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog);
286
287 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
288
289 /*
290 * If the error is the same for both reads then the first set
291 * of reads is valid. If there is a change then there is a CE
292 * with no info and the second set of reads is valid and
293 * should be UE info.
294 */
295 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
296 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog);
297 if (nr_channels == 2)
298 info->eccerrlog[1] =
299 lo_hi_readq(priv->c1errlog);
300 }
301
302 ie31200_clear_error_info(mci);
303 }
304
ie31200_process_error_info(struct mem_ctl_info * mci,struct ie31200_error_info * info)305 static void ie31200_process_error_info(struct mem_ctl_info *mci,
306 struct ie31200_error_info *info)
307 {
308 int channel;
309 u64 log;
310
311 if (!(info->errsts & IE31200_ERRSTS_BITS))
312 return;
313
314 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
315 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
316 -1, -1, -1, "UE overwrote CE", "");
317 info->errsts = info->errsts2;
318 }
319
320 for (channel = 0; channel < nr_channels; channel++) {
321 log = info->eccerrlog[channel];
322 if (log & IE31200_ECCERRLOG_UE) {
323 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
324 0, 0, 0,
325 eccerrlog_row(log),
326 channel, -1,
327 "ie31200 UE", "");
328 } else if (log & IE31200_ECCERRLOG_CE) {
329 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
330 0, 0,
331 IE31200_ECCERRLOG_SYNDROME(log),
332 eccerrlog_row(log),
333 channel, -1,
334 "ie31200 CE", "");
335 }
336 }
337 }
338
ie31200_check(struct mem_ctl_info * mci)339 static void ie31200_check(struct mem_ctl_info *mci)
340 {
341 struct ie31200_error_info info;
342
343 ie31200_get_and_clear_error_info(mci, &info);
344 ie31200_process_error_info(mci, &info);
345 }
346
ie31200_map_mchbar(struct pci_dev * pdev)347 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
348 {
349 union {
350 u64 mchbar;
351 struct {
352 u32 mchbar_low;
353 u32 mchbar_high;
354 };
355 } u;
356 void __iomem *window;
357
358 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
359 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
360 u.mchbar &= IE31200_MCHBAR_MASK;
361
362 if (u.mchbar != (resource_size_t)u.mchbar) {
363 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
364 (unsigned long long)u.mchbar);
365 return NULL;
366 }
367
368 window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE);
369 if (!window)
370 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
371 (unsigned long long)u.mchbar);
372
373 return window;
374 }
375
__skl_populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)376 static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
377 int chan)
378 {
379 dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE_SKL;
380 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;
381 dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>
382 (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));
383 }
384
__populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan)385 static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode,
386 int chan)
387 {
388 dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE;
389 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0;
390 dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0;
391 }
392
populate_dimm_info(struct dimm_data * dd,u32 addr_decode,int chan,bool skl)393 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan,
394 bool skl)
395 {
396 if (skl)
397 __skl_populate_dimm_info(dd, addr_decode, chan);
398 else
399 __populate_dimm_info(dd, addr_decode, chan);
400 }
401
402
ie31200_probe1(struct pci_dev * pdev,int dev_idx)403 static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
404 {
405 int i, j, ret;
406 struct mem_ctl_info *mci = NULL;
407 struct edac_mc_layer layers[2];
408 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
409 void __iomem *window;
410 struct ie31200_priv *priv;
411 u32 addr_decode, mad_offset;
412
413 /*
414 * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit
415 * this logic when adding new CPU support.
416 */
417 bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device);
418
419 edac_dbg(0, "MC:\n");
420
421 if (!ecc_capable(pdev)) {
422 ie31200_printk(KERN_INFO, "No ECC support\n");
423 return -ENODEV;
424 }
425
426 nr_channels = how_many_channels(pdev);
427 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
428 layers[0].size = IE31200_RANKS_PER_CHANNEL;
429 layers[0].is_virt_csrow = true;
430 layers[1].type = EDAC_MC_LAYER_CHANNEL;
431 layers[1].size = nr_channels;
432 layers[1].is_virt_csrow = false;
433 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
434 sizeof(struct ie31200_priv));
435 if (!mci)
436 return -ENOMEM;
437
438 window = ie31200_map_mchbar(pdev);
439 if (!window) {
440 ret = -ENODEV;
441 goto fail_free;
442 }
443
444 edac_dbg(3, "MC: init mci\n");
445 mci->pdev = &pdev->dev;
446 if (skl)
447 mci->mtype_cap = MEM_FLAG_DDR4;
448 else
449 mci->mtype_cap = MEM_FLAG_DDR3;
450 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
451 mci->edac_cap = EDAC_FLAG_SECDED;
452 mci->mod_name = EDAC_MOD_STR;
453 mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
454 mci->dev_name = pci_name(pdev);
455 mci->edac_check = ie31200_check;
456 mci->ctl_page_to_phys = NULL;
457 priv = mci->pvt_info;
458 priv->window = window;
459 if (skl) {
460 priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL;
461 priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL;
462 mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL;
463 } else {
464 priv->c0errlog = window + IE31200_C0ECCERRLOG;
465 priv->c1errlog = window + IE31200_C1ECCERRLOG;
466 mad_offset = IE31200_MAD_DIMM_0_OFFSET;
467 }
468
469 /* populate DIMM info */
470 for (i = 0; i < IE31200_CHANNELS; i++) {
471 addr_decode = readl(window + mad_offset +
472 (i * 4));
473 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
474 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
475 populate_dimm_info(&dimm_info[i][j], addr_decode, j,
476 skl);
477 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
478 dimm_info[i][j].size,
479 dimm_info[i][j].dual_rank,
480 dimm_info[i][j].x16_width);
481 }
482 }
483
484 /*
485 * The dram rank boundary (DRB) reg values are boundary addresses
486 * for each DRAM rank with a granularity of 64MB. DRB regs are
487 * cumulative; the last one will contain the total memory
488 * contained in all ranks.
489 */
490 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
491 for (j = 0; j < IE31200_CHANNELS; j++) {
492 struct dimm_info *dimm;
493 unsigned long nr_pages;
494
495 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl);
496 if (nr_pages == 0)
497 continue;
498
499 if (dimm_info[j][i].dual_rank) {
500 nr_pages = nr_pages / 2;
501 dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0);
502 dimm->nr_pages = nr_pages;
503 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
504 dimm->grain = 8; /* just a guess */
505 if (skl)
506 dimm->mtype = MEM_DDR4;
507 else
508 dimm->mtype = MEM_DDR3;
509 dimm->dtype = DEV_UNKNOWN;
510 dimm->edac_mode = EDAC_UNKNOWN;
511 }
512 dimm = edac_get_dimm(mci, i * 2, j, 0);
513 dimm->nr_pages = nr_pages;
514 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
515 dimm->grain = 8; /* same guess */
516 if (skl)
517 dimm->mtype = MEM_DDR4;
518 else
519 dimm->mtype = MEM_DDR3;
520 dimm->dtype = DEV_UNKNOWN;
521 dimm->edac_mode = EDAC_UNKNOWN;
522 }
523 }
524
525 ie31200_clear_error_info(mci);
526
527 if (edac_mc_add_mc(mci)) {
528 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
529 ret = -ENODEV;
530 goto fail_unmap;
531 }
532
533 /* get this far and it's successful */
534 edac_dbg(3, "MC: success\n");
535 return 0;
536
537 fail_unmap:
538 iounmap(window);
539
540 fail_free:
541 edac_mc_free(mci);
542
543 return ret;
544 }
545
ie31200_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)546 static int ie31200_init_one(struct pci_dev *pdev,
547 const struct pci_device_id *ent)
548 {
549 int rc;
550
551 edac_dbg(0, "MC:\n");
552 if (pci_enable_device(pdev) < 0)
553 return -EIO;
554 rc = ie31200_probe1(pdev, ent->driver_data);
555 if (rc == 0 && !mci_pdev)
556 mci_pdev = pci_dev_get(pdev);
557
558 return rc;
559 }
560
ie31200_remove_one(struct pci_dev * pdev)561 static void ie31200_remove_one(struct pci_dev *pdev)
562 {
563 struct mem_ctl_info *mci;
564 struct ie31200_priv *priv;
565
566 edac_dbg(0, "\n");
567 pci_dev_put(mci_pdev);
568 mci_pdev = NULL;
569 mci = edac_mc_del_mc(&pdev->dev);
570 if (!mci)
571 return;
572 priv = mci->pvt_info;
573 iounmap(priv->window);
574 edac_mc_free(mci);
575 }
576
577 static const struct pci_device_id ie31200_pci_tbl[] = {
578 { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
579 { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
580 { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
581 { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
582 { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
583 { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
584 { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
585 { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
586 { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
587 { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
588 { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
589 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
590 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
591 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
592 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
593 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
594 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
595 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
596 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
597 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
598 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
599 { 0, } /* 0 terminated list. */
600 };
601 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
602
603 static struct pci_driver ie31200_driver = {
604 .name = EDAC_MOD_STR,
605 .probe = ie31200_init_one,
606 .remove = ie31200_remove_one,
607 .id_table = ie31200_pci_tbl,
608 };
609
ie31200_init(void)610 static int __init ie31200_init(void)
611 {
612 int pci_rc, i;
613
614 edac_dbg(3, "MC:\n");
615 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
616 opstate_init();
617
618 pci_rc = pci_register_driver(&ie31200_driver);
619 if (pci_rc < 0)
620 return pci_rc;
621
622 if (!mci_pdev) {
623 ie31200_registered = 0;
624 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) {
625 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor,
626 ie31200_pci_tbl[i].device,
627 NULL);
628 if (mci_pdev)
629 break;
630 }
631
632 if (!mci_pdev) {
633 edac_dbg(0, "ie31200 pci_get_device fail\n");
634 pci_rc = -ENODEV;
635 goto fail0;
636 }
637
638 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]);
639 if (pci_rc < 0) {
640 edac_dbg(0, "ie31200 init fail\n");
641 pci_rc = -ENODEV;
642 goto fail1;
643 }
644 }
645
646 return 0;
647 fail1:
648 pci_dev_put(mci_pdev);
649 fail0:
650 pci_unregister_driver(&ie31200_driver);
651
652 return pci_rc;
653 }
654
ie31200_exit(void)655 static void __exit ie31200_exit(void)
656 {
657 edac_dbg(3, "MC:\n");
658 pci_unregister_driver(&ie31200_driver);
659 if (!ie31200_registered)
660 ie31200_remove_one(mci_pdev);
661 }
662
663 module_init(ie31200_init);
664 module_exit(ie31200_exit);
665
666 MODULE_LICENSE("GPL");
667 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
668 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
669