xref: /openbmc/u-boot/arch/nds32/include/asm/cache.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (C) 2011 Andes Technology Corporation
4  * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
5  * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
6  */
7 
8 #ifndef _ASM_CACHE_H
9 #define _ASM_CACHE_H
10 
11 /* cache */
12 int	icache_status(void);
13 void	icache_enable(void);
14 void	icache_disable(void);
15 int	dcache_status(void);
16 void	dcache_enable(void);
17 void	dcache_disable(void);
18 void cache_flush(void);
19 
20 #define DEFINE_GET_SYS_REG(reg) \
21 	static inline unsigned long GET_##reg(void)		\
22 	{							\
23 		unsigned long val;				\
24 		__asm__ volatile (				\
25 		"mfsr %0, $"#reg : "=&r" (val) : : "memory"	\
26 		);						\
27 		return val;					\
28 	}
29 
30 enum cache_t {ICACHE, DCACHE};
31 DEFINE_GET_SYS_REG(ICM_CFG);
32 DEFINE_GET_SYS_REG(DCM_CFG);
33 /* I-cache sets (# of cache lines) per way */
34 #define ICM_CFG_OFF_ISET	0
35 /* I-cache ways */
36 #define ICM_CFG_OFF_IWAY	3
37 #define ICM_CFG_MSK_ISET	(0x7 << ICM_CFG_OFF_ISET)
38 #define ICM_CFG_MSK_IWAY	(0x7 << ICM_CFG_OFF_IWAY)
39 /* D-cache sets (# of cache lines) per way */
40 #define DCM_CFG_OFF_DSET	0
41 /* D-cache ways */
42 #define DCM_CFG_OFF_DWAY	3
43 #define DCM_CFG_MSK_DSET	(0x7 << DCM_CFG_OFF_DSET)
44 #define DCM_CFG_MSK_DWAY	(0x7 << DCM_CFG_OFF_DWAY)
45 /* I-cache line size */
46 #define ICM_CFG_OFF_ISZ	6
47 #define ICM_CFG_MSK_ISZ		(0x7UL << ICM_CFG_OFF_ISZ)
48 /* D-cache line size */
49 #define DCM_CFG_OFF_DSZ	6
50 #define DCM_CFG_MSK_DSZ		(0x7UL << DCM_CFG_OFF_DSZ)
51 
52 /*
53  * The current upper bound for NDS32 L1 data cache line sizes is 32 bytes.
54  * We use that value for aligning DMA buffers unless the board config has
55  * specified an alternate cache line size.
56  */
57 #ifdef CONFIG_SYS_CACHELINE_SIZE
58 #define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
59 #else
60 #define ARCH_DMA_MINALIGN	32
61 #endif
62 
63 #endif /* _ASM_CACHE_H */
64