1 #ifndef __ASM_PPC_PROCESSOR_H
2 #define __ASM_PPC_PROCESSOR_H
3
4 /*
5 * Default implementation of macro that returns current
6 * instruction pointer ("program counter").
7 */
8 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
9
10 #include <asm/ptrace.h>
11 #include <asm/types.h>
12
13 /* Machine State Register (MSR) Fields */
14
15 #ifdef CONFIG_PPC64BRIDGE
16 #define MSR_SF (1<<63)
17 #define MSR_ISF (1<<61)
18 #endif /* CONFIG_PPC64BRIDGE */
19 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
20 #define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */
21 #define MSR_SPE (1<<25) /* Enable SPE(e500) */
22 #define MSR_POW (1<<18) /* Enable Power Management */
23 #define MSR_WE (1<<18) /* Wait State Enable */
24 #define MSR_TGPR (1<<17) /* TLB Update registers in use */
25 #define MSR_CE (1<<17) /* Critical Interrupt Enable */
26 #define MSR_ILE (1<<16) /* Interrupt Little Endian */
27 #define MSR_EE (1<<15) /* External Interrupt Enable */
28 #define MSR_PR (1<<14) /* Problem State / Privilege Level */
29 #define MSR_FP (1<<13) /* Floating Point enable */
30 #define MSR_ME (1<<12) /* Machine Check Enable */
31 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
32 #define MSR_SE (1<<10) /* Single Step */
33 #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
34 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
35 #define MSR_BE (1<<9) /* Branch Trace */
36 #define MSR_DE (1<<9) /* Debug Exception Enable */
37 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
38 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
39 #define MSR_IR (1<<5) /* Instruction Relocate */
40 #define MSR_IS (1<<5) /* Book E Instruction space */
41 #define MSR_DR (1<<4) /* Data Relocate */
42 #define MSR_DS (1<<4) /* Book E Data space */
43 #define MSR_PE (1<<3) /* Protection Enable */
44 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
45 #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
46 #define MSR_RI (1<<1) /* Recoverable Exception */
47 #define MSR_LE (1<<0) /* Little Endian */
48
49 #ifdef CONFIG_APUS_FAST_EXCEPT
50 #define MSR_ MSR_ME|MSR_IP|MSR_RI
51 #else
52 #define MSR_ MSR_ME|MSR_RI
53 #endif
54 #ifndef CONFIG_E500
55 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR
56 #else
57 #define MSR_KERNEL MSR_ME
58 #endif
59
60 /* Floating Point Status and Control Register (FPSCR) Fields */
61
62 #define FPSCR_FX 0x80000000 /* FPU exception summary */
63 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
64 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
65 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
66 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
68 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
69 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
70 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
71 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
72 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
73 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
74 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
75 #define FPSCR_FR 0x00040000 /* Fraction rounded */
76 #define FPSCR_FI 0x00020000 /* Fraction inexact */
77 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
78 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
79 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
80 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
81 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
82 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
83 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
84 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
85 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
86 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
87 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
88 #define FPSCR_RN 0x00000003 /* FPU rounding control */
89
90 /* Special Purpose Registers (SPRNs)*/
91
92 #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
93 #ifdef CONFIG_BOOKE
94 #define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */
95 #endif
96 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
97 #define SPRN_CTR 0x009 /* Count Register */
98 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
99 #ifndef CONFIG_BOOKE
100 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
101 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
102 #else
103 #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
104 #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
105 #endif /* CONFIG_BOOKE */
106 #define SPRN_DAR 0x013 /* Data Address Register */
107 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
108 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
109 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
110 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
111 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
112 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
113 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
114 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
115 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
116 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
117 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
118 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
119 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
120 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
121 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
122 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */
123 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
124 #define DBCR_EDM 0x80000000
125 #define DBCR_IDM 0x40000000
126 #define DBCR_RST(x) (((x) & 0x3) << 28)
127 #define DBCR_RST_NONE 0
128 #define DBCR_RST_CORE 1
129 #define DBCR_RST_CHIP 2
130 #define DBCR_RST_SYSTEM 3
131 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
132 #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
133 #define DBCR_EDE 0x02000000 /* Exception Debug Event */
134 #define DBCR_TDE 0x01000000 /* TRAP Debug Event */
135 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
136 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
137 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
138 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
139 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
140 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
141 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
142 #define DAC_BYTE 0
143 #define DAC_HALF 1
144 #define DAC_WORD 2
145 #define DAC_QUAD 3
146 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
147 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
148 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
149 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
150 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
151 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
152 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
153 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
154 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
155 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
156 #ifndef CONFIG_BOOKE
157 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
158 #else
159 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
160 #endif /* CONFIG_BOOKE */
161 #ifndef CONFIG_BOOKE
162 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
163 #define SPRN_DBSR 0x3F0 /* Debug Status Register */
164 #else
165 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
166 #ifdef CONFIG_BOOKE
167 #define SPRN_DBDR 0x3f3 /* Debug Data Register */
168 #endif
169 #define SPRN_DBSR 0x130 /* Book E Debug Status Register */
170 #define DBSR_IC 0x08000000 /* Book E Instruction Completion */
171 #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
172 #endif /* CONFIG_BOOKE */
173 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
174 #define DCCR_NOCACHE 0 /* Noncacheable */
175 #define DCCR_CACHE 1 /* Cacheable */
176 #ifndef CONFIG_BOOKE
177 #define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */
178 #define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */
179 #endif
180 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
181 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
182 #define DCWR_COPY 0 /* Copy-back */
183 #define DCWR_WRITE 1 /* Write-through */
184 #ifndef CONFIG_BOOKE
185 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
186 #else
187 #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
188 #endif /* CONFIG_BOOKE */
189 #define SPRN_DEC 0x016 /* Decrement Register */
190 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
191 #ifdef CONFIG_BOOKE
192 #define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */
193 #define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */
194 #define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */
195 #define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */
196 #endif
197 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
198 #ifdef CONFIG_BOOKE
199 #define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */
200 #define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */
201 #define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */
202 #define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */
203 #define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */
204 #endif
205 #define SPRN_EAR 0x11A /* External Address Register */
206 #ifndef CONFIG_BOOKE
207 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
208 #else
209 #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
210 #endif /* CONFIG_BOOKE */
211 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
212 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
213 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
214 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
215 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
216 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
217 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
218 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
219 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
220 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
221 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
222 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
223 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
224
225 #define HID0_ICE_SHIFT 15
226 #define HID0_DCE_SHIFT 14
227 #define HID0_DLOCK_SHIFT 12
228
229 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
230 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
231 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
232 #define HID0_SBCLK (1<<27)
233 #define HID0_EICE (1<<26)
234 #define HID0_ECLK (1<<25)
235 #define HID0_PAR (1<<24)
236 #define HID0_DOZE (1<<23)
237 #define HID0_NAP (1<<22)
238 #define HID0_SLEEP (1<<21)
239 #define HID0_DPM (1<<20)
240 #define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
241 #define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
242 #define HID0_TBEN (1<<14) /* Time Base Enable */
243 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
244 #define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
245 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
246 #define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
247 #define HID0_DCI HID0_DCFI
248 #define HID0_SPD (1<<9) /* Speculative disable */
249 #define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
250 #define HID0_SGE (1<<7) /* Store Gathering Enable */
251 #define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
252 #define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
253 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
254 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
255 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
256 #define HID0_BTCD (1<<1) /* Branch target cache disable */
257 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
258 #define HID1_RFXE (1<<17) /* Read Fault Exception Enable */
259 #define HID1_ASTME (1<<13) /* Address bus streaming mode */
260 #define HID1_ABE (1<<12) /* Address broadcast enable */
261 #define HID1_MBDD (1<<6) /* optimized sync instruction */
262 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
263 #ifndef CONFIG_BOOKE
264 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
265 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
266 #else
267 #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
268 #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
269 #endif /* CONFIG_BOOKE */
270 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
271 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
272 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
273 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
274 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
275 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
276 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
277 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
278 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
279 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
280 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
281 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
282 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
283 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
284 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
285 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
286 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
287 #define ICCR_NOCACHE 0 /* Noncacheable */
288 #define ICCR_CACHE 1 /* Cacheable */
289 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
290 #ifdef CONFIG_BOOKE
291 #define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */
292 #define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */
293 #endif
294 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
295 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
296 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
297 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
298 #ifdef CONFIG_BOOKE
299 #define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */
300 #define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */
301 #define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */
302 #define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */
303 #define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */
304 #define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */
305 #define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */
306 #define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */
307 #define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */
308 #endif
309 #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
310 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
311 #define SPRN_LR 0x008 /* Link Register */
312 #define SPRN_MBAR 0x137 /* System memory base address */
313 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
314 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
315 #ifdef CONFIG_BOOKE
316 #define SPRN_MMUCR 0x3b2 /* MMU Control Register */
317 #endif
318 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
319 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
320 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
321 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
322 #ifndef CONFIG_BOOKE
323 #define SPRN_PID 0x3B1 /* Process ID */
324 #define SPRN_PIR 0x3FF /* Processor Identification Register */
325 #else
326 #define SPRN_PID 0x030 /* Book E Process ID */
327 #define SPRN_PIR 0x11E /* Book E Processor Identification Register */
328 #endif /* CONFIG_BOOKE */
329 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
330 #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
331 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
332 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
333 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
334 #define SPRN_PVR 0x11F /* Processor Version Register */
335 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
336 #ifdef CONFIG_BOOKE
337 #define SPRN_RSTCFG 0x39b /* Reset Configuration */
338 #endif
339 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
340 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
341 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
342 #define SGR_NORMAL 0
343 #define SGR_GUARDED 1
344 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
345 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
346 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
347 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
348 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
349 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
350 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
351 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
352 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
353 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
354 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
355 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
356 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
357
358 #ifdef CONFIG_BOOKE
359 #define SPRN_SVR 0x3FF /* System Version Register */
360 #else
361 #define SPRN_SVR 0x11E /* System Version Register */
362 #endif
363 #define SPRN_TBHI 0x3DC /* Time Base High */
364 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
365 #define SPRN_TBLO 0x3DD /* Time Base Low */
366 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
367 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register */
368 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register */
369 #define SPRN_TBWL 0x11C /* Time Base Write Lower Register */
370 #define SPRN_TBWU 0x11D /* Time Base Write Upper Register */
371 #ifndef CONFIG_BOOKE
372 #define SPRN_TCR 0x3DA /* Timer Control Register */
373 #else
374 #define SPRN_TCR 0x154 /* Book E Timer Control Register */
375 #endif /* CONFIG_BOOKE */
376 #ifdef CONFIG_E500MC
377 #define TCR_WP(x) (((64-x)&0x3)<<30)| \
378 (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
379 #else
380 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
381 #define WP_2_17 0 /* 2^17 clocks */
382 #define WP_2_21 1 /* 2^21 clocks */
383 #define WP_2_25 2 /* 2^25 clocks */
384 #define WP_2_29 3 /* 2^29 clocks */
385 #endif /* CONFIG_E500 */
386 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
387 #define WRC_NONE 0 /* No reset will occur */
388 #define WRC_CORE 1 /* Core reset will occur */
389 #define WRC_CHIP 2 /* Chip reset will occur */
390 #define WRC_SYSTEM 3 /* System reset will occur */
391 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
392 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
393 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
394 #define FP_2_9 0 /* 2^9 clocks */
395 #define FP_2_13 1 /* 2^13 clocks */
396 #define FP_2_17 2 /* 2^17 clocks */
397 #define FP_2_21 3 /* 2^21 clocks */
398 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
399 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
400 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
401 #define THRM1_TIN (1<<0)
402 #define THRM1_TIV (1<<1)
403 #define THRM1_THRES (0x7f<<2)
404 #define THRM1_TID (1<<29)
405 #define THRM1_TIE (1<<30)
406 #define THRM1_V (1<<31)
407 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
408 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
409 #define THRM3_E (1<<31)
410 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
411 #ifndef CONFIG_BOOKE
412 #define SPRN_TSR 0x3D8 /* Timer Status Register */
413 #else
414 #define SPRN_TSR 0x150 /* Book E Timer Status Register */
415 #endif /* CONFIG_BOOKE */
416 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
417 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
418 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
419 #define WRS_NONE 0 /* No WDT reset occurred */
420 #define WRS_CORE 1 /* WDT forced core reset */
421 #define WRS_CHIP 2 /* WDT forced chip reset */
422 #define WRS_SYSTEM 3 /* WDT forced system reset */
423 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
424 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
425 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
426 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
427 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
428 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
429 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
430 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
431 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
432 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
433 #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
434
435 /* Book E definitions */
436 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
437 #define SPRN_CSRR0 0x03A /* Critical SRR0 */
438 #define SPRN_CSRR1 0x03B /* Critical SRR0 */
439 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
440 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
441 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
442 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
443 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
444 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
445 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
446 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
447 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
448 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
449 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
450 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
451 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
452 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
453 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
454 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
455 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
456 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
457 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
458 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
459 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
460 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
461 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
462 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
463 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
464 #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
465 #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
466 #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
467 #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
468 #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
469 #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
470 #define SPRN_IVOR38 0x1b0 /* Interrupt Vector Offset Register 38 */
471 #define SPRN_IVOR39 0x1b1 /* Interrupt Vector Offset Register 39 */
472 #define SPRN_IVOR40 0x1b2 /* Interrupt Vector Offset Register 40 */
473 #define SPRN_IVOR41 0x1b3 /* Interrupt Vector Offset Register 41 */
474 #define SPRN_GIVOR2 0x1b8 /* Guest Interrupt Vector Offset Register 2 */
475 #define SPRN_GIVOR3 0x1b9 /* Guest Interrupt Vector Offset Register 3 */
476 #define SPRN_GIVOR4 0x1ba /* Guest Interrupt Vector Offset Register 4 */
477 #define SPRN_GIVOR8 0x1bb /* Guest Interrupt Vector Offset Register 8 */
478 #define SPRN_GIVOR13 0x1bc /* Guest Interrupt Vector Offset Register 13 */
479 #define SPRN_GIVOR14 0x1bd /* Guest Interrupt Vector Offset Register 14 */
480
481 /* e500 definitions */
482 #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */
483 #define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */
484 #define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */
485 #define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */
486 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
487 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
488 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
489 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
490 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
491 #define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */
492 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
493 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
494 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
495 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
496 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
497 #define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */
498 #define L1CSR2_DCWS 0x40000000 /* Data Cache Write Shadow */
499 #define L1CSR2_DCSTASHID 0x000003ff /* Data Cache Stash ID */
500 #define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */
501 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
502 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */
503 #define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */
504 #define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */
505 #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */
506 #define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */
507 #define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */
508 #define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */
509
510 /* e6500 */
511 #define L2CSR0_L2REP_SPLRUAGE 0x00000000 /* L2REP Streaming PLRU with Aging */
512 #define L2CSR0_L2REP_FIFO 0x00001000 /* L2REP FIFO */
513 #define L2CSR0_L2REP_SPLRU 0x00002000 /* L2REP Streaming PLRU */
514 #define L2CSR0_L2REP_PLRU 0x00003000 /* L2REP PLRU */
515
516 #define L2CSR0_L2REP_MODE L2CSR0_L2REP_SPLRUAGE
517
518 #define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */
519 #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */
520 #define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */
521 #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */
522 #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */
523
524 #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
525 #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
526 #define TLBnCFG_NENTRY_MASK 0x00000fff
527 #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */
528 #define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */
529 #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */
530 #define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
531 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
532 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
533 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
534 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
535 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
536 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
537 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
538 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
539 #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
540 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
541 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
542 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
543
544 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
545 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
546 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
547 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
548 #define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
549 #define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
550 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
551
552 #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */
553 #define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */
554 #define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */
555 #define BUCSR_STAC_EN 0x01000000 /* Segment target addr cache enable */
556 #define BUCSR_LS_EN 0x00400000 /* Link stack enable */
557 #define BUCSR_BBFI 0x00000200 /* Branch buffer flash invalidate */
558 #define BUCSR_BPEN 0x00000001 /* Branch prediction enable */
559 #define BUCSR_ENABLE (BUCSR_STAC_EN|BUCSR_LS_EN|BUCSR_BBFI|BUCSR_BPEN)
560 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
561 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
562 #define SPRN_PID1 0x279 /* Process ID Register 1 */
563 #define SPRN_PID2 0x27a /* Process ID Register 2 */
564 #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
565 #define SPRN_MCAR 0x23d /* Machine Check Address register */
566 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
567 #define MCSR_IB 0x40000000 /* Instruction PLB Error */
568 #define MCSR_DB 0x20000000 /* Data PLB Error */
569 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */
570 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
571 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
572 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
573 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
574 #define ESR_ST 0x00800000 /* Store Operation */
575
576 #if defined(CONFIG_MPC86xx)
577 #define SPRN_MSSCR0 0x3f6
578 #define SPRN_MSSSR0 0x3f7
579 #endif
580
581 #define SPRN_HDBCR0 0x3d0
582 #define SPRN_HDBCR1 0x3d1
583 #define SPRN_HDBCR2 0x3d2
584 #define SPRN_HDBCR3 0x3d3
585 #define SPRN_HDBCR4 0x3d4
586 #define SPRN_HDBCR5 0x3d5
587 #define SPRN_HDBCR6 0x3d6
588 #define SPRN_HDBCR7 0x277
589 #define SPRN_HDBCR8 0x278
590
591 /* Short-hand versions for a number of the above SPRNs */
592
593 #define CTR SPRN_CTR /* Counter Register */
594 #define DAR SPRN_DAR /* Data Address Register */
595 #define DABR SPRN_DABR /* Data Address Breakpoint Register */
596 #define DAC1 SPRN_DAC1 /* Data Address Register 1 */
597 #define DAC2 SPRN_DAC2 /* Data Address Register 2 */
598 #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
599 #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
600 #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
601 #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
602 #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
603 #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
604 #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
605 #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
606 #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
607 #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
608 #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
609 #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
610 #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
611 #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
612 #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
613 #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
614 #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
615 #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
616 #define DBSR SPRN_DBSR /* Debug Status Register */
617 #define DCMP SPRN_DCMP /* Data TLB Compare Register */
618 #define DEC SPRN_DEC /* Decrement Register */
619 #define DMISS SPRN_DMISS /* Data TLB Miss Register */
620 #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
621 #define EAR SPRN_EAR /* External Address Register */
622 #define ESR SPRN_ESR /* Exception Syndrome Register */
623 #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
624 #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
625 #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
626 #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
627 #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
628 #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
629 #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
630 #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
631 #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
632 #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
633 #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
634 #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
635 #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
636 #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
637 #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
638 #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
639 #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
640 #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
641 #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
642 #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
643 #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
644 #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
645 #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
646 #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
647 #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
648 #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
649 #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
650 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
651 #define LR SPRN_LR
652 #define MBAR SPRN_MBAR /* System memory base address */
653 #if defined(CONFIG_MPC86xx)
654 #define MSSCR0 SPRN_MSSCR0
655 #endif
656 #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
657 #define PIR SPRN_PIR
658 #endif
659 #define SVR SPRN_SVR /* System-On-Chip Version Register */
660 #define PVR SPRN_PVR /* Processor Version */
661 #define RPA SPRN_RPA /* Required Physical Address Register */
662 #define SDR1 SPRN_SDR1 /* MMU hash base register */
663 #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
664 #define SPR1 SPRN_SPRG1
665 #define SPR2 SPRN_SPRG2
666 #define SPR3 SPRN_SPRG3
667 #define SPRG0 SPRN_SPRG0
668 #define SPRG1 SPRN_SPRG1
669 #define SPRG2 SPRN_SPRG2
670 #define SPRG3 SPRN_SPRG3
671 #define SPRG4 SPRN_SPRG4
672 #define SPRG5 SPRN_SPRG5
673 #define SPRG6 SPRN_SPRG6
674 #define SPRG7 SPRN_SPRG7
675 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
676 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
677 #define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */
678 #define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */
679 #define SVR SPRN_SVR /* System Version Register */
680 #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
681 #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
682 #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
683 #define TBWU SPRN_TBWU /* Time Base Write Upper Register */
684 #define TCR SPRN_TCR /* Timer Control Register */
685 #define TSR SPRN_TSR /* Timer Status Register */
686 #define ICTC 1019
687 #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
688 #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
689 #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
690 #define XER SPRN_XER
691
692 #define DECAR SPRN_DECAR
693 #define CSRR0 SPRN_CSRR0
694 #define CSRR1 SPRN_CSRR1
695 #define IVPR SPRN_IVPR
696 #define USPRG0 SPRN_USPRG
697 #define SPRG4R SPRN_SPRG4R
698 #define SPRG5R SPRN_SPRG5R
699 #define SPRG6R SPRN_SPRG6R
700 #define SPRG7R SPRN_SPRG7R
701 #define SPRG4W SPRN_SPRG4W
702 #define SPRG5W SPRN_SPRG5W
703 #define SPRG6W SPRN_SPRG6W
704 #define SPRG7W SPRN_SPRG7W
705 #define DEAR SPRN_DEAR
706 #define DBCR2 SPRN_DBCR2
707 #define IAC3 SPRN_IAC3
708 #define IAC4 SPRN_IAC4
709 #define DVC1 SPRN_DVC1
710 #define DVC2 SPRN_DVC2
711 #define IVOR0 SPRN_IVOR0
712 #define IVOR1 SPRN_IVOR1
713 #define IVOR2 SPRN_IVOR2
714 #define IVOR3 SPRN_IVOR3
715 #define IVOR4 SPRN_IVOR4
716 #define IVOR5 SPRN_IVOR5
717 #define IVOR6 SPRN_IVOR6
718 #define IVOR7 SPRN_IVOR7
719 #define IVOR8 SPRN_IVOR8
720 #define IVOR9 SPRN_IVOR9
721 #define IVOR10 SPRN_IVOR10
722 #define IVOR11 SPRN_IVOR11
723 #define IVOR12 SPRN_IVOR12
724 #define IVOR13 SPRN_IVOR13
725 #define IVOR14 SPRN_IVOR14
726 #define IVOR15 SPRN_IVOR15
727 #define IVOR32 SPRN_IVOR32
728 #define IVOR33 SPRN_IVOR33
729 #define IVOR34 SPRN_IVOR34
730 #define IVOR35 SPRN_IVOR35
731 #define MCSRR0 SPRN_MCSRR0
732 #define MCSRR1 SPRN_MCSRR1
733 #define L1CSR0 SPRN_L1CSR0
734 #define L1CSR1 SPRN_L1CSR1
735 #define L1CSR2 SPRN_L1CSR2
736 #define L1CFG0 SPRN_L1CFG0
737 #define L1CFG1 SPRN_L1CFG1
738 #define L2CFG0 SPRN_L2CFG0
739 #define L2CSR0 SPRN_L2CSR0
740 #define L2CSR1 SPRN_L2CSR1
741 #define MCSR SPRN_MCSR
742 #define MMUCSR0 SPRN_MMUCSR0
743 #define BUCSR SPRN_BUCSR
744 #define PID0 SPRN_PID
745 #define PID1 SPRN_PID1
746 #define PID2 SPRN_PID2
747 #define MAS0 SPRN_MAS0
748 #define MAS1 SPRN_MAS1
749 #define MAS2 SPRN_MAS2
750 #define MAS3 SPRN_MAS3
751 #define MAS4 SPRN_MAS4
752 #define MAS5 SPRN_MAS5
753 #define MAS6 SPRN_MAS6
754 #define MAS7 SPRN_MAS7
755 #define MAS8 SPRN_MAS8
756
757 #if defined(CONFIG_MPC85xx)
758 #define DAR_DEAR DEAR
759 #else
760 #define DAR_DEAR DAR
761 #endif
762
763 /* Device Control Registers */
764
765 #define DCRN_BEAR 0x090 /* Bus Error Address Register */
766 #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
767 #define BESR_DSES 0x80000000 /* Data-Side Error Status */
768 #define BESR_DMES 0x40000000 /* DMA Error Status */
769 #define BESR_RWS 0x20000000 /* Read/Write Status */
770 #define BESR_ETMASK 0x1C000000 /* Error Type */
771 #define ET_PROT 0
772 #define ET_PARITY 1
773 #define ET_NCFG 2
774 #define ET_BUSERR 4
775 #define ET_BUSTO 6
776 #define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */
777 #define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */
778 #define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */
779 #define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */
780 #define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */
781 #define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */
782 #define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */
783 #define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */
784 #define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */
785 #define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */
786 #define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */
787 #define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */
788 #define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */
789 #define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */
790 #define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */
791 #define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */
792 #define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */
793 #define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */
794 #define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */
795 #define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */
796 #define DCRN_DMASR 0x0E0 /* DMA Status Register */
797 #define DCRN_EXIER 0x042 /* External Interrupt Enable Register */
798 #define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
799 #define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
800 #define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
801 #define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
802 #define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
803 #define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
804 #define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
805 #define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
806 #define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
807 #define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
808 #define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
809 #define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
810 #define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
811 #define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
812 #define DCRN_EXISR 0x040 /* External Interrupt Status Register */
813 #define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */
814 #define IOCR_E0TE 0x80000000
815 #define IOCR_E0LP 0x40000000
816 #define IOCR_E1TE 0x20000000
817 #define IOCR_E1LP 0x10000000
818 #define IOCR_E2TE 0x08000000
819 #define IOCR_E2LP 0x04000000
820 #define IOCR_E3TE 0x02000000
821 #define IOCR_E3LP 0x01000000
822 #define IOCR_E4TE 0x00800000
823 #define IOCR_E4LP 0x00400000
824 #define IOCR_EDT 0x00080000
825 #define IOCR_SOR 0x00040000
826 #define IOCR_EDO 0x00008000
827 #define IOCR_2XC 0x00004000
828 #define IOCR_ATC 0x00002000
829 #define IOCR_SPD 0x00001000
830 #define IOCR_BEM 0x00000800
831 #define IOCR_PTD 0x00000400
832 #define IOCR_ARE 0x00000080
833 #define IOCR_DRC 0x00000020
834 #define IOCR_RDM(x) (((x) & 0x3) << 3)
835 #define IOCR_TCS 0x00000004
836 #define IOCR_SCS 0x00000002
837 #define IOCR_SPC 0x00000001
838
839 /* System-On-Chip Version Register */
840
841 /* System-On-Chip Version Register (SVR) field extraction */
842
843 #define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */
844 #define SVR_REV(svr) (((svr) >> 0) & 0xFF) /* Revision field */
845
846 #define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */
847 #define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */
848 #define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */
849 #define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */
850 #define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */
851 #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */
852 #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */
853
854 /* Processor Version Register */
855
856 /* Processor Version Register (PVR) field extraction */
857
858 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
859 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
860
861 /*
862 * AMCC has further subdivided the standard PowerPC 16-bit version and
863 * revision subfields of the PVR for the PowerPC 403s into the following:
864 */
865
866 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
867 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
868 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
869 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
870 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
871 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
872
873 /* e600 core PVR fields */
874
875 #define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */
876 #define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */
877 #define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */
878 #define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */
879
880 /* Processor Version Numbers */
881
882 #define PVR_403GA 0x00200000
883 #define PVR_403GB 0x00200100
884 #define PVR_403GC 0x00200200
885 #define PVR_403GCX 0x00201400
886 #define PVR_405GP 0x40110000
887 #define PVR_405GP_RB 0x40110040
888 #define PVR_405GP_RC 0x40110082
889 #define PVR_405GP_RD 0x401100C4
890 #define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */
891 #define PVR_405EP_RA 0x51210950
892 #define PVR_405GPR_RB 0x50910951
893 #define PVR_405EZ_RA 0x41511460
894 #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */
895 #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */
896 #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */
897 #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */
898 #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */
899 #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */
900 #define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */
901 #define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */
902 #define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */
903 #define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */
904 #define PVR_440GP_RB 0x40120440
905 #define PVR_440GP_RC 0x40120481
906 #define PVR_440EP_RA 0x42221850
907 #define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
908 #define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
909 #define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */
910 #define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */
911 #define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */
912 #define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */
913 #define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */
914 #define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */
915 #define PVR_440GX_RA 0x51B21850
916 #define PVR_440GX_RB 0x51B21851
917 #define PVR_440GX_RC 0x51B21892
918 #define PVR_440GX_RF 0x51B21894
919 #define PVR_405EP_RB 0x51210950
920 #define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */
921 #define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */
922 #define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */
923 #define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */
924 #define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */
925 #define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */
926 #define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */
927 #define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */
928 #define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */
929 #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */
930 #define PVR_460EX_RB 0x130218A4 /* 460EX rev B with and without Sec Eng*/
931 #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */
932 #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */
933 #define PVR_460GT_RB 0x130218A5 /* 460GT rev B with and without Sec Eng*/
934 #define PVR_460SX_RA 0x13541800 /* 460SX rev A */
935 #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */
936 #define PVR_460GX_RA 0x13541802 /* 460GX rev A */
937 #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */
938 #define PVR_APM821XX_RA 0x12C41C80 /* APM821XX rev A */
939 #define PVR_601 0x00010000
940 #define PVR_602 0x00050000
941 #define PVR_603 0x00030000
942 #define PVR_603e 0x00060000
943 #define PVR_603ev 0x00070000
944 #define PVR_603r 0x00071000
945 #define PVR_604 0x00040000
946 #define PVR_604e 0x00090000
947 #define PVR_604r 0x000A0000
948 #define PVR_620 0x00140000
949 #define PVR_740 0x00080000
950 #define PVR_750 PVR_740
951 #define PVR_740P 0x10080000
952 #define PVR_750P PVR_740P
953 #define PVR_7400 0x000C0000
954 #define PVR_7410 0x800C0000
955 #define PVR_7450 0x80000000
956
957 #define PVR_85xx 0x80200000
958 #define PVR_85xx_REV1 (PVR_85xx | 0x0010)
959 #define PVR_85xx_REV2 (PVR_85xx | 0x0020)
960 #define PVR_VER_E500_V1 0x8020
961 #define PVR_VER_E500_V2 0x8021
962 #define PVR_VER_E500MC 0x8023
963 #define PVR_VER_E5500 0x8024
964 #define PVR_VER_E6500 0x8040
965
966 #define PVR_86xx 0x80040000
967
968 #define PVR_VIRTEX5 0x7ff21912
969
970 /*
971 * For the 8xx processors, all of them report the same PVR family for
972 * the PowerPC core. The various versions of these processors must be
973 * differentiated by the version number in the Communication Processor
974 * Module (CPM).
975 */
976 #define PVR_8xx 0x00500000
977
978 #define PVR_7400 0x000C0000
979
980 /*
981 * MPC 52xx
982 */
983 #define PVR_5200 0x80822011
984 #define PVR_5200B 0x80822014
985
986 /*
987 * 405EX/EXr CHIP_21 Errata
988 */
989 #ifdef CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
990 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
991 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX1_RC
992 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX1_RD
993 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x0
994 #endif
995
996 #ifdef CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY
997 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
998 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EX2_RC
999 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EX2_RD
1000 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x1
1001 #endif
1002
1003 #ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY
1004 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
1005 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR1_RC
1006 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR1_RD
1007 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x2
1008 #endif
1009
1010 #ifdef CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY
1011 #define CONFIG_SYS_4xx_CHIP_21_ERRATA
1012 #define CONFIG_405EX_CHIP21_PVR_REV_C PVR_405EXR2_RC
1013 #define CONFIG_405EX_CHIP21_PVR_REV_D PVR_405EXR2_RD
1014 #define CONFIG_405EX_CHIP21_ECID3_REV_D 0x3
1015 #endif
1016
1017 /*
1018 * System Version Register
1019 */
1020
1021 /* System Version Register (SVR) field extraction */
1022
1023 #define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */
1024
1025 #define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */
1026 #define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */
1027
1028 #ifdef CONFIG_ARCH_MPC8536
1029 #define SVR_MAJ(svr) (((svr) >> 4) & 0x7) /* Major revision field*/
1030 #else
1031 #define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/
1032 #endif
1033 #define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/
1034
1035 /* Some parts define SVR[0:23] as the SOC version */
1036 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFF7FF) /* SOC w/o E bit*/
1037
1038 /* whether MPC8xxxE (i.e. has SEC) */
1039 #if defined(CONFIG_MPC85xx)
1040 #define IS_E_PROCESSOR(svr) (svr & 0x80000)
1041 #else
1042 #if defined(CONFIG_MPC83xx)
1043 #define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
1044 #endif
1045 #endif
1046
1047 #define IS_SVR_REV(svr, maj, min) \
1048 ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
1049
1050 /*
1051 * SVR_SOC_VER() Version Values
1052 */
1053
1054 #define SVR_8533 0x803400
1055 #define SVR_8535 0x803701
1056 #define SVR_8536 0x803700
1057 #define SVR_8540 0x803000
1058 #define SVR_8541 0x807200
1059 #define SVR_8543 0x803200
1060 #define SVR_8544 0x803401
1061 #define SVR_8545 0x803102
1062 #define SVR_8547 0x803101
1063 #define SVR_8548 0x803100
1064 #define SVR_8555 0x807100
1065 #define SVR_8560 0x807000
1066 #define SVR_8567 0x807501
1067 #define SVR_8568 0x807500
1068 #define SVR_8569 0x808000
1069 #define SVR_8572 0x80E000
1070 #define SVR_P1010 0x80F100
1071 #define SVR_P1011 0x80E500
1072 #define SVR_P1012 0x80E501
1073 #define SVR_P1013 0x80E700
1074 #define SVR_P1014 0x80F101
1075 #define SVR_P1017 0x80F700
1076 #define SVR_P1020 0x80E400
1077 #define SVR_P1021 0x80E401
1078 #define SVR_P1022 0x80E600
1079 #define SVR_P1023 0x80F600
1080 #define SVR_P1024 0x80E402
1081 #define SVR_P1025 0x80E403
1082 #define SVR_P2010 0x80E300
1083 #define SVR_P2020 0x80E200
1084 #define SVR_P2040 0x821000
1085 #define SVR_P2041 0x821001
1086 #define SVR_P3041 0x821103
1087 #define SVR_P4040 0x820100
1088 #define SVR_P4080 0x820000
1089 #define SVR_P5010 0x822100
1090 #define SVR_P5020 0x822000
1091 #define SVR_P5021 0X820500
1092 #define SVR_P5040 0x820400
1093 #define SVR_T4240 0x824000
1094 #define SVR_T4120 0x824001
1095 #define SVR_T4160 0x824100
1096 #define SVR_T4080 0x824102
1097 #define SVR_C291 0x850000
1098 #define SVR_C292 0x850020
1099 #define SVR_C293 0x850030
1100 #define SVR_B4860 0X868000
1101 #define SVR_G4860 0x868001
1102 #define SVR_B4460 0x868003
1103 #define SVR_B4440 0x868100
1104 #define SVR_G4440 0x868101
1105 #define SVR_B4420 0x868102
1106 #define SVR_B4220 0x868103
1107 #define SVR_T1040 0x852000
1108 #define SVR_T1041 0x852001
1109 #define SVR_T1042 0x852002
1110 #define SVR_T1020 0x852100
1111 #define SVR_T1021 0x852101
1112 #define SVR_T1022 0x852102
1113 #define SVR_T1024 0x854000
1114 #define SVR_T1023 0x854100
1115 #define SVR_T1014 0x854400
1116 #define SVR_T1013 0x854500
1117 #define SVR_T2080 0x853000
1118 #define SVR_T2081 0x853100
1119
1120 #define SVR_8610 0x80A000
1121 #define SVR_8641 0x809000
1122 #define SVR_8641D 0x809001
1123
1124 #define SVR_9130 0x860001
1125 #define SVR_9131 0x860000
1126 #define SVR_9132 0x861000
1127 #define SVR_9232 0x861400
1128
1129 #define SVR_Unknown 0xFFFFFF
1130
1131 #define _GLOBAL(n)\
1132 .globl n;\
1133 n:
1134
1135 /* Macros for setting and retrieving special purpose registers */
1136
1137 #define stringify(s) tostring(s)
1138 #define tostring(s) #s
1139
1140 #define mfdcr(rn) ({unsigned int rval; \
1141 asm volatile("mfdcr %0," stringify(rn) \
1142 : "=r" (rval)); rval;})
1143 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v))
1144
1145 #define mfmsr() ({unsigned int rval; \
1146 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
1147 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
1148
1149 #define mfspr(rn) ({unsigned int rval; \
1150 asm volatile("mfspr %0," stringify(rn) \
1151 : "=r" (rval)); rval;})
1152 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v))
1153
1154 #define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v))
1155
1156 /* Segment Registers */
1157
1158 #define SR0 0
1159 #define SR1 1
1160 #define SR2 2
1161 #define SR3 3
1162 #define SR4 4
1163 #define SR5 5
1164 #define SR6 6
1165 #define SR7 7
1166 #define SR8 8
1167 #define SR9 9
1168 #define SR10 10
1169 #define SR11 11
1170 #define SR12 12
1171 #define SR13 13
1172 #define SR14 14
1173 #define SR15 15
1174
1175 #ifndef __ASSEMBLY__
1176
1177 struct cpu_type {
1178 char name[15];
1179 u32 soc_ver;
1180 u32 num_cores;
1181 u32 mask; /* which cpu(s) actually exist */
1182 #ifdef CONFIG_HETROGENOUS_CLUSTERS
1183 u32 dsp_num_cores;
1184 u32 dsp_mask; /* which DSP cpu(s) actually exist */
1185 #endif
1186 };
1187
1188 struct cpu_type *identify_cpu(u32 ver);
1189 int fixup_cpu(void);
1190
1191 int fsl_qoriq_core_to_cluster(unsigned int core);
1192 int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
1193
1194 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
1195 #define CPU_TYPE_ENTRY(n, v, nc) \
1196 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), \
1197 .mask = (1 << (nc)) - 1 }
1198 #define CPU_TYPE_ENTRY_MASK(n, v, nc, m) \
1199 { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc), .mask = (m) }
1200 #else
1201 #if defined(CONFIG_MPC83xx)
1202 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
1203 #endif
1204 #endif
1205
1206
1207 /* what kind of prep workstation we are */
1208 extern int _prep_type;
1209 /*
1210 * This is used to identify the board type from a given PReP board
1211 * vendor. Board revision is also made available.
1212 */
1213 extern unsigned char ucSystemType;
1214 extern unsigned char ucBoardRev;
1215 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
1216
1217 struct task_struct;
1218 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
1219 void release_thread(struct task_struct *);
1220
1221 /*
1222 * Create a new kernel thread.
1223 */
1224 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
1225
1226 /*
1227 * Bus types
1228 */
1229 #define EISA_bus 0
1230 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
1231 #define MCA_bus 0
1232 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
1233
1234 /* Lazy FPU handling on uni-processor */
1235 extern struct task_struct *last_task_used_math;
1236 extern struct task_struct *last_task_used_altivec;
1237
1238 /*
1239 * this is the minimum allowable io space due to the location
1240 * of the io areas on prep (first one at 0x80000000) but
1241 * as soon as I get around to remapping the io areas with the BATs
1242 * to match the mac we can raise this. -- Cort
1243 */
1244 #define TASK_SIZE (0x80000000UL)
1245
1246 /* This decides where the kernel will search for a free chunk of vm
1247 * space during mmap's.
1248 */
1249 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
1250
1251 typedef struct {
1252 unsigned long seg;
1253 } mm_segment_t;
1254
1255 struct thread_struct {
1256 unsigned long ksp; /* Kernel stack pointer */
1257 unsigned long wchan; /* Event task is sleeping on */
1258 struct pt_regs *regs; /* Pointer to saved register state */
1259 mm_segment_t fs; /* for get_fs() validation */
1260 void *pgdir; /* root of page-table tree */
1261 signed long last_syscall;
1262 double fpr[32]; /* Complete floating point set */
1263 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
1264 unsigned long fpscr; /* Floating point status */
1265 #ifdef CONFIG_ALTIVEC
1266 vector128 vr[32]; /* Complete AltiVec set */
1267 vector128 vscr; /* AltiVec status */
1268 unsigned long vrsave;
1269 #endif /* CONFIG_ALTIVEC */
1270 };
1271
1272 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
1273
1274 #define INIT_THREAD { \
1275 INIT_SP, /* ksp */ \
1276 0, /* wchan */ \
1277 (struct pt_regs *)INIT_SP - 1, /* regs */ \
1278 KERNEL_DS, /*fs*/ \
1279 swapper_pg_dir, /* pgdir */ \
1280 0, /* last_syscall */ \
1281 {0}, 0, 0 \
1282 }
1283
1284 /*
1285 * Note: the vm_start and vm_end fields here should *not*
1286 * be in kernel space. (Could vm_end == vm_start perhaps?)
1287 */
1288 #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \
1289 PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \
1290 1, NULL, NULL }
1291
1292 /*
1293 * Return saved PC of a blocked thread. For now, this is the "user" PC
1294 */
thread_saved_pc(struct thread_struct * t)1295 static inline unsigned long thread_saved_pc(struct thread_struct *t)
1296 {
1297 return (t->regs) ? t->regs->nip : 0;
1298 }
1299
1300 #define copy_segments(tsk, mm) do { } while (0)
1301 #define release_segments(mm) do { } while (0)
1302 #define forget_segments() do { } while (0)
1303
1304 unsigned long get_wchan(struct task_struct *p);
1305
1306 #define KSTK_EIP(tsk) ((tsk)->thread.regs->nip)
1307 #define KSTK_ESP(tsk) ((tsk)->thread.regs->gpr[1])
1308
1309 /*
1310 * NOTE! The task struct and the stack go together
1311 */
1312 #define THREAD_SIZE (2*PAGE_SIZE)
1313 #define alloc_task_struct() \
1314 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
1315 #define free_task_struct(p) free_pages((unsigned long)(p),1)
1316 #define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count)
1317
1318 /* in process.c - for early bootup debug -- Cort */
1319 int ll_printk(const char *, ...);
1320 void ll_puts(const char *);
1321
1322 #define init_task (init_task_union.task)
1323 #define init_stack (init_task_union.stack)
1324
1325 /* In misc.c */
1326 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
1327
1328 #ifndef CONFIG_CPU_MPC83XX
1329 int prt_83xx_rsr(void);
1330 #endif
1331
1332 #endif /* ndef ASSEMBLY*/
1333
1334 #if defined(CONFIG_MPC85xx)
1335 #define EPAPR_MAGIC (0x45504150)
1336 #else
1337 #define EPAPR_MAGIC (0x65504150)
1338 #endif
1339
1340 #endif /* __ASM_PPC_PROCESSOR_H */
1341