1 /* 2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> 3 * Copyright (C) 2012-2013 Xilinx, Inc. 4 * Copyright (C) 2007-2009 PetaLogix 5 * Copyright (C) 2006 Atmark Techno, Inc. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 12 #include <linux/irqdomain.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/of_address.h> 17 #include <linux/io.h> 18 #include <linux/jump_label.h> 19 #include <linux/bug.h> 20 #include <linux/of_irq.h> 21 22 /* No one else should require these constants, so define them locally here. */ 23 #define ISR 0x00 /* Interrupt Status Register */ 24 #define IPR 0x04 /* Interrupt Pending Register */ 25 #define IER 0x08 /* Interrupt Enable Register */ 26 #define IAR 0x0c /* Interrupt Acknowledge Register */ 27 #define SIE 0x10 /* Set Interrupt Enable bits */ 28 #define CIE 0x14 /* Clear Interrupt Enable bits */ 29 #define IVR 0x18 /* Interrupt Vector Register */ 30 #define MER 0x1c /* Master Enable Register */ 31 32 #define MER_ME (1<<0) 33 #define MER_HIE (1<<1) 34 35 #define SPURIOUS_IRQ (-1U) 36 37 static DEFINE_STATIC_KEY_FALSE(xintc_is_be); 38 39 struct xintc_irq_chip { 40 void __iomem *base; 41 struct irq_domain *root_domain; 42 u32 intr_mask; 43 u32 nr_irq; 44 }; 45 46 static struct xintc_irq_chip *primary_intc; 47 xintc_write(struct xintc_irq_chip * irqc,int reg,u32 data)48 static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data) 49 { 50 if (static_branch_unlikely(&xintc_is_be)) 51 iowrite32be(data, irqc->base + reg); 52 else 53 iowrite32(data, irqc->base + reg); 54 } 55 xintc_read(struct xintc_irq_chip * irqc,int reg)56 static u32 xintc_read(struct xintc_irq_chip *irqc, int reg) 57 { 58 if (static_branch_unlikely(&xintc_is_be)) 59 return ioread32be(irqc->base + reg); 60 else 61 return ioread32(irqc->base + reg); 62 } 63 intc_enable_or_unmask(struct irq_data * d)64 static void intc_enable_or_unmask(struct irq_data *d) 65 { 66 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 67 unsigned long mask = BIT(d->hwirq); 68 69 pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq); 70 71 /* ack level irqs because they can't be acked during 72 * ack function since the handle_level_irq function 73 * acks the irq before calling the interrupt handler 74 */ 75 if (irqd_is_level_type(d)) 76 xintc_write(irqc, IAR, mask); 77 78 xintc_write(irqc, SIE, mask); 79 } 80 intc_disable_or_mask(struct irq_data * d)81 static void intc_disable_or_mask(struct irq_data *d) 82 { 83 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 84 85 pr_debug("irq-xilinx: disable: %ld\n", d->hwirq); 86 xintc_write(irqc, CIE, BIT(d->hwirq)); 87 } 88 intc_ack(struct irq_data * d)89 static void intc_ack(struct irq_data *d) 90 { 91 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 92 93 pr_debug("irq-xilinx: ack: %ld\n", d->hwirq); 94 xintc_write(irqc, IAR, BIT(d->hwirq)); 95 } 96 intc_mask_ack(struct irq_data * d)97 static void intc_mask_ack(struct irq_data *d) 98 { 99 struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d); 100 unsigned long mask = BIT(d->hwirq); 101 102 pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq); 103 xintc_write(irqc, CIE, mask); 104 xintc_write(irqc, IAR, mask); 105 } 106 107 static struct irq_chip intc_dev = { 108 .name = "Xilinx INTC", 109 .irq_unmask = intc_enable_or_unmask, 110 .irq_mask = intc_disable_or_mask, 111 .irq_ack = intc_ack, 112 .irq_mask_ack = intc_mask_ack, 113 }; 114 xintc_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)115 static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw) 116 { 117 struct xintc_irq_chip *irqc = d->host_data; 118 119 if (irqc->intr_mask & BIT(hw)) { 120 irq_set_chip_and_handler_name(irq, &intc_dev, 121 handle_edge_irq, "edge"); 122 irq_clear_status_flags(irq, IRQ_LEVEL); 123 } else { 124 irq_set_chip_and_handler_name(irq, &intc_dev, 125 handle_level_irq, "level"); 126 irq_set_status_flags(irq, IRQ_LEVEL); 127 } 128 irq_set_chip_data(irq, irqc); 129 return 0; 130 } 131 132 static const struct irq_domain_ops xintc_irq_domain_ops = { 133 .xlate = irq_domain_xlate_onetwocell, 134 .map = xintc_map, 135 }; 136 xil_intc_irq_handler(struct irq_desc * desc)137 static void xil_intc_irq_handler(struct irq_desc *desc) 138 { 139 struct irq_chip *chip = irq_desc_get_chip(desc); 140 struct xintc_irq_chip *irqc; 141 142 irqc = irq_data_get_irq_handler_data(&desc->irq_data); 143 chained_irq_enter(chip, desc); 144 do { 145 u32 hwirq = xintc_read(irqc, IVR); 146 147 if (hwirq == -1U) 148 break; 149 150 generic_handle_domain_irq(irqc->root_domain, hwirq); 151 } while (true); 152 chained_irq_exit(chip, desc); 153 } 154 xil_intc_handle_irq(struct pt_regs * regs)155 static void xil_intc_handle_irq(struct pt_regs *regs) 156 { 157 u32 hwirq; 158 159 do { 160 hwirq = xintc_read(primary_intc, IVR); 161 if (unlikely(hwirq == SPURIOUS_IRQ)) 162 break; 163 164 generic_handle_domain_irq(primary_intc->root_domain, hwirq); 165 } while (true); 166 } 167 xilinx_intc_of_init(struct device_node * intc,struct device_node * parent)168 static int __init xilinx_intc_of_init(struct device_node *intc, 169 struct device_node *parent) 170 { 171 struct xintc_irq_chip *irqc; 172 int ret, irq; 173 174 irqc = kzalloc(sizeof(*irqc), GFP_KERNEL); 175 if (!irqc) 176 return -ENOMEM; 177 irqc->base = of_iomap(intc, 0); 178 BUG_ON(!irqc->base); 179 180 ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq); 181 if (ret < 0) { 182 pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n"); 183 goto error; 184 } 185 186 ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask); 187 if (ret < 0) { 188 pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n"); 189 irqc->intr_mask = 0; 190 } 191 192 if ((u64)irqc->intr_mask >> irqc->nr_irq) 193 pr_warn("irq-xilinx: mismatch in kind-of-intr param\n"); 194 195 pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n", 196 intc, irqc->nr_irq, irqc->intr_mask); 197 198 199 /* 200 * Disable all external interrupts until they are 201 * explicitly requested. 202 */ 203 xintc_write(irqc, IER, 0); 204 205 /* Acknowledge any pending interrupts just in case. */ 206 xintc_write(irqc, IAR, 0xffffffff); 207 208 /* Turn on the Master Enable. */ 209 xintc_write(irqc, MER, MER_HIE | MER_ME); 210 if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) { 211 static_branch_enable(&xintc_is_be); 212 xintc_write(irqc, MER, MER_HIE | MER_ME); 213 } 214 215 irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq, 216 &xintc_irq_domain_ops, irqc); 217 if (!irqc->root_domain) { 218 pr_err("irq-xilinx: Unable to create IRQ domain\n"); 219 ret = -EINVAL; 220 goto error; 221 } 222 223 if (parent) { 224 irq = irq_of_parse_and_map(intc, 0); 225 if (irq) { 226 irq_set_chained_handler_and_data(irq, 227 xil_intc_irq_handler, 228 irqc); 229 } else { 230 pr_err("irq-xilinx: interrupts property not in DT\n"); 231 ret = -EINVAL; 232 goto error; 233 } 234 } else { 235 primary_intc = irqc; 236 irq_set_default_host(primary_intc->root_domain); 237 set_handle_irq(xil_intc_handle_irq); 238 } 239 240 return 0; 241 242 error: 243 iounmap(irqc->base); 244 kfree(irqc); 245 return ret; 246 247 } 248 249 IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init); 250 IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init); 251