1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Board functions for EETS PDU001 board
6 *
7 * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
8 *
9 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
10 */
11
12 #include <common.h>
13 #include <errno.h>
14 #include <spl.h>
15 #include <i2c.h>
16 #include <environment.h>
17 #include <watchdog.h>
18 #include <debug_uart.h>
19 #include <dm/ofnode.h>
20 #include <power/pmic.h>
21 #include <power/regulator.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/hardware.h>
24 #include <asm/arch/omap.h>
25 #include <asm/arch/ddr_defs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/mmc_host_def.h>
29 #include <asm/arch/sys_proto.h>
30 #include <asm/arch/mem.h>
31 #include <asm/io.h>
32 #include <asm/emif.h>
33 #include <asm/gpio.h>
34 #include "board.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 #define I2C_ADDR_NODE_ID 0x50
39 #define I2C_REG_NODE_ID_BASE 0xfa
40 #define NODE_ID_BYTE_COUNT 6
41
42 #define I2C_ADDR_LEDS 0x60
43 #define I2C_REG_RUN_LED 0x06
44 #define RUN_LED_OFF 0x0
45 #define RUN_LED_RED 0x1
46 #define RUN_LED_GREEN (0x1 << 2)
47
48 #define VDD_MPU_REGULATOR "regulator@2"
49 #define VDD_CORE_REGULATOR "regulator@3"
50 #define DEFAULT_CORE_VOLTAGE 1137500
51
52 /*
53 * boot device save register
54 * -------------------------
55 * The boot device can be quired by 'spl_boot_device()' in
56 * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
57 * environment here. In turn 'spl_boot_device' can't be called in
58 * 'board_late_init' which allows writing to u-boot environment.
59 * To get the boot device from 'am33xx_spl_board_init' to
60 * 'board_late_init' we therefore use a scratch register from the RTC.
61 */
62 #define CONFIG_SYS_RTC_SCRATCH0 0x60
63 #define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
64
65 #ifdef CONFIG_SPL_BUILD
save_boot_device(void)66 static void save_boot_device(void)
67 {
68 *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
69 }
70 #endif
71
boot_device(void)72 u32 boot_device(void)
73 {
74 return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
75 }
76
77 /* Store the boot device in the environment variable 'boot_device' */
env_set_boot_device(void)78 static void env_set_boot_device(void)
79 {
80 switch (boot_device()) {
81 case BOOT_DEVICE_MMC1: {
82 env_set("boot_device", "emmc");
83 break;
84 }
85 case BOOT_DEVICE_MMC2: {
86 env_set("boot_device", "sdcard");
87 break;
88 }
89 default: {
90 env_set("boot_device", "unknown");
91 break;
92 }
93 }
94 }
95
set_run_led(struct udevice * dev)96 static void set_run_led(struct udevice *dev)
97 {
98 int val = RUN_LED_OFF;
99
100 if (IS_ENABLED(CONFIG_RUN_LED_RED))
101 val = RUN_LED_RED;
102 else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
103 val = RUN_LED_GREEN;
104
105 dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
106 }
107
108 /* Set 'serial#' to the EUI-48 value of board node ID chip */
env_set_serial(struct udevice * dev)109 static void env_set_serial(struct udevice *dev)
110 {
111 int val;
112 char serial[2 * NODE_ID_BYTE_COUNT + 1];
113 int n;
114
115 for (n = 0; n < sizeof(serial); n += 2) {
116 val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
117 sprintf(serial + n, "%02X", val);
118 }
119 serial[2 * NODE_ID_BYTE_COUNT] = '\0';
120 env_set("serial#", serial);
121 }
122
set_mpu_and_core_voltage(void)123 static void set_mpu_and_core_voltage(void)
124 {
125 int mpu_vdd;
126 int sil_rev;
127 struct udevice *dev;
128 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
129
130 /*
131 * The PDU001 (more precisely the computing module m2) uses a
132 * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
133 * voltage of 1.1375V. For MPU voltage we need to switch based on
134 * the frequency we are running at.
135 */
136
137 /*
138 * Depending on MPU clock and PG we will need a different VDD
139 * to drive at that speed.
140 */
141 sil_rev = readl(&cdev->deviceid) >> 28;
142 mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
143
144 /* first update the MPU voltage */
145 if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
146 if (regulator_set_value(dev, mpu_vdd))
147 debug("failed to set MPU voltage\n");
148 } else {
149 debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
150 }
151
152 /* second update the CORE voltage */
153 if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
154 if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
155 debug("failed to set CORE voltage\n");
156 } else {
157 debug("invalid CORE voltage ragulator %s\n",
158 VDD_CORE_REGULATOR);
159 }
160 }
161
162 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
163 static const struct ddr_data ddr2_data = {
164 .datardsratio0 = MT47H128M16RT25E_RD_DQS,
165 .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
166 .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
167 };
168
169 static const struct cmd_control ddr2_cmd_ctrl_data = {
170 .cmd0csratio = MT47H128M16RT25E_RATIO,
171 .cmd1csratio = MT47H128M16RT25E_RATIO,
172 .cmd2csratio = MT47H128M16RT25E_RATIO,
173 };
174
175 static const struct emif_regs ddr2_emif_reg_data = {
176 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
177 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
178 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
179 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
180 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
181 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
182 };
183
184 #define OSC (V_OSCK / 1000000)
185 const struct dpll_params dpll_ddr = {
186 266, OSC - 1, 1, -1, -1, -1, -1};
187 const struct dpll_params dpll_ddr_evm_sk = {
188 303, OSC - 1, 1, -1, -1, -1, -1};
189 const struct dpll_params dpll_ddr_bone_black = {
190 400, OSC - 1, 1, -1, -1, -1, -1};
191
am33xx_spl_board_init(void)192 void am33xx_spl_board_init(void)
193 {
194 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
195
196 /* Get the frequency */
197 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
198
199 /* Set CORE Frequencies to OPP100 */
200 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
201
202 /* Set MPU Frequency to what we detected now that voltages are set */
203 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
204
205 /* save boot device for later use by 'board_late_init' */
206 save_boot_device();
207 }
208
get_dpll_ddr_params(void)209 const struct dpll_params *get_dpll_ddr_params(void)
210 {
211 enable_i2c0_pin_mux();
212
213 return &dpll_ddr;
214 }
215
set_mux_conf_regs(void)216 void set_mux_conf_regs(void)
217 {
218 /* done first by the ROM and afterwards by the pin controller driver */
219 enable_i2c0_pin_mux();
220 }
221
222 const struct ctrl_ioregs ioregs = {
223 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
224 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
225 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
226 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
227 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
228 };
229
sdram_init(void)230 void sdram_init(void)
231 {
232 config_ddr(266, &ioregs, &ddr2_data,
233 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
234 }
235 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
236
237 #ifdef CONFIG_DEBUG_UART
board_debug_uart_init(void)238 void board_debug_uart_init(void)
239 {
240 /* done by pin controller driver if not debugging */
241 enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
242 }
243 #endif
244
245 /*
246 * Basic board specific setup. Pinmux has been handled already.
247 */
board_init(void)248 int board_init(void)
249 {
250 #ifdef CONFIG_HW_WATCHDOG
251 hw_watchdog_init();
252 #endif
253
254 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
255 return 0;
256 }
257
258 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)259 int board_late_init(void)
260 {
261 struct udevice *dev;
262
263 set_mpu_and_core_voltage();
264 env_set_boot_device();
265
266 /* second I2C bus connects to node ID and front panel LED chip */
267 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
268 set_run_led(dev);
269 if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
270 env_set_serial(dev);
271
272 return 0;
273 }
274 #endif
275