xref: /openbmc/qemu/include/hw/char/stm32l4x5_usart.h (revision 87b77e6e)
1 /*
2  * STM32L4X5 USART (Universal Synchronous Asynchronous Receiver Transmitter)
3  *
4  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  *
12  * The STM32L4X5 USART is heavily inspired by the stm32f2xx_usart
13  * by Alistair Francis.
14  * The reference used is the STMicroElectronics RM0351 Reference manual
15  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
16  */
17 
18 #ifndef HW_STM32L4X5_USART_H
19 #define HW_STM32L4X5_USART_H
20 
21 #include "hw/sysbus.h"
22 #include "chardev/char-fe.h"
23 #include "qom/object.h"
24 
25 #define TYPE_STM32L4X5_USART_BASE "stm32l4x5-usart-base"
26 #define TYPE_STM32L4X5_USART "stm32l4x5-usart"
27 #define TYPE_STM32L4X5_UART "stm32l4x5-uart"
28 #define TYPE_STM32L4X5_LPUART "stm32l4x5-lpuart"
29 OBJECT_DECLARE_TYPE(Stm32l4x5UsartBaseState, Stm32l4x5UsartBaseClass,
30                     STM32L4X5_USART_BASE)
31 
32 typedef enum {
33     STM32L4x5_USART,
34     STM32L4x5_UART,
35     STM32L4x5_LPUART,
36 } Stm32l4x5UsartType;
37 
38 struct Stm32l4x5UsartBaseState {
39     SysBusDevice parent_obj;
40 
41     MemoryRegion mmio;
42 
43     uint32_t cr1;
44     uint32_t cr2;
45     uint32_t cr3;
46     uint32_t brr;
47     uint32_t gtpr;
48     uint32_t rtor;
49     /* rqr is write-only */
50     uint32_t isr;
51     /* icr is a clear register */
52     uint32_t rdr;
53     uint32_t tdr;
54 
55     Clock *clk;
56     CharBackend chr;
57     qemu_irq irq;
58     guint watch_tag;
59 };
60 
61 struct Stm32l4x5UsartBaseClass {
62     SysBusDeviceClass parent_class;
63 
64     Stm32l4x5UsartType type;
65 };
66 
67 #endif /* HW_STM32L4X5_USART_H */
68