xref: /openbmc/qemu/include/hw/misc/stm32l4x5_exti.h (revision 27d40530)
1 /*
2  * STM32L4x5 EXTI (Extended interrupts and events controller)
3  *
4  * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
5  * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
6  *
7  * SPDX-License-Identifier: GPL-2.0-or-later
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  *
12  * This work is based on the stm32f4xx_exti by Alistair Francis.
13  * Original code is licensed under the MIT License:
14  *
15  * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
16  */
17 
18 /*
19  * The reference used is the STMicroElectronics RM0351 Reference manual
20  * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
21  * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
22  */
23 
24 #ifndef HW_STM32L4X5_EXTI_H
25 #define HW_STM32L4X5_EXTI_H
26 
27 #include "hw/sysbus.h"
28 #include "qom/object.h"
29 
30 #define TYPE_STM32L4X5_EXTI "stm32l4x5-exti"
31 OBJECT_DECLARE_SIMPLE_TYPE(Stm32l4x5ExtiState, STM32L4X5_EXTI)
32 
33 #define EXTI_NUM_LINES 40
34 #define EXTI_NUM_REGISTER 2
35 
36 struct Stm32l4x5ExtiState {
37     SysBusDevice parent_obj;
38 
39     MemoryRegion mmio;
40 
41     uint32_t imr[EXTI_NUM_REGISTER];
42     uint32_t emr[EXTI_NUM_REGISTER];
43     uint32_t rtsr[EXTI_NUM_REGISTER];
44     uint32_t ftsr[EXTI_NUM_REGISTER];
45     uint32_t swier[EXTI_NUM_REGISTER];
46     uint32_t pr[EXTI_NUM_REGISTER];
47 
48     /* used for edge detection */
49     uint32_t irq_levels[EXTI_NUM_REGISTER];
50     qemu_irq irq[EXTI_NUM_LINES];
51 };
52 
53 #endif
54