1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2016 Savoir-faire Linux Inc.
4  *
5  * Author: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
6  *
7  * Based on work from TS7680 code by:
8  *   Kris Bahnsen <kris@embeddedarm.com>
9  *   Mark Featherston <mark@embeddedarm.com>
10  *   https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680
11  *
12  * Derived from MX28EVK code by
13  *   Freescale Semiconductor, Inc.
14  */
15 
16 #include <common.h>
17 #include <config.h>
18 #include <asm/io.h>
19 #include <asm/arch/iomux-mx28.h>
20 #include <asm/arch/imx-regs.h>
21 #include <asm/arch/sys_proto.h>
22 
23 #define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
24 #define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
25 
26 const iomux_cfg_t iomux_setup[] = {
27 	/* DUART */
28 	MX28_PAD_PWM0__DUART_RX,
29 	MX28_PAD_PWM1__DUART_TX,
30 
31 	/* MMC0 */
32 	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
33 	MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
34 	MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
35 	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
36 	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
37 	MX28_PAD_SSP0_SCK__SSP0_SCK |
38 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
39 
40 	/* MMC0 slot power enable */
41 	MX28_PAD_PWM3__GPIO_3_28 |
42 		(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
43 
44 	/* EMI */
45 	MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
46 	MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
47 	MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
48 	MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
49 	MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
50 	MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
51 	MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
52 	MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
53 	MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
54 	MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
55 	MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
56 	MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
57 	MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
58 	MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
59 	MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
60 	MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
61 	MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
62 	MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
63 	MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
64 	MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
65 	MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
66 	MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
67 	MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
68 	MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
69 	MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
70 	MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
71 	MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
72 	MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
73 	MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
74 	MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
75 	MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
76 	MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
77 	MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
78 	MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
79 	MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
80 	MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
81 	MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
82 	MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
83 	MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
84 	MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
85 	MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
86 	MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
87 	MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
88 	MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
89 	MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
90 	MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
91 	MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
92 	MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
93 	MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
94 
95 	/* I2C */
96 	MX28_PAD_I2C0_SCL__I2C0_SCL,
97 	MX28_PAD_I2C0_SDA__I2C0_SDA,
98 
99 };
100 
101 #define HW_DRAM_CTL29	(0x74 >> 2)
102 #define CS_MAP		0xf
103 #define COLUMN_SIZE	0x2
104 #define ADDR_PINS	0x1
105 #define APREBIT		0xa
106 
107 #define HW_DRAM_CTL29_CONFIG	(CS_MAP << 24 | COLUMN_SIZE << 16 | \
108 					ADDR_PINS << 8 | APREBIT)
109 
110 #define HW_DRAM_CTL39	(0x9c >> 2)
111 #define TFAW		0xb
112 #define TDLL		0xc8
113 
114 #define HW_DRAM_CTL39_CONFIG	(TFAW << 24 | TDLL)
115 
116 #define HW_DRAM_CTL41	(0xa4 >> 2)
117 #define TPDEX		0x2
118 #define TRCD_INT	0x4
119 #define TRC		0xd
120 
121 #define HW_DRAM_CTL41_CONFIG	(TPDEX << 24 | TRCD_INT << 8 | TRC)
122 
123 #define HW_DRAM_CTL42	(0xa8 >> 2)
124 #define TRAS_MAX	0x36a6
125 #define TRAS_MIN	0xa
126 
127 #define HW_DRAM_CTL42_CONFIG  (TRAS_MAX << 8 | TRAS_MIN)
128 
129 #define HW_DRAM_CTL43	(0xac >> 2)
130 #define TRP		0x4
131 #define TRFC		0x27
132 #define TREF		0x2a0
133 
134 #define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF)
135 
mxs_adjust_memory_params(uint32_t * dram_vals)136 void mxs_adjust_memory_params(uint32_t *dram_vals)
137 {
138 	dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG;
139 	dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG;
140 	dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG;
141 	dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG;
142 	dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG;
143 }
144 
board_init_ll(const uint32_t arg,const uint32_t * resptr)145 void board_init_ll(const uint32_t arg, const uint32_t *resptr)
146 {
147 	mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
148 }
149