xref: /openbmc/linux/drivers/char/hw_random/n2rng.h (revision b2441318)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* n2rng.h: Niagara2 RNG defines.
3  *
4  * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
5  */
6 
7 #ifndef _N2RNG_H
8 #define _N2RNG_H
9 
10 /* ver1 devices - n2-rng, vf-rng, kt-rng */
11 #define RNG_v1_CTL_WAIT       0x0000000001fffe00ULL /* Minimum wait time    */
12 #define RNG_v1_CTL_WAIT_SHIFT 9
13 #define RNG_v1_CTL_BYPASS     0x0000000000000100ULL /* VCO voltage source   */
14 #define RNG_v1_CTL_VCO        0x00000000000000c0ULL /* VCO rate control     */
15 #define RNG_v1_CTL_VCO_SHIFT  6
16 #define RNG_v1_CTL_ASEL       0x0000000000000030ULL /* Analog MUX select    */
17 #define RNG_v1_CTL_ASEL_SHIFT 4
18 #define RNG_v1_CTL_ASEL_NOOUT 2
19 
20 /* these are the same in v2 as in v1 */
21 #define RNG_CTL_LFSR       0x0000000000000008ULL /* Use LFSR or plain shift */
22 #define RNG_CTL_ES3        0x0000000000000004ULL /* Enable entropy source 3 */
23 #define RNG_CTL_ES2        0x0000000000000002ULL /* Enable entropy source 2 */
24 #define RNG_CTL_ES1        0x0000000000000001ULL /* Enable entropy source 1 */
25 
26 /* ver2 devices - m4-rng, m7-rng */
27 #define RNG_v2_CTL_WAIT       0x0000000007fff800ULL /* Minimum wait time    */
28 #define RNG_v2_CTL_WAIT_SHIFT 12
29 #define RNG_v2_CTL_BYPASS     0x0000000000000400ULL /* VCO voltage source   */
30 #define RNG_v2_CTL_VCO        0x0000000000000300ULL /* VCO rate control     */
31 #define RNG_v2_CTL_VCO_SHIFT  9
32 #define RNG_v2_CTL_PERF       0x0000000000000180ULL /* Perf */
33 #define RNG_v2_CTL_ASEL       0x0000000000000070ULL /* Analog MUX select    */
34 #define RNG_v2_CTL_ASEL_SHIFT 4
35 #define RNG_v2_CTL_ASEL_NOOUT 7
36 
37 
38 #define HV_FAST_RNG_GET_DIAG_CTL	0x130
39 #define HV_FAST_RNG_CTL_READ		0x131
40 #define HV_FAST_RNG_CTL_WRITE		0x132
41 #define HV_FAST_RNG_DATA_READ_DIAG	0x133
42 #define HV_FAST_RNG_DATA_READ		0x134
43 
44 #define HV_RNG_STATE_UNCONFIGURED	0
45 #define HV_RNG_STATE_CONFIGURED		1
46 #define HV_RNG_STATE_HEALTHCHECK	2
47 #define HV_RNG_STATE_ERROR		3
48 
49 #define HV_RNG_NUM_CONTROL		4
50 
51 #ifndef __ASSEMBLY__
52 extern unsigned long sun4v_rng_get_diag_ctl(void);
53 extern unsigned long sun4v_rng_ctl_read_v1(unsigned long ctl_regs_ra,
54 					   unsigned long *state,
55 					   unsigned long *tick_delta);
56 extern unsigned long sun4v_rng_ctl_read_v2(unsigned long ctl_regs_ra,
57 					   unsigned long unit,
58 					   unsigned long *state,
59 					   unsigned long *tick_delta,
60 					   unsigned long *watchdog,
61 					   unsigned long *write_status);
62 extern unsigned long sun4v_rng_ctl_write_v1(unsigned long ctl_regs_ra,
63 					    unsigned long state,
64 					    unsigned long write_timeout,
65 					    unsigned long *tick_delta);
66 extern unsigned long sun4v_rng_ctl_write_v2(unsigned long ctl_regs_ra,
67 					    unsigned long state,
68 					    unsigned long write_timeout,
69 					    unsigned long unit);
70 extern unsigned long sun4v_rng_data_read_diag_v1(unsigned long data_ra,
71 						 unsigned long len,
72 						 unsigned long *tick_delta);
73 extern unsigned long sun4v_rng_data_read_diag_v2(unsigned long data_ra,
74 						 unsigned long len,
75 						 unsigned long unit,
76 						 unsigned long *tick_delta);
77 extern unsigned long sun4v_rng_data_read(unsigned long data_ra,
78 					 unsigned long *tick_delta);
79 
80 enum n2rng_compat_id {
81 	N2_n2_rng,
82 	N2_vf_rng,
83 	N2_kt_rng,
84 	N2_m4_rng,
85 	N2_m7_rng,
86 };
87 
88 struct n2rng_template {
89 	enum n2rng_compat_id id;
90 	int multi_capable;
91 	int chip_version;
92 };
93 
94 struct n2rng_unit {
95 	u64			control[HV_RNG_NUM_CONTROL];
96 };
97 
98 struct n2rng {
99 	struct platform_device	*op;
100 
101 	unsigned long		flags;
102 #define N2RNG_FLAG_MULTI	0x00000001 /* Multi-unit capable RNG */
103 #define N2RNG_FLAG_CONTROL	0x00000002 /* Operating in control domain */
104 #define N2RNG_FLAG_READY	0x00000008 /* Ready for hw-rng layer      */
105 #define N2RNG_FLAG_SHUTDOWN	0x00000010 /* Driver unregistering        */
106 #define N2RNG_FLAG_BUFFER_VALID	0x00000020 /* u32 buffer holds valid data */
107 
108 	struct n2rng_template	*data;
109 	int			num_units;
110 	struct n2rng_unit	*units;
111 
112 	struct hwrng		hwrng;
113 	u32			buffer;
114 
115 	/* Registered hypervisor group API major and minor version.  */
116 	unsigned long		hvapi_major;
117 	unsigned long		hvapi_minor;
118 
119 	struct delayed_work	work;
120 
121 	unsigned long		hv_state; /* HV_RNG_STATE_foo */
122 
123 	unsigned long		health_check_sec;
124 	unsigned long		accum_cycles;
125 	unsigned long		wd_timeo;
126 #define N2RNG_HEALTH_CHECK_SEC_DEFAULT	0
127 #define N2RNG_ACCUM_CYCLES_DEFAULT	2048
128 #define N2RNG_WD_TIMEO_DEFAULT		0
129 
130 	u64			scratch_control[HV_RNG_NUM_CONTROL];
131 
132 #define RNG_v1_SELFTEST_TICKS	38859
133 #define RNG_v1_SELFTEST_VAL	((u64)0xB8820C7BD387E32C)
134 #define RNG_v2_SELFTEST_TICKS	64
135 #define RNG_v2_SELFTEST_VAL	((u64)0xffffffffffffffff)
136 #define SELFTEST_POLY		((u64)0x231DCEE91262B8A3)
137 #define SELFTEST_MATCH_GOAL	6
138 #define SELFTEST_LOOPS_MAX	40000
139 #define SELFTEST_BUFFER_WORDS	8
140 
141 	u64			test_data;
142 	u64			test_control[HV_RNG_NUM_CONTROL];
143 	u64			test_buffer[SELFTEST_BUFFER_WORDS];
144 };
145 
146 #define N2RNG_BLOCK_LIMIT	60000
147 #define N2RNG_BUSY_LIMIT	100
148 #define N2RNG_HCHECK_LIMIT	100
149 
150 #endif /* !(__ASSEMBLY__) */
151 
152 #endif /* _N2RNG_H */
153