xref: /openbmc/qemu/include/hw/xen/interface/hvm/params.h (revision 8ac98aed)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright (c) 2007, Keir Fraser
4  */
5 
6 #ifndef __XEN_PUBLIC_HVM_PARAMS_H__
7 #define __XEN_PUBLIC_HVM_PARAMS_H__
8 
9 #include "hvm_op.h"
10 
11 /* These parameters are deprecated and their meaning is undefined. */
12 #if defined(__XEN__) || defined(__XEN_TOOLS__)
13 
14 #define HVM_PARAM_PAE_ENABLED                4
15 #define HVM_PARAM_DM_DOMAIN                 13
16 #define HVM_PARAM_MEMORY_EVENT_CR0          20
17 #define HVM_PARAM_MEMORY_EVENT_CR3          21
18 #define HVM_PARAM_MEMORY_EVENT_CR4          22
19 #define HVM_PARAM_MEMORY_EVENT_INT3         23
20 #define HVM_PARAM_NESTEDHVM                 24
21 #define HVM_PARAM_MEMORY_EVENT_SINGLE_STEP  25
22 #define HVM_PARAM_BUFIOREQ_EVTCHN           26
23 #define HVM_PARAM_MEMORY_EVENT_MSR          30
24 
25 #endif /* defined(__XEN__) || defined(__XEN_TOOLS__) */
26 
27 /*
28  * Parameter space for HVMOP_{set,get}_param.
29  */
30 
31 #define HVM_PARAM_CALLBACK_IRQ 0
32 #define HVM_PARAM_CALLBACK_IRQ_TYPE_MASK xen_mk_ullong(0xFF00000000000000)
33 /*
34  * How should CPU0 event-channel notifications be delivered?
35  *
36  * If val == 0 then CPU0 event-channel notifications are not delivered.
37  * If val != 0, val[63:56] encodes the type, as follows:
38  */
39 
40 #define HVM_PARAM_CALLBACK_TYPE_GSI      0
41 /*
42  * val[55:0] is a delivery GSI.  GSI 0 cannot be used, as it aliases val == 0,
43  * and disables all notifications.
44  */
45 
46 #define HVM_PARAM_CALLBACK_TYPE_PCI_INTX 1
47 /*
48  * val[55:0] is a delivery PCI INTx line:
49  * Domain = val[47:32], Bus = val[31:16] DevFn = val[15:8], IntX = val[1:0]
50  */
51 
52 #if defined(__i386__) || defined(__x86_64__)
53 #define HVM_PARAM_CALLBACK_TYPE_VECTOR   2
54 /*
55  * val[7:0] is a vector number.  Check for XENFEAT_hvm_callback_vector to know
56  * if this delivery method is available.
57  */
58 #elif defined(__arm__) || defined(__aarch64__)
59 #define HVM_PARAM_CALLBACK_TYPE_PPI      2
60 /*
61  * val[55:16] needs to be zero.
62  * val[15:8] is interrupt flag of the PPI used by event-channel:
63  *  bit 8: the PPI is edge(1) or level(0) triggered
64  *  bit 9: the PPI is active low(1) or high(0)
65  * val[7:0] is a PPI number used by event-channel.
66  * This is only used by ARM/ARM64 and masking/eoi the interrupt associated to
67  * the notification is handled by the interrupt controller.
68  */
69 #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK      0xFF00
70 #define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL 2
71 #endif
72 
73 /*
74  * These are not used by Xen. They are here for convenience of HVM-guest
75  * xenbus implementations.
76  */
77 #define HVM_PARAM_STORE_PFN    1
78 #define HVM_PARAM_STORE_EVTCHN 2
79 
80 #define HVM_PARAM_IOREQ_PFN    5
81 
82 #define HVM_PARAM_BUFIOREQ_PFN 6
83 
84 #if defined(__i386__) || defined(__x86_64__)
85 
86 /*
87  * Viridian enlightenments
88  *
89  * (See http://download.microsoft.com/download/A/B/4/AB43A34E-BDD0-4FA6-BDEF-79EEF16E880B/Hypervisor%20Top%20Level%20Functional%20Specification%20v4.0.docx)
90  *
91  * To expose viridian enlightenments to the guest set this parameter
92  * to the desired feature mask. The base feature set must be present
93  * in any valid feature mask.
94  */
95 #define HVM_PARAM_VIRIDIAN     9
96 
97 /* Base+Freq viridian feature sets:
98  *
99  * - Hypercall MSRs (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL)
100  * - APIC access MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and HV_X64_MSR_TPR)
101  * - Virtual Processor index MSR (HV_X64_MSR_VP_INDEX)
102  * - Timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
103  *   HV_X64_MSR_APIC_FREQUENCY)
104  */
105 #define _HVMPV_base_freq 0
106 #define HVMPV_base_freq  (1 << _HVMPV_base_freq)
107 
108 /* Feature set modifications */
109 
110 /* Disable timer frequency MSRs (HV_X64_MSR_TSC_FREQUENCY and
111  * HV_X64_MSR_APIC_FREQUENCY).
112  * This modification restores the viridian feature set to the
113  * original 'base' set exposed in releases prior to Xen 4.4.
114  */
115 #define _HVMPV_no_freq 1
116 #define HVMPV_no_freq  (1 << _HVMPV_no_freq)
117 
118 /* Enable Partition Time Reference Counter (HV_X64_MSR_TIME_REF_COUNT) */
119 #define _HVMPV_time_ref_count 2
120 #define HVMPV_time_ref_count  (1 << _HVMPV_time_ref_count)
121 
122 /* Enable Reference TSC Page (HV_X64_MSR_REFERENCE_TSC) */
123 #define _HVMPV_reference_tsc 3
124 #define HVMPV_reference_tsc  (1 << _HVMPV_reference_tsc)
125 
126 /* Use Hypercall for remote TLB flush */
127 #define _HVMPV_hcall_remote_tlb_flush 4
128 #define HVMPV_hcall_remote_tlb_flush (1 << _HVMPV_hcall_remote_tlb_flush)
129 
130 /* Use APIC assist */
131 #define _HVMPV_apic_assist 5
132 #define HVMPV_apic_assist (1 << _HVMPV_apic_assist)
133 
134 /* Enable crash MSRs */
135 #define _HVMPV_crash_ctl 6
136 #define HVMPV_crash_ctl (1 << _HVMPV_crash_ctl)
137 
138 /* Enable SYNIC MSRs */
139 #define _HVMPV_synic 7
140 #define HVMPV_synic (1 << _HVMPV_synic)
141 
142 /* Enable STIMER MSRs */
143 #define _HVMPV_stimer 8
144 #define HVMPV_stimer (1 << _HVMPV_stimer)
145 
146 /* Use Synthetic Cluster IPI Hypercall */
147 #define _HVMPV_hcall_ipi 9
148 #define HVMPV_hcall_ipi (1 << _HVMPV_hcall_ipi)
149 
150 /* Enable ExProcessorMasks */
151 #define _HVMPV_ex_processor_masks 10
152 #define HVMPV_ex_processor_masks (1 << _HVMPV_ex_processor_masks)
153 
154 /* Allow more than 64 VPs */
155 #define _HVMPV_no_vp_limit 11
156 #define HVMPV_no_vp_limit (1 << _HVMPV_no_vp_limit)
157 
158 /* Enable vCPU hotplug */
159 #define _HVMPV_cpu_hotplug 12
160 #define HVMPV_cpu_hotplug (1 << _HVMPV_cpu_hotplug)
161 
162 #define HVMPV_feature_mask \
163         (HVMPV_base_freq | \
164          HVMPV_no_freq | \
165          HVMPV_time_ref_count | \
166          HVMPV_reference_tsc | \
167          HVMPV_hcall_remote_tlb_flush | \
168          HVMPV_apic_assist | \
169          HVMPV_crash_ctl | \
170          HVMPV_synic | \
171          HVMPV_stimer | \
172          HVMPV_hcall_ipi | \
173          HVMPV_ex_processor_masks | \
174          HVMPV_no_vp_limit | \
175          HVMPV_cpu_hotplug)
176 
177 #endif
178 
179 /*
180  * Set mode for virtual timers (currently x86 only):
181  *  delay_for_missed_ticks (default):
182  *   Do not advance a vcpu's time beyond the correct delivery time for
183  *   interrupts that have been missed due to preemption. Deliver missed
184  *   interrupts when the vcpu is rescheduled and advance the vcpu's virtual
185  *   time stepwise for each one.
186  *  no_delay_for_missed_ticks:
187  *   As above, missed interrupts are delivered, but guest time always tracks
188  *   wallclock (i.e., real) time while doing so.
189  *  no_missed_ticks_pending:
190  *   No missed interrupts are held pending. Instead, to ensure ticks are
191  *   delivered at some non-zero rate, if we detect missed ticks then the
192  *   internal tick alarm is not disabled if the VCPU is preempted during the
193  *   next tick period.
194  *  one_missed_tick_pending:
195  *   Missed interrupts are collapsed together and delivered as one 'late tick'.
196  *   Guest time always tracks wallclock (i.e., real) time.
197  */
198 #define HVM_PARAM_TIMER_MODE   10
199 #define HVMPTM_delay_for_missed_ticks    0
200 #define HVMPTM_no_delay_for_missed_ticks 1
201 #define HVMPTM_no_missed_ticks_pending   2
202 #define HVMPTM_one_missed_tick_pending   3
203 
204 /* Boolean: Enable virtual HPET (high-precision event timer)? (x86-only) */
205 #define HVM_PARAM_HPET_ENABLED 11
206 
207 /* Identity-map page directory used by Intel EPT when CR0.PG=0. */
208 #define HVM_PARAM_IDENT_PT     12
209 
210 /* ACPI S state: currently support S0 and S3 on x86. */
211 #define HVM_PARAM_ACPI_S_STATE 14
212 
213 /* TSS used on Intel when CR0.PE=0. */
214 #define HVM_PARAM_VM86_TSS     15
215 
216 /* Boolean: Enable aligning all periodic vpts to reduce interrupts */
217 #define HVM_PARAM_VPT_ALIGN    16
218 
219 /* Console debug shared memory ring and event channel */
220 #define HVM_PARAM_CONSOLE_PFN    17
221 #define HVM_PARAM_CONSOLE_EVTCHN 18
222 
223 /*
224  * Select location of ACPI PM1a and TMR control blocks. Currently two locations
225  * are supported, specified by version 0 or 1 in this parameter:
226  *   - 0: default, use the old addresses
227  *        PM1A_EVT == 0x1f40; PM1A_CNT == 0x1f44; PM_TMR == 0x1f48
228  *   - 1: use the new default qemu addresses
229  *        PM1A_EVT == 0xb000; PM1A_CNT == 0xb004; PM_TMR == 0xb008
230  * You can find these address definitions in <hvm/ioreq.h>
231  */
232 #define HVM_PARAM_ACPI_IOPORTS_LOCATION 19
233 
234 /* Params for the mem event rings */
235 #define HVM_PARAM_PAGING_RING_PFN   27
236 #define HVM_PARAM_MONITOR_RING_PFN  28
237 #define HVM_PARAM_SHARING_RING_PFN  29
238 
239 /* SHUTDOWN_* action in case of a triple fault */
240 #define HVM_PARAM_TRIPLE_FAULT_REASON 31
241 
242 #define HVM_PARAM_IOREQ_SERVER_PFN 32
243 #define HVM_PARAM_NR_IOREQ_SERVER_PAGES 33
244 
245 /* Location of the VM Generation ID in guest physical address space. */
246 #define HVM_PARAM_VM_GENERATION_ID_ADDR 34
247 
248 /*
249  * Set mode for altp2m:
250  *  disabled: don't activate altp2m (default)
251  *  mixed: allow access to all altp2m ops for both in-guest and external tools
252  *  external: allow access to external privileged tools only
253  *  limited: guest only has limited access (ie. control VMFUNC and #VE)
254  *
255  * Note that 'mixed' mode has not been evaluated for safety from a
256  * security perspective.  Before using this mode in a
257  * security-critical environment, each subop should be evaluated for
258  * safety, with unsafe subops blacklisted in XSM.
259  */
260 #define HVM_PARAM_ALTP2M       35
261 #define XEN_ALTP2M_disabled      0
262 #define XEN_ALTP2M_mixed         1
263 #define XEN_ALTP2M_external      2
264 #define XEN_ALTP2M_limited       3
265 
266 /*
267  * Size of the x87 FPU FIP/FDP registers that the hypervisor needs to
268  * save/restore.  This is a workaround for a hardware limitation that
269  * does not allow the full FIP/FDP and FCS/FDS to be restored.
270  *
271  * Valid values are:
272  *
273  * 8: save/restore 64-bit FIP/FDP and clear FCS/FDS (default if CPU
274  *    has FPCSDS feature).
275  *
276  * 4: save/restore 32-bit FIP/FDP, FCS/FDS, and clear upper 32-bits of
277  *    FIP/FDP.
278  *
279  * 0: allow hypervisor to choose based on the value of FIP/FDP
280  *    (default if CPU does not have FPCSDS).
281  *
282  * If FPCSDS (bit 13 in CPUID leaf 0x7, subleaf 0x0) is set, the CPU
283  * never saves FCS/FDS and this parameter should be left at the
284  * default of 8.
285  */
286 #define HVM_PARAM_X87_FIP_WIDTH 36
287 
288 /*
289  * TSS (and its size) used on Intel when CR0.PE=0. The address occupies
290  * the low 32 bits, while the size is in the high 32 ones.
291  */
292 #define HVM_PARAM_VM86_TSS_SIZED 37
293 
294 /* Enable MCA capabilities. */
295 #define HVM_PARAM_MCA_CAP 38
296 #define XEN_HVM_MCA_CAP_LMCE   (xen_mk_ullong(1) << 0)
297 #define XEN_HVM_MCA_CAP_MASK   XEN_HVM_MCA_CAP_LMCE
298 
299 #define HVM_NR_PARAMS 39
300 
301 #endif /* __XEN_PUBLIC_HVM_PARAMS_H__ */
302