xref: /openbmc/u-boot/arch/mips/include/asm/cacheops.h (revision 7e40d0a3)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Cache operations for the cache instruction.
4  *
5  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
6  * (C) Copyright 1999 Silicon Graphics, Inc.
7  */
8 #ifndef	__ASM_CACHEOPS_H
9 #define	__ASM_CACHEOPS_H
10 
11 #ifndef __ASSEMBLY__
12 
mips_cache(int op,const volatile void * addr)13 static inline void mips_cache(int op, const volatile void *addr)
14 {
15 #ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
16 	__builtin_mips_cache(op, addr);
17 #else
18 	__asm__ __volatile__("cache %0, 0(%1)" : : "i"(op), "r"(addr));
19 #endif
20 }
21 
22 #define MIPS32_WHICH_ICACHE                    0x0
23 #define MIPS32_FETCH_AND_LOCK                  0x7
24 
25 #define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
26 
27 /* Prefetch and lock instructions into cache */
icache_lock(void * func,size_t len)28 static inline void icache_lock(void *func, size_t len)
29 {
30 	int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
31 
32 	for (i = 0; i < lines; i++) {
33 		asm volatile (" cache %0, %1(%2)"
34 			      : /* No Output */
35 			      : "I" ICACHE_LOAD_LOCK,
36 				"n" (i * ARCH_DMA_MINALIGN),
37 				"r" (func)
38 			      : /* No Clobbers */);
39 	}
40 }
41 #endif /* !__ASSEMBLY__ */
42 
43 /*
44  * Cache Operations available on all MIPS processors with R4000-style caches
45  */
46 #define INDEX_INVALIDATE_I      0x00
47 #define INDEX_WRITEBACK_INV_D   0x01
48 #define INDEX_LOAD_TAG_I	0x04
49 #define INDEX_LOAD_TAG_D	0x05
50 #define INDEX_STORE_TAG_I	0x08
51 #define INDEX_STORE_TAG_D	0x09
52 #if defined(CONFIG_CPU_LOONGSON2)
53 #define HIT_INVALIDATE_I	0x00
54 #else
55 #define HIT_INVALIDATE_I	0x10
56 #endif
57 #define HIT_INVALIDATE_D	0x11
58 #define HIT_WRITEBACK_INV_D	0x15
59 
60 /*
61  * R4000-specific cacheops
62  */
63 #define CREATE_DIRTY_EXCL_D	0x0d
64 #define FILL			0x14
65 #define HIT_WRITEBACK_I		0x18
66 #define HIT_WRITEBACK_D		0x19
67 
68 /*
69  * R4000SC and R4400SC-specific cacheops
70  */
71 #define INDEX_INVALIDATE_SI     0x02
72 #define INDEX_WRITEBACK_INV_SD  0x03
73 #define INDEX_LOAD_TAG_SI	0x06
74 #define INDEX_LOAD_TAG_SD	0x07
75 #define INDEX_STORE_TAG_SI	0x0A
76 #define INDEX_STORE_TAG_SD	0x0B
77 #define CREATE_DIRTY_EXCL_SD	0x0f
78 #define HIT_INVALIDATE_SI	0x12
79 #define HIT_INVALIDATE_SD	0x13
80 #define HIT_WRITEBACK_INV_SD	0x17
81 #define HIT_WRITEBACK_SD	0x1b
82 #define HIT_SET_VIRTUAL_SI	0x1e
83 #define HIT_SET_VIRTUAL_SD	0x1f
84 
85 /*
86  * R5000-specific cacheops
87  */
88 #define R5K_PAGE_INVALIDATE_S	0x17
89 
90 /*
91  * RM7000-specific cacheops
92  */
93 #define PAGE_INVALIDATE_T	0x16
94 
95 /*
96  * R10000-specific cacheops
97  *
98  * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
99  * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
100  */
101 #define INDEX_WRITEBACK_INV_S	0x03
102 #define INDEX_LOAD_TAG_S	0x07
103 #define INDEX_STORE_TAG_S	0x0B
104 #define HIT_INVALIDATE_S	0x13
105 #define CACHE_BARRIER		0x14
106 #define HIT_WRITEBACK_INV_S	0x17
107 #define INDEX_LOAD_DATA_I	0x18
108 #define INDEX_LOAD_DATA_D	0x19
109 #define INDEX_LOAD_DATA_S	0x1b
110 #define INDEX_STORE_DATA_I	0x1c
111 #define INDEX_STORE_DATA_D	0x1d
112 #define INDEX_STORE_DATA_S	0x1f
113 
114 #endif	/* __ASM_CACHEOPS_H */
115